process.hh revision 13166
16019Shines@cs.fsu.edu/* 213121Sgiacomo.travaglini@arm.com* Copyright (c) 2012, 2018 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 146019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Stephen Hines 416019Shines@cs.fsu.edu */ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#ifndef __ARM_PROCESS_HH__ 446019Shines@cs.fsu.edu#define __ARM_PROCESS_HH__ 456019Shines@cs.fsu.edu 466019Shines@cs.fsu.edu#include <string> 476019Shines@cs.fsu.edu#include <vector> 488229Snate@binkert.org 4910037SARM gem5 Developers#include "arch/arm/intregs.hh" 507096Sgblack@eecs.umich.edu#include "base/loader/object_file.hh" 5111800Sbrandon.potter@amd.com#include "mem/page_table.hh" 526019Shines@cs.fsu.edu#include "sim/process.hh" 536019Shines@cs.fsu.edu 546019Shines@cs.fsu.educlass ObjectFile; 556019Shines@cs.fsu.edu 5611851Sbrandon.potter@amd.comclass ArmProcess : public Process 576019Shines@cs.fsu.edu{ 586019Shines@cs.fsu.edu protected: 597096Sgblack@eecs.umich.edu ObjectFile::Arch arch; 6011851Sbrandon.potter@amd.com ArmProcess(ProcessParams * params, ObjectFile *objFile, 6111851Sbrandon.potter@amd.com ObjectFile::Arch _arch); 6210037SARM gem5 Developers template<class IntType> 6310037SARM gem5 Developers void argsInit(int pageSize, ArmISA::IntRegIndex spIndex); 6413121Sgiacomo.travaglini@arm.com 6513121Sgiacomo.travaglini@arm.com template<class IntType> 6613121Sgiacomo.travaglini@arm.com IntType armHwcap() const 6713121Sgiacomo.travaglini@arm.com { 6813121Sgiacomo.travaglini@arm.com return static_cast<IntType>(armHwcapImpl()); 6913121Sgiacomo.travaglini@arm.com } 7013121Sgiacomo.travaglini@arm.com 7113121Sgiacomo.travaglini@arm.com /** 7213121Sgiacomo.travaglini@arm.com * AT_HWCAP is 32-bit wide on AArch64 as well so we can 7313121Sgiacomo.travaglini@arm.com * safely return an uint32_t */ 7413121Sgiacomo.travaglini@arm.com virtual uint32_t armHwcapImpl() const = 0; 7510037SARM gem5 Developers}; 7610037SARM gem5 Developers 7711851Sbrandon.potter@amd.comclass ArmProcess32 : public ArmProcess 7810037SARM gem5 Developers{ 7910037SARM gem5 Developers protected: 8011851Sbrandon.potter@amd.com ArmProcess32(ProcessParams * params, ObjectFile *objFile, 8111851Sbrandon.potter@amd.com ObjectFile::Arch _arch); 826019Shines@cs.fsu.edu 8313166SMatteo.Andreozzi@arm.com void initState() override; 846019Shines@cs.fsu.edu 8513121Sgiacomo.travaglini@arm.com /** AArch32 AT_HWCAP */ 8613121Sgiacomo.travaglini@arm.com uint32_t armHwcapImpl() const override; 8713121Sgiacomo.travaglini@arm.com 886019Shines@cs.fsu.edu public: 8910037SARM gem5 Developers 9013166SMatteo.Andreozzi@arm.com ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width) override; 9113166SMatteo.Andreozzi@arm.com ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; 9213166SMatteo.Andreozzi@arm.com void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) override; 9313166SMatteo.Andreozzi@arm.com void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value) override; 9410037SARM gem5 Developers}; 9510037SARM gem5 Developers 9611851Sbrandon.potter@amd.comclass ArmProcess64 : public ArmProcess 9710037SARM gem5 Developers{ 9810037SARM gem5 Developers protected: 9911851Sbrandon.potter@amd.com ArmProcess64(ProcessParams * params, ObjectFile *objFile, 10011851Sbrandon.potter@amd.com ObjectFile::Arch _arch); 10110037SARM gem5 Developers 10213166SMatteo.Andreozzi@arm.com void initState() override; 10310037SARM gem5 Developers 10413121Sgiacomo.travaglini@arm.com /** AArch64 AT_HWCAP */ 10513121Sgiacomo.travaglini@arm.com uint32_t armHwcapImpl() const override; 10613121Sgiacomo.travaglini@arm.com 10710037SARM gem5 Developers public: 1086019Shines@cs.fsu.edu 10913166SMatteo.Andreozzi@arm.com ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width) override; 11013166SMatteo.Andreozzi@arm.com ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; 11113166SMatteo.Andreozzi@arm.com void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) override; 11213166SMatteo.Andreozzi@arm.com void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value) override; 1136019Shines@cs.fsu.edu}; 1146019Shines@cs.fsu.edu 1156019Shines@cs.fsu.edu#endif // __ARM_PROCESS_HH__ 1166019Shines@cs.fsu.edu 117