nativetrace.cc revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/arm/isa_traits.hh"
44#include "arch/arm/miscregs.hh"
45#include "arch/arm/nativetrace.hh"
46#include "cpu/thread_context.hh"
47#include "params/ArmNativeTrace.hh"
48#include "sim/byteswap.hh"
49
50namespace Trace {
51
52#if TRACING_ON
53static const char *regNames[] = {
54    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
55    "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
56    "cpsr"
57};
58#endif
59
60void
61Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
62{
63    oldState = state[current];
64    current = (current + 1) % 2;
65    newState = state[current];
66
67    memcpy(newState, oldState, sizeof(state[0]));
68
69    uint32_t diffVector;
70    parent->read(&diffVector, sizeof(diffVector));
71    diffVector = ArmISA::gtoh(diffVector);
72
73    int changes = 0;
74    for (int i = 0; i < STATE_NUMVALS; i++) {
75        if (diffVector & 0x1) {
76            changed[i] = true;
77            changes++;
78        } else {
79            changed[i] = false;
80        }
81        diffVector >>= 1;
82    }
83
84    uint32_t values[changes];
85    parent->read(values, sizeof(values));
86    int pos = 0;
87    for (int i = 0; i < STATE_NUMVALS; i++) {
88        if (changed[i]) {
89            newState[i] = ArmISA::gtoh(values[pos++]);
90            changed[i] = (newState[i] != oldState[i]);
91        }
92    }
93}
94
95void
96Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
97{
98    oldState = state[current];
99    current = (current + 1) % 2;
100    newState = state[current];
101
102    // Regular int regs
103    for (int i = 0; i < 15; i++) {
104        newState[i] = tc->readIntReg(i);
105        changed[i] = (oldState[i] != newState[i]);
106    }
107
108    //R15, aliased with the PC
109    newState[STATE_PC] = tc->pcState().npc();
110    changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
111
112    //CPSR
113    newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) |
114                           tc->readIntReg(INTREG_CONDCODES);
115    changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
116}
117
118void
119Trace::ArmNativeTrace::check(NativeTraceRecord *record)
120{
121    ThreadContext *tc = record->getThread();
122    // This area is read only on the target. It can't stop there to tell us
123    // what's going on, so we should skip over anything there also.
124    if (tc->nextInstAddr() > 0xffff0000)
125        return;
126    nState.update(this);
127    mState.update(tc);
128
129    // If a syscall just happened native trace needs another tick
130    if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
131            (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
132            DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
133            nState.update(this);
134
135    }
136
137    bool errorFound = false;
138    // Regular int regs
139    for (int i = 0; i < STATE_NUMVALS; i++) {
140        if (nState.changed[i] || mState.changed[i]) {
141            const char *vergence = "  ";
142            bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
143            bool newMatch = (mState.newState[i] == nState.newState[i]);
144            if (oldMatch && newMatch) {
145                // The more things change, the more they stay the same.
146                continue;
147            } else if (oldMatch && !newMatch) {
148                vergence = "<>";
149            } else if (!oldMatch && newMatch) {
150                vergence = "><";
151            }
152            errorFound = true;
153            if (!nState.changed[i]) {
154                DPRINTF(ExecRegDelta, "%s [%5s] "\
155                                      "Native:         %#010x         "\
156                                      "M5:     %#010x => %#010x\n",
157                                      vergence, regNames[i],
158                                      nState.newState[i],
159                                      mState.oldState[i], mState.newState[i]);
160            } else if (!mState.changed[i]) {
161                DPRINTF(ExecRegDelta, "%s [%5s] "\
162                                      "Native: %#010x => %#010x "\
163                                      "M5:             %#010x        \n",
164                                      vergence, regNames[i],
165                                      nState.oldState[i], nState.newState[i],
166                                      mState.newState[i]);
167            } else {
168                DPRINTF(ExecRegDelta, "%s [%5s] "\
169                                      "Native: %#010x => %#010x "\
170                                      "M5:     %#010x => %#010x\n",
171                                      vergence, regNames[i],
172                                      nState.oldState[i], nState.newState[i],
173                                      mState.oldState[i], mState.newState[i]);
174            }
175        }
176    }
177    if (errorFound) {
178        StaticInstPtr inst = record->getStaticInst();
179        assert(inst);
180        bool ran = true;
181        if (inst->isMicroop()) {
182            ran = false;
183            inst = record->getMacroStaticInst();
184        }
185        assert(inst);
186        record->traceInst(inst, ran);
187
188        bool pcError = (mState.newState[STATE_PC] !=
189                        nState.newState[STATE_PC]);
190        if (stopOnPCError && pcError)
191            panic("Native trace detected an error in control flow!");
192    }
193}
194
195} /* namespace Trace */
196
197////////////////////////////////////////////////////////////////////////
198//
199//  ExeTracer Simulation Object
200//
201Trace::ArmNativeTrace *
202ArmNativeTraceParams::create()
203{
204    return new Trace::ArmNativeTrace(this);
205};
206