nativetrace.cc revision 6411:cf69f61d8f24
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/arm/isa_traits.hh" 32#include "arch/arm/miscregs.hh" 33#include "arch/arm/nativetrace.hh" 34#include "cpu/thread_context.hh" 35#include "params/ArmNativeTrace.hh" 36 37namespace Trace { 38 39#if TRACING_ON 40static const char *regNames[] = { 41 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 42 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", 43 "cpsr" 44}; 45#endif 46 47void 48Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent) 49{ 50 oldState = state[current]; 51 current = (current + 1) % 2; 52 newState = state[current]; 53 54 memcpy(newState, oldState, sizeof(state[0])); 55 56 uint32_t diffVector; 57 parent->read(&diffVector, sizeof(diffVector)); 58 diffVector = ArmISA::gtoh(diffVector); 59 60 int changes = 0; 61 for (int i = 0; i < STATE_NUMVALS; i++) { 62 if (diffVector & 0x1) { 63 changed[i] = true; 64 changes++; 65 } else { 66 changed[i] = false; 67 } 68 diffVector >>= 1; 69 } 70 71 uint32_t values[changes]; 72 parent->read(values, sizeof(values)); 73 int pos = 0; 74 for (int i = 0; i < STATE_NUMVALS; i++) { 75 if (changed[i]) { 76 newState[i] = ArmISA::gtoh(values[pos++]); 77 changed[i] = (newState[i] != oldState[i]); 78 } 79 } 80} 81 82void 83Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) 84{ 85 oldState = state[current]; 86 current = (current + 1) % 2; 87 newState = state[current]; 88 89 // Regular int regs 90 for (int i = 0; i < 15; i++) { 91 newState[i] = tc->readIntReg(i); 92 changed[i] = (oldState[i] != newState[i]); 93 } 94 95 //R15, aliased with the PC 96 newState[STATE_PC] = tc->readNextPC(); 97 changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]); 98 99 //CPSR 100 newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR); 101 changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); 102} 103 104void 105Trace::ArmNativeTrace::check(NativeTraceRecord *record) 106{ 107 nState.update(this); 108 mState.update(record->getThread()); 109 110 bool errorFound = false; 111 // Regular int regs 112 for (int i = 0; i < STATE_NUMVALS; i++) { 113 if (nState.changed[i] || mState.changed[i]) { 114 const char *vergence = " "; 115 bool oldMatch = (mState.oldState[i] == nState.oldState[i]); 116 bool newMatch = (mState.newState[i] == nState.newState[i]); 117 if (oldMatch && newMatch) { 118 // The more things change, the more they stay the same. 119 continue; 120 } else if (oldMatch && !newMatch) { 121 vergence = "<>"; 122 } else if (!oldMatch && newMatch) { 123 vergence = "><"; 124 } 125 errorFound = true; 126 if (!nState.changed[i]) { 127 DPRINTF(ExecRegDelta, "%s [%5s] "\ 128 "Native: %#010x "\ 129 "M5: %#010x => %#010x\n", 130 vergence, regNames[i], 131 nState.newState[i], 132 mState.oldState[i], mState.newState[i]); 133 } else if (!mState.changed[i]) { 134 DPRINTF(ExecRegDelta, "%s [%5s] "\ 135 "Native: %#010x => %#010x "\ 136 "M5: %#010x \n", 137 vergence, regNames[i], 138 nState.oldState[i], nState.newState[i], 139 mState.newState[i]); 140 } else { 141 DPRINTF(ExecRegDelta, "%s [%5s] "\ 142 "Native: %#010x => %#010x "\ 143 "M5: %#010x => %#010x\n", 144 vergence, regNames[i], 145 nState.oldState[i], nState.newState[i], 146 mState.oldState[i], mState.newState[i]); 147 } 148 } 149 } 150 if (errorFound) { 151 StaticInstPtr inst = record->getStaticInst(); 152 assert(inst); 153 bool ran = true; 154 if (inst->isMicroop()) { 155 ran = false; 156 inst = record->getMacroStaticInst(); 157 } 158 assert(inst); 159 record->traceInst(inst, ran); 160 } 161} 162 163} /* namespace Trace */ 164 165//////////////////////////////////////////////////////////////////////// 166// 167// ExeTracer Simulation Object 168// 169Trace::ArmNativeTrace * 170ArmNativeTraceParams::create() 171{ 172 return new Trace::ArmNativeTrace(this); 173}; 174