nativetrace.cc revision 7811
14776SN/A/* 27414SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37414SAli.Saidi@ARM.com * All rights reserved 47414SAli.Saidi@ARM.com * 57414SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67414SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77414SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87414SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97414SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107414SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117414SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127414SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137414SAli.Saidi@ARM.com * 146365SN/A * Copyright (c) 2006 The Regents of The University of Michigan 154776SN/A * All rights reserved. 164776SN/A * 174776SN/A * Redistribution and use in source and binary forms, with or without 184776SN/A * modification, are permitted provided that the following conditions are 194776SN/A * met: redistributions of source code must retain the above copyright 204776SN/A * notice, this list of conditions and the following disclaimer; 214776SN/A * redistributions in binary form must reproduce the above copyright 224776SN/A * notice, this list of conditions and the following disclaimer in the 234776SN/A * documentation and/or other materials provided with the distribution; 244776SN/A * neither the name of the copyright holders nor the names of its 254776SN/A * contributors may be used to endorse or promote products derived from 264776SN/A * this software without specific prior written permission. 274776SN/A * 284776SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294776SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304776SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314776SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324776SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334776SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344776SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354776SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364776SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374776SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384776SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394776SN/A * 406365SN/A * Authors: Gabe Black 414776SN/A */ 424776SN/A 436397Sgblack@eecs.umich.edu#include "arch/arm/isa_traits.hh" 446397Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 456397Sgblack@eecs.umich.edu#include "arch/arm/nativetrace.hh" 464776SN/A#include "cpu/thread_context.hh" 476397Sgblack@eecs.umich.edu#include "params/ArmNativeTrace.hh" 487678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 494776SN/A 504776SN/Anamespace Trace { 514776SN/A 526398Sgblack@eecs.umich.edu#if TRACING_ON 536397Sgblack@eecs.umich.edustatic const char *regNames[] = { 546397Sgblack@eecs.umich.edu "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 556397Sgblack@eecs.umich.edu "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", 566397Sgblack@eecs.umich.edu "cpsr" 576365SN/A}; 586398Sgblack@eecs.umich.edu#endif 596398Sgblack@eecs.umich.edu 606398Sgblack@eecs.umich.eduvoid 616398Sgblack@eecs.umich.eduTrace::ArmNativeTrace::ThreadState::update(NativeTrace *parent) 626398Sgblack@eecs.umich.edu{ 636398Sgblack@eecs.umich.edu oldState = state[current]; 646398Sgblack@eecs.umich.edu current = (current + 1) % 2; 656398Sgblack@eecs.umich.edu newState = state[current]; 666398Sgblack@eecs.umich.edu 676411Sgblack@eecs.umich.edu memcpy(newState, oldState, sizeof(state[0])); 686411Sgblack@eecs.umich.edu 696411Sgblack@eecs.umich.edu uint32_t diffVector; 706411Sgblack@eecs.umich.edu parent->read(&diffVector, sizeof(diffVector)); 716411Sgblack@eecs.umich.edu diffVector = ArmISA::gtoh(diffVector); 726411Sgblack@eecs.umich.edu 736411Sgblack@eecs.umich.edu int changes = 0; 746398Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 756411Sgblack@eecs.umich.edu if (diffVector & 0x1) { 766411Sgblack@eecs.umich.edu changed[i] = true; 776411Sgblack@eecs.umich.edu changes++; 786411Sgblack@eecs.umich.edu } else { 796411Sgblack@eecs.umich.edu changed[i] = false; 806411Sgblack@eecs.umich.edu } 816411Sgblack@eecs.umich.edu diffVector >>= 1; 826411Sgblack@eecs.umich.edu } 836411Sgblack@eecs.umich.edu 846411Sgblack@eecs.umich.edu uint32_t values[changes]; 856411Sgblack@eecs.umich.edu parent->read(values, sizeof(values)); 866411Sgblack@eecs.umich.edu int pos = 0; 876411Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 886411Sgblack@eecs.umich.edu if (changed[i]) { 896411Sgblack@eecs.umich.edu newState[i] = ArmISA::gtoh(values[pos++]); 906411Sgblack@eecs.umich.edu changed[i] = (newState[i] != oldState[i]); 916411Sgblack@eecs.umich.edu } 926398Sgblack@eecs.umich.edu } 936398Sgblack@eecs.umich.edu} 946398Sgblack@eecs.umich.edu 956398Sgblack@eecs.umich.eduvoid 966398Sgblack@eecs.umich.eduTrace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) 976398Sgblack@eecs.umich.edu{ 986398Sgblack@eecs.umich.edu oldState = state[current]; 996398Sgblack@eecs.umich.edu current = (current + 1) % 2; 1006398Sgblack@eecs.umich.edu newState = state[current]; 1016398Sgblack@eecs.umich.edu 1026398Sgblack@eecs.umich.edu // Regular int regs 1036398Sgblack@eecs.umich.edu for (int i = 0; i < 15; i++) { 1046398Sgblack@eecs.umich.edu newState[i] = tc->readIntReg(i); 1056398Sgblack@eecs.umich.edu changed[i] = (oldState[i] != newState[i]); 1066398Sgblack@eecs.umich.edu } 1076398Sgblack@eecs.umich.edu 1086398Sgblack@eecs.umich.edu //R15, aliased with the PC 1097720Sgblack@eecs.umich.edu newState[STATE_PC] = tc->pcState().npc(); 1106398Sgblack@eecs.umich.edu changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]); 1116398Sgblack@eecs.umich.edu 1126398Sgblack@eecs.umich.edu //CPSR 1136724Sgblack@eecs.umich.edu newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) | 1146724Sgblack@eecs.umich.edu tc->readIntReg(INTREG_CONDCODES); 1156398Sgblack@eecs.umich.edu changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); 1166398Sgblack@eecs.umich.edu} 1176365SN/A 1186365SN/Avoid 1196397Sgblack@eecs.umich.eduTrace::ArmNativeTrace::check(NativeTraceRecord *record) 1204776SN/A{ 1216417Sgblack@eecs.umich.edu ThreadContext *tc = record->getThread(); 1226417Sgblack@eecs.umich.edu // This area is read only on the target. It can't stop there to tell us 1236417Sgblack@eecs.umich.edu // what's going on, so we should skip over anything there also. 1247720Sgblack@eecs.umich.edu if (tc->nextInstAddr() > 0xffff0000) 1256417Sgblack@eecs.umich.edu return; 1266398Sgblack@eecs.umich.edu nState.update(this); 1276417Sgblack@eecs.umich.edu mState.update(tc); 1285523SN/A 1297414SAli.Saidi@ARM.com // If a syscall just happened native trace needs another tick 1307414SAli.Saidi@ARM.com if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) && 1317414SAli.Saidi@ARM.com (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) { 1327414SAli.Saidi@ARM.com DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n"); 1337414SAli.Saidi@ARM.com nState.update(this); 1347414SAli.Saidi@ARM.com 1357414SAli.Saidi@ARM.com } 1367414SAli.Saidi@ARM.com 1376409Sgblack@eecs.umich.edu bool errorFound = false; 1386397Sgblack@eecs.umich.edu // Regular int regs 1396398Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 1406398Sgblack@eecs.umich.edu if (nState.changed[i] || mState.changed[i]) { 1416398Sgblack@eecs.umich.edu const char *vergence = " "; 1426410Sgblack@eecs.umich.edu bool oldMatch = (mState.oldState[i] == nState.oldState[i]); 1436410Sgblack@eecs.umich.edu bool newMatch = (mState.newState[i] == nState.newState[i]); 1446410Sgblack@eecs.umich.edu if (oldMatch && newMatch) { 1456410Sgblack@eecs.umich.edu // The more things change, the more they stay the same. 1466410Sgblack@eecs.umich.edu continue; 1476410Sgblack@eecs.umich.edu } else if (oldMatch && !newMatch) { 1486398Sgblack@eecs.umich.edu vergence = "<>"; 1496410Sgblack@eecs.umich.edu } else if (!oldMatch && newMatch) { 1506398Sgblack@eecs.umich.edu vergence = "><"; 1516398Sgblack@eecs.umich.edu } 1526410Sgblack@eecs.umich.edu errorFound = true; 1536398Sgblack@eecs.umich.edu if (!nState.changed[i]) { 1546398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1556398Sgblack@eecs.umich.edu "Native: %#010x "\ 1566398Sgblack@eecs.umich.edu "M5: %#010x => %#010x\n", 1576398Sgblack@eecs.umich.edu vergence, regNames[i], 1586398Sgblack@eecs.umich.edu nState.newState[i], 1596398Sgblack@eecs.umich.edu mState.oldState[i], mState.newState[i]); 1606398Sgblack@eecs.umich.edu } else if (!mState.changed[i]) { 1616398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1626398Sgblack@eecs.umich.edu "Native: %#010x => %#010x "\ 1636398Sgblack@eecs.umich.edu "M5: %#010x \n", 1646398Sgblack@eecs.umich.edu vergence, regNames[i], 1656398Sgblack@eecs.umich.edu nState.oldState[i], nState.newState[i], 1666398Sgblack@eecs.umich.edu mState.newState[i]); 1676410Sgblack@eecs.umich.edu } else { 1686398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1696398Sgblack@eecs.umich.edu "Native: %#010x => %#010x "\ 1706398Sgblack@eecs.umich.edu "M5: %#010x => %#010x\n", 1716398Sgblack@eecs.umich.edu vergence, regNames[i], 1726398Sgblack@eecs.umich.edu nState.oldState[i], nState.newState[i], 1736398Sgblack@eecs.umich.edu mState.oldState[i], mState.newState[i]); 1746398Sgblack@eecs.umich.edu } 1756398Sgblack@eecs.umich.edu } 1764776SN/A } 1776409Sgblack@eecs.umich.edu if (errorFound) { 1786409Sgblack@eecs.umich.edu StaticInstPtr inst = record->getStaticInst(); 1796409Sgblack@eecs.umich.edu assert(inst); 1806409Sgblack@eecs.umich.edu bool ran = true; 1816409Sgblack@eecs.umich.edu if (inst->isMicroop()) { 1826409Sgblack@eecs.umich.edu ran = false; 1836409Sgblack@eecs.umich.edu inst = record->getMacroStaticInst(); 1846409Sgblack@eecs.umich.edu } 1856409Sgblack@eecs.umich.edu assert(inst); 1866409Sgblack@eecs.umich.edu record->traceInst(inst, ran); 1876419Sgblack@eecs.umich.edu 1886419Sgblack@eecs.umich.edu bool pcError = (mState.newState[STATE_PC] != 1896419Sgblack@eecs.umich.edu nState.newState[STATE_PC]); 1906419Sgblack@eecs.umich.edu if (stopOnPCError && pcError) 1916419Sgblack@eecs.umich.edu panic("Native trace detected an error in control flow!"); 1926409Sgblack@eecs.umich.edu } 1934776SN/A} 1944776SN/A 1957811Ssteve.reinhardt@amd.com} // namespace Trace 1964776SN/A 1974776SN/A//////////////////////////////////////////////////////////////////////// 1984776SN/A// 1994776SN/A// ExeTracer Simulation Object 2004776SN/A// 2016397Sgblack@eecs.umich.eduTrace::ArmNativeTrace * 2026397Sgblack@eecs.umich.eduArmNativeTraceParams::create() 2034776SN/A{ 2046397Sgblack@eecs.umich.edu return new Trace::ArmNativeTrace(this); 2054776SN/A}; 206