miscregs.hh revision 9256:f14188a5a1d6
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 45#include "base/bitunion.hh" 46#include "base/compiler.hh" 47 48namespace ArmISA 49{ 50 enum ConditionCode { 51 COND_EQ = 0, 52 COND_NE, // 1 53 COND_CS, // 2 54 COND_CC, // 3 55 COND_MI, // 4 56 COND_PL, // 5 57 COND_VS, // 6 58 COND_VC, // 7 59 COND_HI, // 8 60 COND_LS, // 9 61 COND_GE, // 10 62 COND_LT, // 11 63 COND_GT, // 12 64 COND_LE, // 13 65 COND_AL, // 14 66 COND_UC // 15 67 }; 68 69 enum MiscRegIndex { 70 MISCREG_CPSR = 0, 71 MISCREG_CPSR_Q, 72 MISCREG_SPSR, 73 MISCREG_SPSR_FIQ, 74 MISCREG_SPSR_IRQ, 75 MISCREG_SPSR_SVC, 76 MISCREG_SPSR_MON, 77 MISCREG_SPSR_UND, 78 MISCREG_SPSR_ABT, 79 MISCREG_FPSR, 80 MISCREG_FPSID, 81 MISCREG_FPSCR, 82 MISCREG_FPSCR_QC, // Cumulative saturation flag 83 MISCREG_FPSCR_EXC, // Cumulative FP exception flags 84 MISCREG_FPEXC, 85 MISCREG_MVFR0, 86 MISCREG_MVFR1, 87 MISCREG_SCTLR_RST, 88 MISCREG_SEV_MAILBOX, 89 90 // CP14 registers 91 MISCREG_CP14_START, 92 MISCREG_DBGDIDR = MISCREG_CP14_START, 93 MISCREG_DBGDSCR_INT, 94 MISCREG_DBGDTRRX_INT, 95 MISCREG_DBGTRTX_INT, 96 MISCREG_DBGWFAR, 97 MISCREG_DBGVCR, 98 MISCREG_DBGECR, 99 MISCREG_DBGDSCCR, 100 MISCREG_DBGSMCR, 101 MISCREG_DBGDTRRX_EXT, 102 MISCREG_DBGDSCR_EXT, 103 MISCREG_DBGDTRTX_EXT, 104 MISCREG_DBGDRCR, 105 MISCREG_DBGBVR, 106 MISCREG_DBGBCR, 107 MISCREG_DBGBVR_M, 108 MISCREG_DBGBCR_M, 109 MISCREG_DBGDRAR, 110 MISCREG_DBGBXVR_M, 111 MISCREG_DBGOSLAR, 112 MISCREG_DBGOSSRR, 113 MISCREG_DBGOSDLR, 114 MISCREG_DBGPRCR, 115 MISCREG_DBGPRSR, 116 MISCREG_DBGDSAR, 117 MISCREG_DBGITCTRL, 118 MISCREG_DBGCLAIMSET, 119 MISCREG_DBGCLAIMCLR, 120 MISCREG_DBGAUTHSTATUS, 121 MISCREG_DBGDEVID2, 122 MISCREG_DBGDEVID1, 123 MISCREG_DBGDEVID, 124 125 // CP15 registers 126 MISCREG_CP15_START, 127 MISCREG_SCTLR = MISCREG_CP15_START, 128 MISCREG_DCCISW, 129 MISCREG_DCCIMVAC, 130 MISCREG_DCCMVAC, 131 MISCREG_CONTEXTIDR, 132 MISCREG_TPIDRURW, 133 MISCREG_TPIDRURO, 134 MISCREG_TPIDRPRW, 135 MISCREG_CP15ISB, 136 MISCREG_CP15DSB, 137 MISCREG_CP15DMB, 138 MISCREG_CPACR, 139 MISCREG_CLIDR, 140 MISCREG_CCSIDR, 141 MISCREG_CSSELR, 142 MISCREG_ICIALLUIS, 143 MISCREG_ICIALLU, 144 MISCREG_ICIMVAU, 145 MISCREG_BPIMVA, 146 MISCREG_BPIALLIS, 147 MISCREG_BPIALL, 148 MISCREG_MIDR, 149 MISCREG_TTBR0, 150 MISCREG_TTBR1, 151 MISCREG_TLBTR, 152 MISCREG_DACR, 153 MISCREG_TLBIALLIS, 154 MISCREG_TLBIMVAIS, 155 MISCREG_TLBIASIDIS, 156 MISCREG_TLBIMVAAIS, 157 MISCREG_ITLBIALL, 158 MISCREG_ITLBIMVA, 159 MISCREG_ITLBIASID, 160 MISCREG_DTLBIALL, 161 MISCREG_DTLBIMVA, 162 MISCREG_DTLBIASID, 163 MISCREG_TLBIALL, 164 MISCREG_TLBIMVA, 165 MISCREG_TLBIASID, 166 MISCREG_TLBIMVAA, 167 MISCREG_DFSR, 168 MISCREG_IFSR, 169 MISCREG_DFAR, 170 MISCREG_IFAR, 171 MISCREG_MPIDR, 172 MISCREG_PRRR, 173 MISCREG_NMRR, 174 MISCREG_TTBCR, 175 MISCREG_ID_PFR0, 176 MISCREG_CTR, 177 MISCREG_SCR, 178 MISCREG_SDER, 179 MISCREG_PAR, 180 MISCREG_V2PCWPR, 181 MISCREG_V2PCWPW, 182 MISCREG_V2PCWUR, 183 MISCREG_V2PCWUW, 184 MISCREG_V2POWPR, 185 MISCREG_V2POWPW, 186 MISCREG_V2POWUR, 187 MISCREG_V2POWUW, 188 MISCREG_ID_MMFR0, 189 MISCREG_ID_MMFR2, 190 MISCREG_ID_MMFR3, 191 MISCREG_ACTLR, 192 MISCREG_PMCR, 193 MISCREG_PMCCNTR, 194 MISCREG_PMCNTENSET, 195 MISCREG_PMCNTENCLR, 196 MISCREG_PMOVSR, 197 MISCREG_PMSWINC, 198 MISCREG_PMSELR, 199 MISCREG_PMCEID0, 200 MISCREG_PMCEID1, 201 MISCREG_PMC_OTHER, 202 MISCREG_PMXEVCNTR, 203 MISCREG_PMUSERENR, 204 MISCREG_PMINTENSET, 205 MISCREG_PMINTENCLR, 206 MISCREG_ID_ISAR0, 207 MISCREG_ID_ISAR1, 208 MISCREG_ID_ISAR2, 209 MISCREG_ID_ISAR3, 210 MISCREG_ID_ISAR4, 211 MISCREG_ID_ISAR5, 212 MISCREG_CPSR_MODE, 213 MISCREG_LOCKFLAG, 214 MISCREG_LOCKADDR, 215 MISCREG_ID_PFR1, 216 MISCREG_L2CTLR, 217 MISCREG_CP15_UNIMP_START, 218 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 219 MISCREG_ID_DFR0, 220 MISCREG_ID_AFR0, 221 MISCREG_ID_MMFR1, 222 MISCREG_AIDR, 223 MISCREG_ADFSR, 224 MISCREG_AIFSR, 225 MISCREG_DCIMVAC, 226 MISCREG_DCISW, 227 MISCREG_MCCSW, 228 MISCREG_DCCMVAU, 229 MISCREG_NSACR, 230 MISCREG_VBAR, 231 MISCREG_MVBAR, 232 MISCREG_ISR, 233 MISCREG_FCEIDR, 234 MISCREG_L2LATENCY, 235 MISCREG_CRN15, 236 237 238 MISCREG_CP15_END, 239 240 // Dummy indices 241 MISCREG_NOP = MISCREG_CP15_END, 242 MISCREG_RAZ, 243 244 NUM_MISCREGS 245 }; 246 247 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 248 unsigned crm, unsigned opc2); 249 250 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 251 unsigned crm, unsigned opc2); 252 253 254 const char * const miscRegName[] = { 255 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 256 "spsr_mon", "spsr_und", "spsr_abt", 257 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 258 "mvfr0", "mvfr1", 259 "sctlr_rst", "sev_mailbox", 260 "DBGDIDR", 261 "DBGDSCR_INT", 262 "DBGDTRRX_INT", 263 "DBGTRTX_INT", 264 "DBGWFAR", 265 "DBGVCR", 266 "DBGECR", 267 "DBGDSCCR", 268 "DBGSMCR", 269 "DBGDTRRX_EXT", 270 "DBGDSCR_EXT", 271 "DBGDTRTX_EXT", 272 "DBGDRCR", 273 "DBGBVR", 274 "DBGBCR", 275 "DBGBVR_M", 276 "DBGBCR_M", 277 "DBGDRAR", 278 "DBGBXVR_M", 279 "DBGOSLAR", 280 "DBGOSSRR", 281 "DBGOSDLR", 282 "DBGPRCR", 283 "DBGPRSR", 284 "DBGDSAR", 285 "DBGITCTRL", 286 "DBGCLAIMSET", 287 "DBGCLAIMCLR", 288 "DBGAUTHSTATUS", 289 "DBGDEVID2", 290 "DBGDEVID1", 291 "DBGDEVID", 292 "sctlr", "dccisw", "dccimvac", "dccmvac", 293 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 294 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 295 "clidr", "ccsidr", "csselr", 296 "icialluis", "iciallu", "icimvau", 297 "bpimva", "bpiallis", "bpiall", 298 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 299 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 300 "itlbiall", "itlbimva", "itlbiasid", 301 "dtlbiall", "dtlbimva", "dtlbiasid", 302 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 303 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 304 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 305 "scr", "sder", "par", 306 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 307 "v2powpr", "v2powpw", "v2powur", "v2powuw", 308 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr", 309 "pmcntenset", "pmcntenclr", "pmovsr", 310 "pmswinc", "pmselr", "pmceid0", 311 "pmceid1", "pmc_other", "pmxevcntr", 312 "pmuserenr", "pmintenset", "pmintenclr", 313 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 314 "cpsr_mode", "lockflag", "lockaddr", "id_pfr1", 315 "l2ctlr", 316 // Unimplemented below 317 "tcmtr", 318 "id_dfr0", "id_afr0", 319 "id_mmfr1", 320 "aidr", "adfsr", "aifsr", 321 "dcimvac", "dcisw", "mccsw", 322 "dccmvau", 323 "nsacr", 324 "vbar", "mvbar", "isr", "fceidr", "l2latency", 325 "crn15", 326 "nop", "raz" 327 }; 328 329 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 330 "The miscRegName array and NUM_MISCREGS are inconsistent."); 331 332 BitUnion32(CPSR) 333 Bitfield<31,30> nz; 334 Bitfield<29> c; 335 Bitfield<28> v; 336 Bitfield<27> q; 337 Bitfield<26,25> it1; 338 Bitfield<24> j; 339 Bitfield<19, 16> ge; 340 Bitfield<15,10> it2; 341 Bitfield<9> e; 342 Bitfield<8> a; 343 Bitfield<7> i; 344 Bitfield<6> f; 345 Bitfield<5> t; 346 Bitfield<4, 0> mode; 347 EndBitUnion(CPSR) 348 349 // This mask selects bits of the CPSR that actually go in the CondCodes 350 // integer register to allow renaming. 351 static const uint32_t CondCodesMask = 0xF00F0000; 352 static const uint32_t CpsrMaskQ = 0x08000000; 353 354 BitUnion32(SCTLR) 355 Bitfield<31> ie; // Instruction endianness 356 Bitfield<30> te; // Thumb Exception Enable 357 Bitfield<29> afe; // Access flag enable 358 Bitfield<28> tre; // TEX Remap bit 359 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 360 Bitfield<25> ee; // Exception Endianness bit 361 Bitfield<24> ve; // Interrupt vectors enable 362 Bitfield<23> xp; // Extended page table enable bit 363 Bitfield<22> u; // Alignment (now unused) 364 Bitfield<21> fi; // Fast interrupts configuration enable 365 Bitfield<19> dz; // Divide by Zero fault enable bit 366 Bitfield<18> rao2;// Read as one 367 Bitfield<17> br; // Background region bit 368 Bitfield<16> rao3;// Read as one 369 Bitfield<14> rr; // Round robin cache replacement 370 Bitfield<13> v; // Base address for exception vectors 371 Bitfield<12> i; // instruction cache enable 372 Bitfield<11> z; // branch prediction enable bit 373 Bitfield<10> sw; // Enable swp/swpb 374 Bitfield<9,8> rs; // deprecated protection bits 375 Bitfield<6,3> rao4;// Read as one 376 Bitfield<7> b; // Endianness support (unused) 377 Bitfield<2> c; // Cache enable bit 378 Bitfield<1> a; // Alignment fault checking 379 Bitfield<0> m; // MMU enable bit 380 EndBitUnion(SCTLR) 381 382 BitUnion32(CPACR) 383 Bitfield<1, 0> cp0; 384 Bitfield<3, 2> cp1; 385 Bitfield<5, 4> cp2; 386 Bitfield<7, 6> cp3; 387 Bitfield<9, 8> cp4; 388 Bitfield<11, 10> cp5; 389 Bitfield<13, 12> cp6; 390 Bitfield<15, 14> cp7; 391 Bitfield<17, 16> cp8; 392 Bitfield<19, 18> cp9; 393 Bitfield<21, 20> cp10; 394 Bitfield<23, 22> cp11; 395 Bitfield<25, 24> cp12; 396 Bitfield<27, 26> cp13; 397 Bitfield<29, 28> rsvd; 398 Bitfield<30> d32dis; 399 Bitfield<31> asedis; 400 EndBitUnion(CPACR) 401 402 BitUnion32(FSR) 403 Bitfield<3, 0> fsLow; 404 Bitfield<7, 4> domain; 405 Bitfield<10> fsHigh; 406 Bitfield<11> wnr; 407 Bitfield<12> ext; 408 EndBitUnion(FSR) 409 410 BitUnion32(FPSCR) 411 Bitfield<0> ioc; 412 Bitfield<1> dzc; 413 Bitfield<2> ofc; 414 Bitfield<3> ufc; 415 Bitfield<4> ixc; 416 Bitfield<7> idc; 417 Bitfield<8> ioe; 418 Bitfield<9> dze; 419 Bitfield<10> ofe; 420 Bitfield<11> ufe; 421 Bitfield<12> ixe; 422 Bitfield<15> ide; 423 Bitfield<18, 16> len; 424 Bitfield<21, 20> stride; 425 Bitfield<23, 22> rMode; 426 Bitfield<24> fz; 427 Bitfield<25> dn; 428 Bitfield<26> ahp; 429 Bitfield<27> qc; 430 Bitfield<28> v; 431 Bitfield<29> c; 432 Bitfield<30> z; 433 Bitfield<31> n; 434 EndBitUnion(FPSCR) 435 436 // This mask selects bits of the FPSCR that actually go in the FpCondCodes 437 // integer register to allow renaming. 438 static const uint32_t FpCondCodesMask = 0xF0000000; 439 // This mask selects the cumulative FP exception flags of the FPSCR. 440 static const uint32_t FpscrExcMask = 0x0000009F; 441 // This mask selects the cumulative saturation flag of the FPSCR. 442 static const uint32_t FpscrQcMask = 0x08000000; 443 444 BitUnion32(FPEXC) 445 Bitfield<31> ex; 446 Bitfield<30> en; 447 Bitfield<29, 0> subArchDefined; 448 EndBitUnion(FPEXC) 449 450 BitUnion32(MVFR0) 451 Bitfield<3, 0> advSimdRegisters; 452 Bitfield<7, 4> singlePrecision; 453 Bitfield<11, 8> doublePrecision; 454 Bitfield<15, 12> vfpExceptionTrapping; 455 Bitfield<19, 16> divide; 456 Bitfield<23, 20> squareRoot; 457 Bitfield<27, 24> shortVectors; 458 Bitfield<31, 28> roundingModes; 459 EndBitUnion(MVFR0) 460 461 BitUnion32(MVFR1) 462 Bitfield<3, 0> flushToZero; 463 Bitfield<7, 4> defaultNaN; 464 Bitfield<11, 8> advSimdLoadStore; 465 Bitfield<15, 12> advSimdInteger; 466 Bitfield<19, 16> advSimdSinglePrecision; 467 Bitfield<23, 20> advSimdHalfPrecision; 468 Bitfield<27, 24> vfpHalfPrecision; 469 Bitfield<31, 28> raz; 470 EndBitUnion(MVFR1) 471 472 BitUnion32(PRRR) 473 Bitfield<1,0> tr0; 474 Bitfield<3,2> tr1; 475 Bitfield<5,4> tr2; 476 Bitfield<7,6> tr3; 477 Bitfield<9,8> tr4; 478 Bitfield<11,10> tr5; 479 Bitfield<13,12> tr6; 480 Bitfield<15,14> tr7; 481 Bitfield<16> ds0; 482 Bitfield<17> ds1; 483 Bitfield<18> ns0; 484 Bitfield<19> ns1; 485 Bitfield<24> nos0; 486 Bitfield<25> nos1; 487 Bitfield<26> nos2; 488 Bitfield<27> nos3; 489 Bitfield<28> nos4; 490 Bitfield<29> nos5; 491 Bitfield<30> nos6; 492 Bitfield<31> nos7; 493 EndBitUnion(PRRR) 494 495 BitUnion32(NMRR) 496 Bitfield<1,0> ir0; 497 Bitfield<3,2> ir1; 498 Bitfield<5,4> ir2; 499 Bitfield<7,6> ir3; 500 Bitfield<9,8> ir4; 501 Bitfield<11,10> ir5; 502 Bitfield<13,12> ir6; 503 Bitfield<15,14> ir7; 504 Bitfield<17,16> or0; 505 Bitfield<19,18> or1; 506 Bitfield<21,20> or2; 507 Bitfield<23,22> or3; 508 Bitfield<25,24> or4; 509 Bitfield<27,26> or5; 510 Bitfield<29,28> or6; 511 Bitfield<31,30> or7; 512 EndBitUnion(NMRR) 513 514 BitUnion32(CONTEXTIDR) 515 Bitfield<7,0> asid; 516 Bitfield<31,8> procid; 517 EndBitUnion(CONTEXTIDR) 518 519 BitUnion32(L2CTLR) 520 Bitfield<2,0> sataRAMLatency; 521 Bitfield<4,3> reserved_4_3; 522 Bitfield<5> dataRAMSetup; 523 Bitfield<8,6> tagRAMLatency; 524 Bitfield<9> tagRAMSetup; 525 Bitfield<11,10> dataRAMSlice; 526 Bitfield<12> tagRAMSlice; 527 Bitfield<20,13> reserved_20_13; 528 Bitfield<21> eccandParityEnable; 529 Bitfield<22> reserved_22; 530 Bitfield<23> interptCtrlPresent; 531 Bitfield<25,24> numCPUs; 532 Bitfield<30,26> reserved_30_26; 533 Bitfield<31> l2rstDISABLE_monitor; 534 EndBitUnion(L2CTLR) 535 536 BitUnion32(CTR) 537 Bitfield<3,0> iCacheLineSize; 538 Bitfield<13,4> raz_13_4; 539 Bitfield<15,14> l1IndexPolicy; 540 Bitfield<19,16> dCacheLineSize; 541 Bitfield<23,20> erg; 542 Bitfield<27,24> cwg; 543 Bitfield<28> raz_28; 544 Bitfield<31,29> format; 545 EndBitUnion(CTR) 546} 547 548#endif // __ARCH_ARM_MISCREGS_HH__ 549