miscregs.hh revision 9051:1554b7722990
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 45#include "base/bitunion.hh" 46 47namespace ArmISA 48{ 49 enum ConditionCode { 50 COND_EQ = 0, 51 COND_NE, // 1 52 COND_CS, // 2 53 COND_CC, // 3 54 COND_MI, // 4 55 COND_PL, // 5 56 COND_VS, // 6 57 COND_VC, // 7 58 COND_HI, // 8 59 COND_LS, // 9 60 COND_GE, // 10 61 COND_LT, // 11 62 COND_GT, // 12 63 COND_LE, // 13 64 COND_AL, // 14 65 COND_UC // 15 66 }; 67 68 enum MiscRegIndex { 69 MISCREG_CPSR = 0, 70 MISCREG_CPSR_Q, 71 MISCREG_SPSR, 72 MISCREG_SPSR_FIQ, 73 MISCREG_SPSR_IRQ, 74 MISCREG_SPSR_SVC, 75 MISCREG_SPSR_MON, 76 MISCREG_SPSR_UND, 77 MISCREG_SPSR_ABT, 78 MISCREG_FPSR, 79 MISCREG_FPSID, 80 MISCREG_FPSCR, 81 MISCREG_FPSCR_QC, // Cumulative saturation flag 82 MISCREG_FPSCR_EXC, // Cumulative FP exception flags 83 MISCREG_FPEXC, 84 MISCREG_MVFR0, 85 MISCREG_MVFR1, 86 MISCREG_SCTLR_RST, 87 MISCREG_SEV_MAILBOX, 88 89 // CP14 registers 90 MISCREG_CP14_START, 91 MISCREG_DBGDIDR = MISCREG_CP14_START, 92 MISCREG_DBGDSCR_INT, 93 MISCREG_DBGDTRRX_INT, 94 MISCREG_DBGTRTX_INT, 95 MISCREG_DBGWFAR, 96 MISCREG_DBGVCR, 97 MISCREG_DBGECR, 98 MISCREG_DBGDSCCR, 99 MISCREG_DBGSMCR, 100 MISCREG_DBGDTRRX_EXT, 101 MISCREG_DBGDSCR_EXT, 102 MISCREG_DBGDTRTX_EXT, 103 MISCREG_DBGDRCR, 104 MISCREG_DBGBVR, 105 MISCREG_DBGBCR, 106 MISCREG_DBGBVR_M, 107 MISCREG_DBGBCR_M, 108 MISCREG_DBGDRAR, 109 MISCREG_DBGBXVR_M, 110 MISCREG_DBGOSLAR, 111 MISCREG_DBGOSSRR, 112 MISCREG_DBGOSDLR, 113 MISCREG_DBGPRCR, 114 MISCREG_DBGPRSR, 115 MISCREG_DBGDSAR, 116 MISCREG_DBGITCTRL, 117 MISCREG_DBGCLAIMSET, 118 MISCREG_DBGCLAIMCLR, 119 MISCREG_DBGAUTHSTATUS, 120 MISCREG_DBGDEVID2, 121 MISCREG_DBGDEVID1, 122 MISCREG_DBGDEVID, 123 124 // CP15 registers 125 MISCREG_CP15_START, 126 MISCREG_SCTLR = MISCREG_CP15_START, 127 MISCREG_DCCISW, 128 MISCREG_DCCIMVAC, 129 MISCREG_DCCMVAC, 130 MISCREG_CONTEXTIDR, 131 MISCREG_TPIDRURW, 132 MISCREG_TPIDRURO, 133 MISCREG_TPIDRPRW, 134 MISCREG_CP15ISB, 135 MISCREG_CP15DSB, 136 MISCREG_CP15DMB, 137 MISCREG_CPACR, 138 MISCREG_CLIDR, 139 MISCREG_CCSIDR, 140 MISCREG_CSSELR, 141 MISCREG_ICIALLUIS, 142 MISCREG_ICIALLU, 143 MISCREG_ICIMVAU, 144 MISCREG_BPIMVA, 145 MISCREG_BPIALLIS, 146 MISCREG_BPIALL, 147 MISCREG_MIDR, 148 MISCREG_TTBR0, 149 MISCREG_TTBR1, 150 MISCREG_TLBTR, 151 MISCREG_DACR, 152 MISCREG_TLBIALLIS, 153 MISCREG_TLBIMVAIS, 154 MISCREG_TLBIASIDIS, 155 MISCREG_TLBIMVAAIS, 156 MISCREG_ITLBIALL, 157 MISCREG_ITLBIMVA, 158 MISCREG_ITLBIASID, 159 MISCREG_DTLBIALL, 160 MISCREG_DTLBIMVA, 161 MISCREG_DTLBIASID, 162 MISCREG_TLBIALL, 163 MISCREG_TLBIMVA, 164 MISCREG_TLBIASID, 165 MISCREG_TLBIMVAA, 166 MISCREG_DFSR, 167 MISCREG_IFSR, 168 MISCREG_DFAR, 169 MISCREG_IFAR, 170 MISCREG_MPIDR, 171 MISCREG_PRRR, 172 MISCREG_NMRR, 173 MISCREG_TTBCR, 174 MISCREG_ID_PFR0, 175 MISCREG_CTR, 176 MISCREG_SCR, 177 MISCREG_SDER, 178 MISCREG_PAR, 179 MISCREG_V2PCWPR, 180 MISCREG_V2PCWPW, 181 MISCREG_V2PCWUR, 182 MISCREG_V2PCWUW, 183 MISCREG_V2POWPR, 184 MISCREG_V2POWPW, 185 MISCREG_V2POWUR, 186 MISCREG_V2POWUW, 187 MISCREG_ID_MMFR0, 188 MISCREG_ID_MMFR2, 189 MISCREG_ID_MMFR3, 190 MISCREG_ACTLR, 191 MISCREG_PMCR, 192 MISCREG_PMCCNTR, 193 MISCREG_PMCNTENSET, 194 MISCREG_PMCNTENCLR, 195 MISCREG_PMOVSR, 196 MISCREG_PMSWINC, 197 MISCREG_PMSELR, 198 MISCREG_PMCEID0, 199 MISCREG_PMCEID1, 200 MISCREG_PMC_OTHER, 201 MISCREG_PMXEVCNTR, 202 MISCREG_PMUSERENR, 203 MISCREG_PMINTENSET, 204 MISCREG_PMINTENCLR, 205 MISCREG_ID_ISAR0, 206 MISCREG_ID_ISAR1, 207 MISCREG_ID_ISAR2, 208 MISCREG_ID_ISAR3, 209 MISCREG_ID_ISAR4, 210 MISCREG_ID_ISAR5, 211 MISCREG_CPSR_MODE, 212 MISCREG_LOCKFLAG, 213 MISCREG_LOCKADDR, 214 MISCREG_ID_PFR1, 215 MISCREG_L2CTLR, 216 MISCREG_CP15_UNIMP_START, 217 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 218 MISCREG_ID_DFR0, 219 MISCREG_ID_AFR0, 220 MISCREG_ID_MMFR1, 221 MISCREG_AIDR, 222 MISCREG_ADFSR, 223 MISCREG_AIFSR, 224 MISCREG_DCIMVAC, 225 MISCREG_DCISW, 226 MISCREG_MCCSW, 227 MISCREG_DCCMVAU, 228 MISCREG_NSACR, 229 MISCREG_VBAR, 230 MISCREG_MVBAR, 231 MISCREG_ISR, 232 MISCREG_FCEIDR, 233 MISCREG_L2LATENCY, 234 MISCREG_CRN15, 235 236 237 MISCREG_CP15_END, 238 239 // Dummy indices 240 MISCREG_NOP = MISCREG_CP15_END, 241 MISCREG_RAZ, 242 243 NUM_MISCREGS 244 }; 245 246 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 247 unsigned crm, unsigned opc2); 248 249 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 250 unsigned crm, unsigned opc2); 251 252 253 const char * const miscRegName[NUM_MISCREGS] = { 254 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 255 "spsr_mon", "spsr_und", "spsr_abt", 256 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 257 "mvfr0", "mvfr1", 258 "sctlr_rst", "sev_mailbox", 259 "DBGDIDR", 260 "DBGDSCR_INT", 261 "DBGDTRRX_INT", 262 "DBGTRTX_INT", 263 "DBGWFAR", 264 "DBGVCR", 265 "DBGECR", 266 "DBGDSCCR", 267 "DBGSMCR", 268 "DBGDTRRX_EXT", 269 "DBGDSCR_EXT", 270 "DBGDTRTX_EXT", 271 "DBGDRCR", 272 "DBGBVR", 273 "DBGBCR", 274 "DBGBVR_M", 275 "DBGBCR_M", 276 "DBGDRAR", 277 "DBGBXVR_M", 278 "DBGOSLAR", 279 "DBGOSSRR", 280 "DBGOSDLR", 281 "DBGPRCR", 282 "DBGPRSR", 283 "DBGDSAR", 284 "DBGITCTRL", 285 "DBGCLAIMSET", 286 "DBGCLAIMCLR", 287 "DBGAUTHSTATUS", 288 "DBGDEVID2", 289 "DBGDEVID1", 290 "DBGDEVID", 291 "sctlr", "dccisw", "dccimvac", "dccmvac", 292 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 293 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 294 "clidr", "ccsidr", "csselr", 295 "icialluis", "iciallu", "icimvau", 296 "bpimva", "bpiallis", "bpiall", 297 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 298 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 299 "itlbiall", "itlbimva", "itlbiasid", 300 "dtlbiall", "dtlbimva", "dtlbiasid", 301 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 302 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 303 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 304 "scr", "sder", "par", 305 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 306 "v2powpr", "v2powpw", "v2powur", "v2powuw", 307 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr", 308 "pmcntenset", "pmcntenclr", "pmovsr", 309 "pmswinc", "pmselr", "pmceid0", 310 "pmceid1", "pmc_other", "pmxevcntr", 311 "pmuserenr", "pmintenset", "pmintenclr", 312 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 313 "cpsr_mode", "lockflag", "lockaddr", "id_pfr1", 314 "l2ctlr", 315 // Unimplemented below 316 "tcmtr", 317 "id_dfr0", "id_afr0", 318 "id_mmfr1", 319 "aidr", "adfsr", "aifsr", 320 "dcimvac", "dcisw", "mccsw", 321 "dccmvau", 322 "nsacr", 323 "vbar", "mvbar", "isr", "fceidr", "l2latency", 324 "crn15", 325 "nop", "raz" 326 }; 327 328 BitUnion32(CPSR) 329 Bitfield<31,30> nz; 330 Bitfield<29> c; 331 Bitfield<28> v; 332 Bitfield<27> q; 333 Bitfield<26,25> it1; 334 Bitfield<24> j; 335 Bitfield<19, 16> ge; 336 Bitfield<15,10> it2; 337 Bitfield<9> e; 338 Bitfield<8> a; 339 Bitfield<7> i; 340 Bitfield<6> f; 341 Bitfield<5> t; 342 Bitfield<4, 0> mode; 343 EndBitUnion(CPSR) 344 345 // This mask selects bits of the CPSR that actually go in the CondCodes 346 // integer register to allow renaming. 347 static const uint32_t CondCodesMask = 0xF00F0000; 348 static const uint32_t CpsrMaskQ = 0x08000000; 349 350 BitUnion32(SCTLR) 351 Bitfield<31> ie; // Instruction endianness 352 Bitfield<30> te; // Thumb Exception Enable 353 Bitfield<29> afe; // Access flag enable 354 Bitfield<28> tre; // TEX Remap bit 355 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 356 Bitfield<25> ee; // Exception Endianness bit 357 Bitfield<24> ve; // Interrupt vectors enable 358 Bitfield<23> xp; // Extended page table enable bit 359 Bitfield<22> u; // Alignment (now unused) 360 Bitfield<21> fi; // Fast interrupts configuration enable 361 Bitfield<19> dz; // Divide by Zero fault enable bit 362 Bitfield<18> rao2;// Read as one 363 Bitfield<17> br; // Background region bit 364 Bitfield<16> rao3;// Read as one 365 Bitfield<14> rr; // Round robin cache replacement 366 Bitfield<13> v; // Base address for exception vectors 367 Bitfield<12> i; // instruction cache enable 368 Bitfield<11> z; // branch prediction enable bit 369 Bitfield<10> sw; // Enable swp/swpb 370 Bitfield<9,8> rs; // deprecated protection bits 371 Bitfield<6,3> rao4;// Read as one 372 Bitfield<7> b; // Endianness support (unused) 373 Bitfield<2> c; // Cache enable bit 374 Bitfield<1> a; // Alignment fault checking 375 Bitfield<0> m; // MMU enable bit 376 EndBitUnion(SCTLR) 377 378 BitUnion32(CPACR) 379 Bitfield<1, 0> cp0; 380 Bitfield<3, 2> cp1; 381 Bitfield<5, 4> cp2; 382 Bitfield<7, 6> cp3; 383 Bitfield<9, 8> cp4; 384 Bitfield<11, 10> cp5; 385 Bitfield<13, 12> cp6; 386 Bitfield<15, 14> cp7; 387 Bitfield<17, 16> cp8; 388 Bitfield<19, 18> cp9; 389 Bitfield<21, 20> cp10; 390 Bitfield<23, 22> cp11; 391 Bitfield<25, 24> cp12; 392 Bitfield<27, 26> cp13; 393 Bitfield<29, 28> rsvd; 394 Bitfield<30> d32dis; 395 Bitfield<31> asedis; 396 EndBitUnion(CPACR) 397 398 BitUnion32(FSR) 399 Bitfield<3, 0> fsLow; 400 Bitfield<7, 4> domain; 401 Bitfield<10> fsHigh; 402 Bitfield<11> wnr; 403 Bitfield<12> ext; 404 EndBitUnion(FSR) 405 406 BitUnion32(FPSCR) 407 Bitfield<0> ioc; 408 Bitfield<1> dzc; 409 Bitfield<2> ofc; 410 Bitfield<3> ufc; 411 Bitfield<4> ixc; 412 Bitfield<7> idc; 413 Bitfield<8> ioe; 414 Bitfield<9> dze; 415 Bitfield<10> ofe; 416 Bitfield<11> ufe; 417 Bitfield<12> ixe; 418 Bitfield<15> ide; 419 Bitfield<18, 16> len; 420 Bitfield<21, 20> stride; 421 Bitfield<23, 22> rMode; 422 Bitfield<24> fz; 423 Bitfield<25> dn; 424 Bitfield<26> ahp; 425 Bitfield<27> qc; 426 Bitfield<28> v; 427 Bitfield<29> c; 428 Bitfield<30> z; 429 Bitfield<31> n; 430 EndBitUnion(FPSCR) 431 432 // This mask selects bits of the FPSCR that actually go in the FpCondCodes 433 // integer register to allow renaming. 434 static const uint32_t FpCondCodesMask = 0xF0000000; 435 // This mask selects the cumulative FP exception flags of the FPSCR. 436 static const uint32_t FpscrExcMask = 0x0000009F; 437 // This mask selects the cumulative saturation flag of the FPSCR. 438 static const uint32_t FpscrQcMask = 0x08000000; 439 440 BitUnion32(FPEXC) 441 Bitfield<31> ex; 442 Bitfield<30> en; 443 Bitfield<29, 0> subArchDefined; 444 EndBitUnion(FPEXC) 445 446 BitUnion32(MVFR0) 447 Bitfield<3, 0> advSimdRegisters; 448 Bitfield<7, 4> singlePrecision; 449 Bitfield<11, 8> doublePrecision; 450 Bitfield<15, 12> vfpExceptionTrapping; 451 Bitfield<19, 16> divide; 452 Bitfield<23, 20> squareRoot; 453 Bitfield<27, 24> shortVectors; 454 Bitfield<31, 28> roundingModes; 455 EndBitUnion(MVFR0) 456 457 BitUnion32(MVFR1) 458 Bitfield<3, 0> flushToZero; 459 Bitfield<7, 4> defaultNaN; 460 Bitfield<11, 8> advSimdLoadStore; 461 Bitfield<15, 12> advSimdInteger; 462 Bitfield<19, 16> advSimdSinglePrecision; 463 Bitfield<23, 20> advSimdHalfPrecision; 464 Bitfield<27, 24> vfpHalfPrecision; 465 Bitfield<31, 28> raz; 466 EndBitUnion(MVFR1) 467 468 BitUnion32(PRRR) 469 Bitfield<1,0> tr0; 470 Bitfield<3,2> tr1; 471 Bitfield<5,4> tr2; 472 Bitfield<7,6> tr3; 473 Bitfield<9,8> tr4; 474 Bitfield<11,10> tr5; 475 Bitfield<13,12> tr6; 476 Bitfield<15,14> tr7; 477 Bitfield<16> ds0; 478 Bitfield<17> ds1; 479 Bitfield<18> ns0; 480 Bitfield<19> ns1; 481 Bitfield<24> nos0; 482 Bitfield<25> nos1; 483 Bitfield<26> nos2; 484 Bitfield<27> nos3; 485 Bitfield<28> nos4; 486 Bitfield<29> nos5; 487 Bitfield<30> nos6; 488 Bitfield<31> nos7; 489 EndBitUnion(PRRR) 490 491 BitUnion32(NMRR) 492 Bitfield<1,0> ir0; 493 Bitfield<3,2> ir1; 494 Bitfield<5,4> ir2; 495 Bitfield<7,6> ir3; 496 Bitfield<9,8> ir4; 497 Bitfield<11,10> ir5; 498 Bitfield<13,12> ir6; 499 Bitfield<15,14> ir7; 500 Bitfield<17,16> or0; 501 Bitfield<19,18> or1; 502 Bitfield<21,20> or2; 503 Bitfield<23,22> or3; 504 Bitfield<25,24> or4; 505 Bitfield<27,26> or5; 506 Bitfield<29,28> or6; 507 Bitfield<31,30> or7; 508 EndBitUnion(NMRR) 509 510 BitUnion32(CONTEXTIDR) 511 Bitfield<7,0> asid; 512 Bitfield<31,8> procid; 513 EndBitUnion(CONTEXTIDR) 514 515 BitUnion32(L2CTLR) 516 Bitfield<2,0> sataRAMLatency; 517 Bitfield<4,3> reserved_4_3; 518 Bitfield<5> dataRAMSetup; 519 Bitfield<8,6> tagRAMLatency; 520 Bitfield<9> tagRAMSetup; 521 Bitfield<11,10> dataRAMSlice; 522 Bitfield<12> tagRAMSlice; 523 Bitfield<20,13> reserved_20_13; 524 Bitfield<21> eccandParityEnable; 525 Bitfield<22> reserved_22; 526 Bitfield<23> interptCtrlPresent; 527 Bitfield<25,24> numCPUs; 528 Bitfield<30,26> reserved_30_26; 529 Bitfield<31> l2rstDISABLE_monitor; 530 EndBitUnion(L2CTLR) 531 532} 533 534#endif // __ARCH_ARM_MISCREGS_HH__ 535