miscregs.hh revision 8550
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49    enum ConditionCode {
50        COND_EQ  =   0,
51        COND_NE, //  1
52        COND_CS, //  2
53        COND_CC, //  3
54        COND_MI, //  4
55        COND_PL, //  5
56        COND_VS, //  6
57        COND_VC, //  7
58        COND_HI, //  8
59        COND_LS, //  9
60        COND_GE, // 10
61        COND_LT, // 11
62        COND_GT, // 12
63        COND_LE, // 13
64        COND_AL, // 14
65        COND_UC  // 15
66    };
67
68    enum MiscRegIndex {
69        MISCREG_CPSR = 0,
70        MISCREG_CPSR_Q,
71        MISCREG_SPSR,
72        MISCREG_SPSR_FIQ,
73        MISCREG_SPSR_IRQ,
74        MISCREG_SPSR_SVC,
75        MISCREG_SPSR_MON,
76        MISCREG_SPSR_UND,
77        MISCREG_SPSR_ABT,
78        MISCREG_FPSR,
79        MISCREG_FPSID,
80        MISCREG_FPSCR,
81        MISCREG_FPSCR_QC,  // Cumulative saturation flag
82        MISCREG_FPSCR_EXC,  // Cumulative FP exception flags
83        MISCREG_FPEXC,
84        MISCREG_MVFR0,
85        MISCREG_MVFR1,
86        MISCREG_SCTLR_RST,
87        MISCREG_SEV_MAILBOX,
88
89        // CP15 registers
90        MISCREG_CP15_START,
91        MISCREG_SCTLR = MISCREG_CP15_START,
92        MISCREG_DCCISW,
93        MISCREG_DCCIMVAC,
94        MISCREG_DCCMVAC,
95        MISCREG_CONTEXTIDR,
96        MISCREG_TPIDRURW,
97        MISCREG_TPIDRURO,
98        MISCREG_TPIDRPRW,
99        MISCREG_CP15ISB,
100        MISCREG_CP15DSB,
101        MISCREG_CP15DMB,
102        MISCREG_CPACR,
103        MISCREG_CLIDR,
104        MISCREG_CCSIDR,
105        MISCREG_CSSELR,
106        MISCREG_ICIALLUIS,
107        MISCREG_ICIALLU,
108        MISCREG_ICIMVAU,
109        MISCREG_BPIMVA,
110        MISCREG_BPIALLIS,
111        MISCREG_BPIALL,
112        MISCREG_MIDR,
113        MISCREG_TTBR0,
114        MISCREG_TTBR1,
115        MISCREG_TLBTR,
116        MISCREG_DACR,
117        MISCREG_TLBIALLIS,
118        MISCREG_TLBIMVAIS,
119        MISCREG_TLBIASIDIS,
120        MISCREG_TLBIMVAAIS,
121        MISCREG_ITLBIALL,
122        MISCREG_ITLBIMVA,
123        MISCREG_ITLBIASID,
124        MISCREG_DTLBIALL,
125        MISCREG_DTLBIMVA,
126        MISCREG_DTLBIASID,
127        MISCREG_TLBIALL,
128        MISCREG_TLBIMVA,
129        MISCREG_TLBIASID,
130        MISCREG_TLBIMVAA,
131        MISCREG_DFSR,
132        MISCREG_IFSR,
133        MISCREG_DFAR,
134        MISCREG_IFAR,
135        MISCREG_MPIDR,
136        MISCREG_PRRR,
137        MISCREG_NMRR,
138        MISCREG_TTBCR,
139        MISCREG_ID_PFR0,
140        MISCREG_CTR,
141        MISCREG_SCR,
142        MISCREG_SDER,
143        MISCREG_PAR,
144        MISCREG_V2PCWPR,
145        MISCREG_V2PCWPW,
146        MISCREG_V2PCWUR,
147        MISCREG_V2PCWUW,
148        MISCREG_V2POWPR,
149        MISCREG_V2POWPW,
150        MISCREG_V2POWUR,
151        MISCREG_V2POWUW,
152        MISCREG_ID_MMFR0,
153        MISCREG_ID_MMFR2,
154        MISCREG_ID_MMFR3,
155        MISCREG_ACTLR,
156        MISCREG_PMCR,
157        MISCREG_PMCCNTR,
158        MISCREG_PMCNTENSET,
159        MISCREG_PMCNTENCLR,
160        MISCREG_PMOVSR,
161        MISCREG_PMSWINC,
162        MISCREG_PMSELR,
163        MISCREG_PMCEID0,
164        MISCREG_PMCEID1,
165        MISCREG_PMC_OTHER,
166        MISCREG_PMXEVCNTR,
167        MISCREG_PMUSERENR,
168        MISCREG_PMINTENSET,
169        MISCREG_PMINTENCLR,
170        MISCREG_ID_ISAR0,
171        MISCREG_ID_ISAR1,
172        MISCREG_ID_ISAR2,
173        MISCREG_ID_ISAR3,
174        MISCREG_ID_ISAR4,
175        MISCREG_ID_ISAR5,
176        MISCREG_CPSR_MODE,
177        MISCREG_LOCKFLAG,
178        MISCREG_LOCKADDR,
179        MISCREG_ID_PFR1,
180        MISCREG_L2CTLR,
181        MISCREG_CP15_UNIMP_START,
182        MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
183        MISCREG_ID_DFR0,
184        MISCREG_ID_AFR0,
185        MISCREG_ID_MMFR1,
186        MISCREG_AIDR,
187        MISCREG_ADFSR,
188        MISCREG_AIFSR,
189        MISCREG_DCIMVAC,
190        MISCREG_DCISW,
191        MISCREG_MCCSW,
192        MISCREG_DCCMVAU,
193        MISCREG_NSACR,
194        MISCREG_VBAR,
195        MISCREG_MVBAR,
196        MISCREG_ISR,
197        MISCREG_FCEIDR,
198        MISCREG_L2LATENCY,
199        MISCREG_CRN15,
200
201
202        MISCREG_CP15_END,
203
204        // Dummy indices
205        MISCREG_NOP = MISCREG_CP15_END,
206        MISCREG_RAZ,
207
208        NUM_MISCREGS
209    };
210
211    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
212                               unsigned crm, unsigned opc2);
213
214    const char * const miscRegName[NUM_MISCREGS] = {
215        "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
216        "spsr_mon", "spsr_und", "spsr_abt",
217        "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
218        "mvfr0", "mvfr1",
219        "sctlr_rst", "sev_mailbox",
220        "sctlr", "dccisw", "dccimvac", "dccmvac",
221        "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
222        "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
223        "clidr", "ccsidr", "csselr",
224        "icialluis", "iciallu", "icimvau",
225        "bpimva", "bpiallis", "bpiall",
226        "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
227        "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
228        "itlbiall", "itlbimva", "itlbiasid",
229        "dtlbiall", "dtlbimva", "dtlbiasid",
230        "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
231        "dfsr", "ifsr", "dfar", "ifar", "mpidr",
232        "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr",
233        "scr", "sder", "par",
234        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
235        "v2powpr", "v2powpw", "v2powur", "v2powuw",
236        "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr",
237        "pmcntenset", "pmcntenclr", "pmovsr",
238        "pmswinc", "pmselr", "pmceid0",
239        "pmceid1", "pmc_other", "pmxevcntr",
240        "pmuserenr", "pmintenset", "pmintenclr",
241        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
242        "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
243        "l2ctlr",
244         // Unimplemented below
245        "tcmtr",
246        "id_dfr0", "id_afr0",
247        "id_mmfr1",
248        "aidr", "adfsr", "aifsr",
249        "dcimvac", "dcisw", "mccsw",
250        "dccmvau",
251        "nsacr",
252        "vbar", "mvbar", "isr", "fceidr", "l2latency",
253        "crn15",
254        "nop", "raz"
255    };
256
257    BitUnion32(CPSR)
258        Bitfield<31,30> nz;
259        Bitfield<29> c;
260        Bitfield<28> v;
261        Bitfield<27> q;
262        Bitfield<26,25> it1;
263        Bitfield<24> j;
264        Bitfield<19, 16> ge;
265        Bitfield<15,10> it2;
266        Bitfield<9> e;
267        Bitfield<8> a;
268        Bitfield<7> i;
269        Bitfield<6> f;
270        Bitfield<5> t;
271        Bitfield<4, 0> mode;
272    EndBitUnion(CPSR)
273
274    // This mask selects bits of the CPSR that actually go in the CondCodes
275    // integer register to allow renaming.
276    static const uint32_t CondCodesMask   = 0xF00F0000;
277    static const uint32_t CpsrMaskQ       = 0x08000000;
278
279    BitUnion32(SCTLR)
280        Bitfield<31> ie;  // Instruction endianness
281        Bitfield<30> te;  // Thumb Exception Enable
282        Bitfield<29> afe; // Access flag enable
283        Bitfield<28> tre; // TEX Remap bit
284        Bitfield<27> nmfi;// Non-maskable fast interrupts enable
285        Bitfield<25> ee;  // Exception Endianness bit
286        Bitfield<24> ve;  // Interrupt vectors enable
287        Bitfield<23> xp; //  Extended page table enable bit
288        Bitfield<22> u;   // Alignment (now unused)
289        Bitfield<21> fi;  // Fast interrupts configuration enable
290        Bitfield<19> dz;  // Divide by Zero fault enable bit
291        Bitfield<18> rao2;// Read as one
292        Bitfield<17> br;  // Background region bit
293        Bitfield<16> rao3;// Read as one
294        Bitfield<14> rr;  // Round robin cache replacement
295        Bitfield<13> v;   // Base address for exception vectors
296        Bitfield<12> i;   // instruction cache enable
297        Bitfield<11> z;   // branch prediction enable bit
298        Bitfield<10> sw;  // Enable swp/swpb
299        Bitfield<9,8> rs;   // deprecated protection bits
300        Bitfield<6,3> rao4;// Read as one
301        Bitfield<7>  b;   // Endianness support (unused)
302        Bitfield<2>  c;   // Cache enable bit
303        Bitfield<1>  a;   // Alignment fault checking
304        Bitfield<0>  m;   // MMU enable bit
305    EndBitUnion(SCTLR)
306
307    BitUnion32(CPACR)
308        Bitfield<1, 0> cp0;
309        Bitfield<3, 2> cp1;
310        Bitfield<5, 4> cp2;
311        Bitfield<7, 6> cp3;
312        Bitfield<9, 8> cp4;
313        Bitfield<11, 10> cp5;
314        Bitfield<13, 12> cp6;
315        Bitfield<15, 14> cp7;
316        Bitfield<17, 16> cp8;
317        Bitfield<19, 18> cp9;
318        Bitfield<21, 20> cp10;
319        Bitfield<23, 22> cp11;
320        Bitfield<25, 24> cp12;
321        Bitfield<27, 26> cp13;
322        Bitfield<29, 28> rsvd;
323        Bitfield<30> d32dis;
324        Bitfield<31> asedis;
325    EndBitUnion(CPACR)
326
327    BitUnion32(FSR)
328        Bitfield<3, 0> fsLow;
329        Bitfield<7, 4> domain;
330        Bitfield<10> fsHigh;
331        Bitfield<11> wnr;
332        Bitfield<12> ext;
333    EndBitUnion(FSR)
334
335    BitUnion32(FPSCR)
336        Bitfield<0> ioc;
337        Bitfield<1> dzc;
338        Bitfield<2> ofc;
339        Bitfield<3> ufc;
340        Bitfield<4> ixc;
341        Bitfield<7> idc;
342        Bitfield<8> ioe;
343        Bitfield<9> dze;
344        Bitfield<10> ofe;
345        Bitfield<11> ufe;
346        Bitfield<12> ixe;
347        Bitfield<15> ide;
348        Bitfield<18, 16> len;
349        Bitfield<21, 20> stride;
350        Bitfield<23, 22> rMode;
351        Bitfield<24> fz;
352        Bitfield<25> dn;
353        Bitfield<26> ahp;
354        Bitfield<27> qc;
355        Bitfield<28> v;
356        Bitfield<29> c;
357        Bitfield<30> z;
358        Bitfield<31> n;
359    EndBitUnion(FPSCR)
360
361    // This mask selects bits of the FPSCR that actually go in the FpCondCodes
362    // integer register to allow renaming.
363    static const uint32_t FpCondCodesMask = 0xF0000000;
364    // This mask selects the cumulative FP exception flags of the FPSCR.
365    static const uint32_t FpscrExcMask = 0x0000009F;
366    // This mask selects the cumulative saturation flag of the FPSCR.
367    static const uint32_t FpscrQcMask = 0x08000000;
368
369    BitUnion32(FPEXC)
370        Bitfield<31> ex;
371        Bitfield<30> en;
372        Bitfield<29, 0> subArchDefined;
373    EndBitUnion(FPEXC)
374
375    BitUnion32(MVFR0)
376        Bitfield<3, 0> advSimdRegisters;
377        Bitfield<7, 4> singlePrecision;
378        Bitfield<11, 8> doublePrecision;
379        Bitfield<15, 12> vfpExceptionTrapping;
380        Bitfield<19, 16> divide;
381        Bitfield<23, 20> squareRoot;
382        Bitfield<27, 24> shortVectors;
383        Bitfield<31, 28> roundingModes;
384    EndBitUnion(MVFR0)
385
386    BitUnion32(MVFR1)
387        Bitfield<3, 0> flushToZero;
388        Bitfield<7, 4> defaultNaN;
389        Bitfield<11, 8> advSimdLoadStore;
390        Bitfield<15, 12> advSimdInteger;
391        Bitfield<19, 16> advSimdSinglePrecision;
392        Bitfield<23, 20> advSimdHalfPrecision;
393        Bitfield<27, 24> vfpHalfPrecision;
394        Bitfield<31, 28> raz;
395    EndBitUnion(MVFR1)
396
397    BitUnion32(PRRR)
398       Bitfield<1,0> tr0;
399       Bitfield<3,2> tr1;
400       Bitfield<5,4> tr2;
401       Bitfield<7,6> tr3;
402       Bitfield<9,8> tr4;
403       Bitfield<11,10> tr5;
404       Bitfield<13,12> tr6;
405       Bitfield<15,14> tr7;
406       Bitfield<16> ds0;
407       Bitfield<17> ds1;
408       Bitfield<18> ns0;
409       Bitfield<19> ns1;
410       Bitfield<24> nos0;
411       Bitfield<25> nos1;
412       Bitfield<26> nos2;
413       Bitfield<27> nos3;
414       Bitfield<28> nos4;
415       Bitfield<29> nos5;
416       Bitfield<30> nos6;
417       Bitfield<31> nos7;
418   EndBitUnion(PRRR)
419
420   BitUnion32(NMRR)
421       Bitfield<1,0> ir0;
422       Bitfield<3,2> ir1;
423       Bitfield<5,4> ir2;
424       Bitfield<7,6> ir3;
425       Bitfield<9,8> ir4;
426       Bitfield<11,10> ir5;
427       Bitfield<13,12> ir6;
428       Bitfield<15,14> ir7;
429       Bitfield<17,16> or0;
430       Bitfield<19,18> or1;
431       Bitfield<21,20> or2;
432       Bitfield<23,22> or3;
433       Bitfield<25,24> or4;
434       Bitfield<27,26> or5;
435       Bitfield<29,28> or6;
436       Bitfield<31,30> or7;
437   EndBitUnion(NMRR)
438
439   BitUnion32(L2CTLR)
440      Bitfield<2,0>   sataRAMLatency;
441      Bitfield<4,3>   reserved_4_3;
442      Bitfield<5>     dataRAMSetup;
443      Bitfield<8,6>   tagRAMLatency;
444      Bitfield<9>     tagRAMSetup;
445      Bitfield<11,10> dataRAMSlice;
446      Bitfield<12>    tagRAMSlice;
447      Bitfield<20,13> reserved_20_13;
448      Bitfield<21>    eccandParityEnable;
449      Bitfield<22>    reserved_22;
450      Bitfield<23>    interptCtrlPresent;
451      Bitfield<25,24> numCPUs;
452      Bitfield<30,26> reserved_30_26;
453      Bitfield<31>    l2rstDISABLE_monitor;
454   EndBitUnion(L2CTLR)
455
456};
457
458#endif // __ARCH_ARM_MISCREGS_HH__
459