miscregs.hh revision 8302:9f23d01421de
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 45#include "base/bitunion.hh" 46 47namespace ArmISA 48{ 49 enum ConditionCode { 50 COND_EQ = 0, 51 COND_NE, // 1 52 COND_CS, // 2 53 COND_CC, // 3 54 COND_MI, // 4 55 COND_PL, // 5 56 COND_VS, // 6 57 COND_VC, // 7 58 COND_HI, // 8 59 COND_LS, // 9 60 COND_GE, // 10 61 COND_LT, // 11 62 COND_GT, // 12 63 COND_LE, // 13 64 COND_AL, // 14 65 COND_UC // 15 66 }; 67 68 enum MiscRegIndex { 69 MISCREG_CPSR = 0, 70 MISCREG_CPSR_Q, 71 MISCREG_SPSR, 72 MISCREG_SPSR_FIQ, 73 MISCREG_SPSR_IRQ, 74 MISCREG_SPSR_SVC, 75 MISCREG_SPSR_MON, 76 MISCREG_SPSR_UND, 77 MISCREG_SPSR_ABT, 78 MISCREG_FPSR, 79 MISCREG_FPSID, 80 MISCREG_FPSCR, 81 MISCREG_FPSCR_QC, // Cumulative saturation flag 82 MISCREG_FPSCR_EXC, // Cumulative FP exception flags 83 MISCREG_FPEXC, 84 MISCREG_MVFR0, 85 MISCREG_MVFR1, 86 MISCREG_SCTLR_RST, 87 MISCREG_SEV_MAILBOX, 88 89 // CP15 registers 90 MISCREG_CP15_START, 91 MISCREG_SCTLR = MISCREG_CP15_START, 92 MISCREG_DCCISW, 93 MISCREG_DCCIMVAC, 94 MISCREG_DCCMVAC, 95 MISCREG_CONTEXTIDR, 96 MISCREG_TPIDRURW, 97 MISCREG_TPIDRURO, 98 MISCREG_TPIDRPRW, 99 MISCREG_CP15ISB, 100 MISCREG_CP15DSB, 101 MISCREG_CP15DMB, 102 MISCREG_CPACR, 103 MISCREG_CLIDR, 104 MISCREG_CCSIDR, 105 MISCREG_CSSELR, 106 MISCREG_ICIALLUIS, 107 MISCREG_ICIALLU, 108 MISCREG_ICIMVAU, 109 MISCREG_BPIMVA, 110 MISCREG_BPIALLIS, 111 MISCREG_BPIALL, 112 MISCREG_MIDR, 113 MISCREG_TTBR0, 114 MISCREG_TTBR1, 115 MISCREG_TLBTR, 116 MISCREG_DACR, 117 MISCREG_TLBIALLIS, 118 MISCREG_TLBIMVAIS, 119 MISCREG_TLBIASIDIS, 120 MISCREG_TLBIMVAAIS, 121 MISCREG_ITLBIALL, 122 MISCREG_ITLBIMVA, 123 MISCREG_ITLBIASID, 124 MISCREG_DTLBIALL, 125 MISCREG_DTLBIMVA, 126 MISCREG_DTLBIASID, 127 MISCREG_TLBIALL, 128 MISCREG_TLBIMVA, 129 MISCREG_TLBIASID, 130 MISCREG_TLBIMVAA, 131 MISCREG_DFSR, 132 MISCREG_IFSR, 133 MISCREG_DFAR, 134 MISCREG_IFAR, 135 MISCREG_MPIDR, 136 MISCREG_PRRR, 137 MISCREG_NMRR, 138 MISCREG_TTBCR, 139 MISCREG_ID_PFR0, 140 MISCREG_CTR, 141 MISCREG_SCR, 142 MISCREG_SDER, 143 MISCREG_PAR, 144 MISCREG_V2PCWPR, 145 MISCREG_V2PCWPW, 146 MISCREG_V2PCWUR, 147 MISCREG_V2PCWUW, 148 MISCREG_V2POWPR, 149 MISCREG_V2POWPW, 150 MISCREG_V2POWUR, 151 MISCREG_V2POWUW, 152 MISCREG_ID_MMFR0, 153 MISCREG_ID_MMFR3, 154 MISCREG_ACTLR, 155 MISCREG_PMCR, 156 MISCREG_PMCCNTR, 157 MISCREG_PMCNTENSET, 158 MISCREG_PMCNTENCLR, 159 MISCREG_PMOVSR, 160 MISCREG_PMSWINC, 161 MISCREG_PMSELR, 162 MISCREG_PMCEID0, 163 MISCREG_PMCEID1, 164 MISCREG_PMC_OTHER, 165 MISCREG_PMXEVCNTR, 166 MISCREG_PMUSERENR, 167 MISCREG_PMINTENSET, 168 MISCREG_PMINTENCLR, 169 MISCREG_ID_ISAR0, 170 MISCREG_ID_ISAR1, 171 MISCREG_ID_ISAR2, 172 MISCREG_ID_ISAR3, 173 MISCREG_ID_ISAR4, 174 MISCREG_ID_ISAR5, 175 MISCREG_CPSR_MODE, 176 MISCREG_LOCKFLAG, 177 MISCREG_LOCKADDR, 178 MISCREG_ID_PFR1, 179 MISCREG_CP15_UNIMP_START, 180 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 181 MISCREG_ID_DFR0, 182 MISCREG_ID_AFR0, 183 MISCREG_ID_MMFR1, 184 MISCREG_ID_MMFR2, 185 MISCREG_AIDR, 186 MISCREG_ADFSR, 187 MISCREG_AIFSR, 188 MISCREG_DCIMVAC, 189 MISCREG_DCISW, 190 MISCREG_MCCSW, 191 MISCREG_DCCMVAU, 192 MISCREG_NSACR, 193 MISCREG_VBAR, 194 MISCREG_MVBAR, 195 MISCREG_ISR, 196 MISCREG_FCEIDR, 197 MISCREG_L2LATENCY, 198 199 200 MISCREG_CP15_END, 201 202 // Dummy indices 203 MISCREG_NOP = MISCREG_CP15_END, 204 MISCREG_RAZ, 205 206 NUM_MISCREGS 207 }; 208 209 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 210 unsigned crm, unsigned opc2); 211 212 const char * const miscRegName[NUM_MISCREGS] = { 213 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 214 "spsr_mon", "spsr_und", "spsr_abt", 215 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 216 "mvfr0", "mvfr1", 217 "sctlr_rst", "sev_mailbox", 218 "sctlr", "dccisw", "dccimvac", "dccmvac", 219 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 220 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 221 "clidr", "ccsidr", "csselr", 222 "icialluis", "iciallu", "icimvau", 223 "bpimva", "bpiallis", "bpiall", 224 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 225 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 226 "itlbiall", "itlbimva", "itlbiasid", 227 "dtlbiall", "dtlbimva", "dtlbiasid", 228 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 229 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 230 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 231 "scr", "sder", "par", 232 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 233 "v2powpr", "v2powpw", "v2powur", "v2powuw", 234 "id_mmfr0", "id_mmfr3", "actlr", "pmcr", "pmccntr", 235 "pmcntenset", "pmcntenclr", "pmovsr", 236 "pmswinc", "pmselr", "pmceid0", 237 "pmceid1", "pmc_other", "pmxevcntr", 238 "pmuserenr", "pmintenset", "pmintenclr", 239 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 240 "cpsr_mode", "lockflag", "lockaddr", "id_pfr1", 241 // Unimplemented below 242 "tcmtr", 243 "id_dfr0", "id_afr0", 244 "id_mmfr1", "id_mmfr2", 245 "aidr", "adfsr", "aifsr", 246 "dcimvac", "dcisw", "mccsw", 247 "dccmvau", 248 "nsacr", 249 "vbar", "mvbar", "isr", "fceidr", "l2latency", 250 "nop", "raz" 251 }; 252 253 BitUnion32(CPSR) 254 Bitfield<31> n; 255 Bitfield<30> z; 256 Bitfield<29> c; 257 Bitfield<28> v; 258 Bitfield<27> q; 259 Bitfield<26,25> it1; 260 Bitfield<24> j; 261 Bitfield<19, 16> ge; 262 Bitfield<15,10> it2; 263 Bitfield<9> e; 264 Bitfield<8> a; 265 Bitfield<7> i; 266 Bitfield<6> f; 267 Bitfield<5> t; 268 Bitfield<4, 0> mode; 269 EndBitUnion(CPSR) 270 271 // This mask selects bits of the CPSR that actually go in the CondCodes 272 // integer register to allow renaming. 273 static const uint32_t CondCodesMask = 0xF00F0000; 274 static const uint32_t CondCodesMaskF = 0xF0000000; 275 static const uint32_t CpsrMaskQ = 0x08000000; 276 static const uint32_t CondCodesMaskGE = 0x000F0000; 277 278 BitUnion32(SCTLR) 279 Bitfield<31> ie; // Instruction endianness 280 Bitfield<30> te; // Thumb Exception Enable 281 Bitfield<29> afe; // Access flag enable 282 Bitfield<28> tre; // TEX Remap bit 283 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 284 Bitfield<25> ee; // Exception Endianness bit 285 Bitfield<24> ve; // Interrupt vectors enable 286 Bitfield<23> xp; // Extended page table enable bit 287 Bitfield<22> u; // Alignment (now unused) 288 Bitfield<21> fi; // Fast interrupts configuration enable 289 Bitfield<19> dz; // Divide by Zero fault enable bit 290 Bitfield<18> rao2;// Read as one 291 Bitfield<17> br; // Background region bit 292 Bitfield<16> rao3;// Read as one 293 Bitfield<14> rr; // Round robin cache replacement 294 Bitfield<13> v; // Base address for exception vectors 295 Bitfield<12> i; // instruction cache enable 296 Bitfield<11> z; // branch prediction enable bit 297 Bitfield<10> sw; // Enable swp/swpb 298 Bitfield<9,8> rs; // deprecated protection bits 299 Bitfield<6,3> rao4;// Read as one 300 Bitfield<7> b; // Endianness support (unused) 301 Bitfield<2> c; // Cache enable bit 302 Bitfield<1> a; // Alignment fault checking 303 Bitfield<0> m; // MMU enable bit 304 EndBitUnion(SCTLR) 305 306 BitUnion32(CPACR) 307 Bitfield<1, 0> cp0; 308 Bitfield<3, 2> cp1; 309 Bitfield<5, 4> cp2; 310 Bitfield<7, 6> cp3; 311 Bitfield<9, 8> cp4; 312 Bitfield<11, 10> cp5; 313 Bitfield<13, 12> cp6; 314 Bitfield<15, 14> cp7; 315 Bitfield<17, 16> cp8; 316 Bitfield<19, 18> cp9; 317 Bitfield<21, 20> cp10; 318 Bitfield<23, 22> cp11; 319 Bitfield<25, 24> cp12; 320 Bitfield<27, 26> cp13; 321 Bitfield<29, 28> rsvd; 322 Bitfield<30> d32dis; 323 Bitfield<31> asedis; 324 EndBitUnion(CPACR) 325 326 BitUnion32(FSR) 327 Bitfield<3, 0> fsLow; 328 Bitfield<7, 4> domain; 329 Bitfield<10> fsHigh; 330 Bitfield<11> wnr; 331 Bitfield<12> ext; 332 EndBitUnion(FSR) 333 334 BitUnion32(FPSCR) 335 Bitfield<0> ioc; 336 Bitfield<1> dzc; 337 Bitfield<2> ofc; 338 Bitfield<3> ufc; 339 Bitfield<4> ixc; 340 Bitfield<7> idc; 341 Bitfield<8> ioe; 342 Bitfield<9> dze; 343 Bitfield<10> ofe; 344 Bitfield<11> ufe; 345 Bitfield<12> ixe; 346 Bitfield<15> ide; 347 Bitfield<18, 16> len; 348 Bitfield<21, 20> stride; 349 Bitfield<23, 22> rMode; 350 Bitfield<24> fz; 351 Bitfield<25> dn; 352 Bitfield<26> ahp; 353 Bitfield<27> qc; 354 Bitfield<28> v; 355 Bitfield<29> c; 356 Bitfield<30> z; 357 Bitfield<31> n; 358 EndBitUnion(FPSCR) 359 360 // This mask selects bits of the FPSCR that actually go in the FpCondCodes 361 // integer register to allow renaming. 362 static const uint32_t FpCondCodesMask = 0xF0000000; 363 // This mask selects the cumulative FP exception flags of the FPSCR. 364 static const uint32_t FpscrExcMask = 0x0000009F; 365 // This mask selects the cumulative saturation flag of the FPSCR. 366 static const uint32_t FpscrQcMask = 0x08000000; 367 368 BitUnion32(FPEXC) 369 Bitfield<31> ex; 370 Bitfield<30> en; 371 Bitfield<29, 0> subArchDefined; 372 EndBitUnion(FPEXC) 373 374 BitUnion32(MVFR0) 375 Bitfield<3, 0> advSimdRegisters; 376 Bitfield<7, 4> singlePrecision; 377 Bitfield<11, 8> doublePrecision; 378 Bitfield<15, 12> vfpExceptionTrapping; 379 Bitfield<19, 16> divide; 380 Bitfield<23, 20> squareRoot; 381 Bitfield<27, 24> shortVectors; 382 Bitfield<31, 28> roundingModes; 383 EndBitUnion(MVFR0) 384 385 BitUnion32(MVFR1) 386 Bitfield<3, 0> flushToZero; 387 Bitfield<7, 4> defaultNaN; 388 Bitfield<11, 8> advSimdLoadStore; 389 Bitfield<15, 12> advSimdInteger; 390 Bitfield<19, 16> advSimdSinglePrecision; 391 Bitfield<23, 20> advSimdHalfPrecision; 392 Bitfield<27, 24> vfpHalfPrecision; 393 Bitfield<31, 28> raz; 394 EndBitUnion(MVFR1) 395 396 BitUnion32(PRRR) 397 Bitfield<1,0> tr0; 398 Bitfield<3,2> tr1; 399 Bitfield<5,4> tr2; 400 Bitfield<7,6> tr3; 401 Bitfield<9,8> tr4; 402 Bitfield<11,10> tr5; 403 Bitfield<13,12> tr6; 404 Bitfield<15,14> tr7; 405 Bitfield<16> ds0; 406 Bitfield<17> ds1; 407 Bitfield<18> ns0; 408 Bitfield<19> ns1; 409 Bitfield<24> nos0; 410 Bitfield<25> nos1; 411 Bitfield<26> nos2; 412 Bitfield<27> nos3; 413 Bitfield<28> nos4; 414 Bitfield<29> nos5; 415 Bitfield<30> nos6; 416 Bitfield<31> nos7; 417 EndBitUnion(PRRR) 418 419 BitUnion32(NMRR) 420 Bitfield<1,0> ir0; 421 Bitfield<3,2> ir1; 422 Bitfield<5,4> ir2; 423 Bitfield<7,6> ir3; 424 Bitfield<9,8> ir4; 425 Bitfield<11,10> ir5; 426 Bitfield<13,12> ir6; 427 Bitfield<15,14> ir7; 428 Bitfield<17,16> or0; 429 Bitfield<19,18> or1; 430 Bitfield<21,20> or2; 431 Bitfield<23,22> or3; 432 Bitfield<25,24> or4; 433 Bitfield<27,26> or5; 434 Bitfield<29,28> or6; 435 Bitfield<31,30> or7; 436 EndBitUnion(NMRR) 437 438}; 439 440#endif // __ARCH_ARM_MISCREGS_HH__ 441