miscregs.hh revision 8058:a259ab86cabf
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 45#include "base/bitunion.hh" 46 47namespace ArmISA 48{ 49 enum ConditionCode { 50 COND_EQ = 0, 51 COND_NE, // 1 52 COND_CS, // 2 53 COND_CC, // 3 54 COND_MI, // 4 55 COND_PL, // 5 56 COND_VS, // 6 57 COND_VC, // 7 58 COND_HI, // 8 59 COND_LS, // 9 60 COND_GE, // 10 61 COND_LT, // 11 62 COND_GT, // 12 63 COND_LE, // 13 64 COND_AL, // 14 65 COND_UC // 15 66 }; 67 68 enum MiscRegIndex { 69 MISCREG_CPSR = 0, 70 MISCREG_ITSTATE, 71 MISCREG_SPSR, 72 MISCREG_SPSR_FIQ, 73 MISCREG_SPSR_IRQ, 74 MISCREG_SPSR_SVC, 75 MISCREG_SPSR_MON, 76 MISCREG_SPSR_UND, 77 MISCREG_SPSR_ABT, 78 MISCREG_FPSR, 79 MISCREG_FPSID, 80 MISCREG_FPSCR, 81 MISCREG_FPSCR_QC, // Cumulative saturation flag 82 MISCREG_FPSCR_EXC, // Cumulative FP exception flags 83 MISCREG_FPEXC, 84 MISCREG_MVFR0, 85 MISCREG_MVFR1, 86 MISCREG_SCTLR_RST, 87 MISCREG_SEV_MAILBOX, 88 89 // CP15 registers 90 MISCREG_CP15_START, 91 MISCREG_SCTLR = MISCREG_CP15_START, 92 MISCREG_DCCISW, 93 MISCREG_DCCIMVAC, 94 MISCREG_DCCMVAC, 95 MISCREG_CONTEXTIDR, 96 MISCREG_TPIDRURW, 97 MISCREG_TPIDRURO, 98 MISCREG_TPIDRPRW, 99 MISCREG_CP15ISB, 100 MISCREG_CP15DSB, 101 MISCREG_CP15DMB, 102 MISCREG_CPACR, 103 MISCREG_CLIDR, 104 MISCREG_CCSIDR, 105 MISCREG_CSSELR, 106 MISCREG_ICIALLUIS, 107 MISCREG_ICIALLU, 108 MISCREG_ICIMVAU, 109 MISCREG_BPIMVA, 110 MISCREG_BPIALLIS, 111 MISCREG_BPIALL, 112 MISCREG_MIDR, 113 MISCREG_TTBR0, 114 MISCREG_TTBR1, 115 MISCREG_TLBTR, 116 MISCREG_DACR, 117 MISCREG_TLBIALLIS, 118 MISCREG_TLBIMVAIS, 119 MISCREG_TLBIASIDIS, 120 MISCREG_TLBIMVAAIS, 121 MISCREG_ITLBIALL, 122 MISCREG_ITLBIMVA, 123 MISCREG_ITLBIASID, 124 MISCREG_DTLBIALL, 125 MISCREG_DTLBIMVA, 126 MISCREG_DTLBIASID, 127 MISCREG_TLBIALL, 128 MISCREG_TLBIMVA, 129 MISCREG_TLBIASID, 130 MISCREG_TLBIMVAA, 131 MISCREG_DFSR, 132 MISCREG_IFSR, 133 MISCREG_DFAR, 134 MISCREG_IFAR, 135 MISCREG_MPIDR, 136 MISCREG_PRRR, 137 MISCREG_NMRR, 138 MISCREG_TTBCR, 139 MISCREG_ID_PFR0, 140 MISCREG_CTR, 141 MISCREG_SCR, 142 MISCREG_SDER, 143 MISCREG_PAR, 144 MISCREG_V2PCWPR, 145 MISCREG_V2PCWPW, 146 MISCREG_V2PCWUR, 147 MISCREG_V2PCWUW, 148 MISCREG_V2POWPR, 149 MISCREG_V2POWPW, 150 MISCREG_V2POWUR, 151 MISCREG_V2POWUW, 152 MISCREG_ID_MMFR0, 153 MISCREG_ACTLR, 154 MISCREG_PMCR, 155 MISCREG_PMCCNTR, 156 MISCREG_PMCNTENSET, 157 MISCREG_PMCNTENCLR, 158 MISCREG_PMOVSR, 159 MISCREG_PMSWINC, 160 MISCREG_PMSELR, 161 MISCREG_PMCEID0, 162 MISCREG_PMCEID1, 163 MISCREG_PMC_OTHER, 164 MISCREG_PMXEVCNTR, 165 MISCREG_PMUSERENR, 166 MISCREG_PMINTENSET, 167 MISCREG_PMINTENCLR, 168 MISCREG_CP15_UNIMP_START, 169 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, 170 MISCREG_ID_PFR1, 171 MISCREG_ID_DFR0, 172 MISCREG_ID_AFR0, 173 MISCREG_ID_MMFR1, 174 MISCREG_ID_MMFR2, 175 MISCREG_ID_MMFR3, 176 MISCREG_ID_ISAR0, 177 MISCREG_ID_ISAR1, 178 MISCREG_ID_ISAR2, 179 MISCREG_ID_ISAR3, 180 MISCREG_ID_ISAR4, 181 MISCREG_ID_ISAR5, 182 MISCREG_AIDR, 183 MISCREG_ADFSR, 184 MISCREG_AIFSR, 185 MISCREG_DCIMVAC, 186 MISCREG_DCISW, 187 MISCREG_MCCSW, 188 MISCREG_DCCMVAU, 189 MISCREG_NSACR, 190 MISCREG_VBAR, 191 MISCREG_MVBAR, 192 MISCREG_ISR, 193 MISCREG_FCEIDR, 194 MISCREG_L2LATENCY, 195 196 197 MISCREG_CP15_END, 198 199 // Dummy indices 200 MISCREG_NOP = MISCREG_CP15_END, 201 MISCREG_RAZ, 202 203 NUM_MISCREGS 204 }; 205 206 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 207 unsigned crm, unsigned opc2); 208 209 const char * const miscRegName[NUM_MISCREGS] = { 210 "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 211 "spsr_mon", "spsr_und", "spsr_abt", 212 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 213 "mvfr0", "mvfr1", 214 "sctlr_rst", "sev_mailbox", 215 "sctlr", "dccisw", "dccimvac", "dccmvac", 216 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 217 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 218 "clidr", "ccsidr", "csselr", 219 "icialluis", "iciallu", "icimvau", 220 "bpimva", "bpiallis", "bpiall", 221 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 222 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 223 "itlbiall", "itlbimva", "itlbiasid", 224 "dtlbiall", "dtlbimva", "dtlbiasid", 225 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 226 "dfsr", "ifsr", "dfar", "ifar", "mpidr", 227 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr", 228 "scr", "sder", "par", 229 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 230 "v2powpr", "v2powpw", "v2powur", "v2powuw", 231 "id_mmfr0","actlr", "pmcr", "pmcntr", 232 "pmcntenset", "pmcntenclr", "pmovsr", 233 "pmswinc", "pmselr", "pmceid0", 234 "pmceid1", "pmc_other", "pmxevcntr", 235 "pmuserenr", "pmintenset", "pmintenclr", 236 // Unimplemented below 237 "tcmtr", 238 "id_pfr1", "id_dfr0", "id_afr0", 239 "id_mmfr1", "id_mmfr2", "id_mmfr3", 240 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 241 "aidr", 242 "adfsr", "aifsr", 243 "dcimvac", "dcisw", "mccsw", 244 "dccmvau", 245 "nsacr", 246 "vbar", "mvbar", "isr", "fceidr", 247 "nop", "raz" 248 }; 249 250 BitUnion32(CPSR) 251 Bitfield<31> n; 252 Bitfield<30> z; 253 Bitfield<29> c; 254 Bitfield<28> v; 255 Bitfield<27> q; 256 Bitfield<26,25> it1; 257 Bitfield<24> j; 258 Bitfield<19, 16> ge; 259 Bitfield<15,10> it2; 260 Bitfield<9> e; 261 Bitfield<8> a; 262 Bitfield<7> i; 263 Bitfield<6> f; 264 Bitfield<5> t; 265 Bitfield<4, 0> mode; 266 EndBitUnion(CPSR) 267 268 BitUnion8(ITSTATE) 269 /* Note that the split (cond, mask) below is not as in ARM ARM. 270 * But it is more convenient for simulation. The condition 271 * is always the concatenation of the top 3 bits and the next bit, 272 * which applies when one of the bottom 4 bits is set. 273 * Refer to predecoder.cc for the use case. 274 */ 275 Bitfield<7, 4> cond; 276 Bitfield<3, 0> mask; 277 // Bitfields for moving to/from CPSR 278 Bitfield<7, 2> top6; 279 Bitfield<1, 0> bottom2; 280 EndBitUnion(ITSTATE) 281 282 // This mask selects bits of the CPSR that actually go in the CondCodes 283 // integer register to allow renaming. 284 static const uint32_t CondCodesMask = 0xF80F0000; 285 286 BitUnion32(SCTLR) 287 Bitfield<31> ie; // Instruction endianness 288 Bitfield<30> te; // Thumb Exception Enable 289 Bitfield<29> afe; // Access flag enable 290 Bitfield<28> tre; // TEX Remap bit 291 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 292 Bitfield<25> ee; // Exception Endianness bit 293 Bitfield<24> ve; // Interrupt vectors enable 294 Bitfield<23> xp; // Extended page table enable bit 295 Bitfield<22> u; // Alignment (now unused) 296 Bitfield<21> fi; // Fast interrupts configuration enable 297 Bitfield<19> dz; // Divide by Zero fault enable bit 298 Bitfield<18> rao2;// Read as one 299 Bitfield<17> br; // Background region bit 300 Bitfield<16> rao3;// Read as one 301 Bitfield<14> rr; // Round robin cache replacement 302 Bitfield<13> v; // Base address for exception vectors 303 Bitfield<12> i; // instruction cache enable 304 Bitfield<11> z; // branch prediction enable bit 305 Bitfield<10> sw; // Enable swp/swpb 306 Bitfield<9,8> rs; // deprecated protection bits 307 Bitfield<6,3> rao4;// Read as one 308 Bitfield<7> b; // Endianness support (unused) 309 Bitfield<2> c; // Cache enable bit 310 Bitfield<1> a; // Alignment fault checking 311 Bitfield<0> m; // MMU enable bit 312 EndBitUnion(SCTLR) 313 314 BitUnion32(CPACR) 315 Bitfield<1, 0> cp0; 316 Bitfield<3, 2> cp1; 317 Bitfield<5, 4> cp2; 318 Bitfield<7, 6> cp3; 319 Bitfield<9, 8> cp4; 320 Bitfield<11, 10> cp5; 321 Bitfield<13, 12> cp6; 322 Bitfield<15, 14> cp7; 323 Bitfield<17, 16> cp8; 324 Bitfield<19, 18> cp9; 325 Bitfield<21, 20> cp10; 326 Bitfield<23, 22> cp11; 327 Bitfield<25, 24> cp12; 328 Bitfield<27, 26> cp13; 329 Bitfield<30> d32dis; 330 Bitfield<31> asedis; 331 EndBitUnion(CPACR) 332 333 BitUnion32(FSR) 334 Bitfield<3, 0> fsLow; 335 Bitfield<7, 4> domain; 336 Bitfield<10> fsHigh; 337 Bitfield<11> wnr; 338 Bitfield<12> ext; 339 EndBitUnion(FSR) 340 341 BitUnion32(FPSCR) 342 Bitfield<0> ioc; 343 Bitfield<1> dzc; 344 Bitfield<2> ofc; 345 Bitfield<3> ufc; 346 Bitfield<4> ixc; 347 Bitfield<7> idc; 348 Bitfield<8> ioe; 349 Bitfield<9> dze; 350 Bitfield<10> ofe; 351 Bitfield<11> ufe; 352 Bitfield<12> ixe; 353 Bitfield<15> ide; 354 Bitfield<18, 16> len; 355 Bitfield<21, 20> stride; 356 Bitfield<23, 22> rMode; 357 Bitfield<24> fz; 358 Bitfield<25> dn; 359 Bitfield<26> ahp; 360 Bitfield<27> qc; 361 Bitfield<28> v; 362 Bitfield<29> c; 363 Bitfield<30> z; 364 Bitfield<31> n; 365 EndBitUnion(FPSCR) 366 367 // This mask selects bits of the FPSCR that actually go in the FpCondCodes 368 // integer register to allow renaming. 369 static const uint32_t FpCondCodesMask = 0xF0000000; 370 // This mask selects the cumulative FP exception flags of the FPSCR. 371 static const uint32_t FpscrExcMask = 0x0000009F; 372 // This mask selects the cumulative saturation flag of the FPSCR. 373 static const uint32_t FpscrQcMask = 0x08000000; 374 375 BitUnion32(FPEXC) 376 Bitfield<31> ex; 377 Bitfield<30> en; 378 Bitfield<29, 0> subArchDefined; 379 EndBitUnion(FPEXC) 380 381 BitUnion32(MVFR0) 382 Bitfield<3, 0> advSimdRegisters; 383 Bitfield<7, 4> singlePrecision; 384 Bitfield<11, 8> doublePrecision; 385 Bitfield<15, 12> vfpExceptionTrapping; 386 Bitfield<19, 16> divide; 387 Bitfield<23, 20> squareRoot; 388 Bitfield<27, 24> shortVectors; 389 Bitfield<31, 28> roundingModes; 390 EndBitUnion(MVFR0) 391 392 BitUnion32(MVFR1) 393 Bitfield<3, 0> flushToZero; 394 Bitfield<7, 4> defaultNaN; 395 Bitfield<11, 8> advSimdLoadStore; 396 Bitfield<15, 12> advSimdInteger; 397 Bitfield<19, 16> advSimdSinglePrecision; 398 Bitfield<23, 20> advSimdHalfPrecision; 399 Bitfield<27, 24> vfpHalfPrecision; 400 Bitfield<31, 28> raz; 401 EndBitUnion(MVFR1) 402 403 BitUnion32(PRRR) 404 Bitfield<1,0> tr0; 405 Bitfield<3,2> tr1; 406 Bitfield<5,4> tr2; 407 Bitfield<7,6> tr3; 408 Bitfield<9,8> tr4; 409 Bitfield<11,10> tr5; 410 Bitfield<13,12> tr6; 411 Bitfield<15,14> tr7; 412 Bitfield<16> ds0; 413 Bitfield<17> ds1; 414 Bitfield<18> ns0; 415 Bitfield<19> ns1; 416 Bitfield<24> nos0; 417 Bitfield<25> nos1; 418 Bitfield<26> nos2; 419 Bitfield<27> nos3; 420 Bitfield<28> nos4; 421 Bitfield<29> nos5; 422 Bitfield<30> nos6; 423 Bitfield<31> nos7; 424 EndBitUnion(PRRR) 425 426 BitUnion32(NMRR) 427 Bitfield<1,0> ir0; 428 Bitfield<3,2> ir1; 429 Bitfield<5,4> ir2; 430 Bitfield<7,6> ir3; 431 Bitfield<9,8> ir4; 432 Bitfield<11,10> ir5; 433 Bitfield<13,12> ir6; 434 Bitfield<15,14> ir7; 435 Bitfield<17,16> or0; 436 Bitfield<19,18> or1; 437 Bitfield<21,20> or2; 438 Bitfield<23,22> or3; 439 Bitfield<25,24> or4; 440 Bitfield<27,26> or5; 441 Bitfield<29,28> or6; 442 Bitfield<31,30> or7; 443 EndBitUnion(NMRR) 444 445}; 446 447#endif // __ARCH_ARM_MISCREGS_HH__ 448