miscregs.hh revision 7643
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49    enum ConditionCode {
50        COND_EQ  =   0,
51        COND_NE, //  1
52        COND_CS, //  2
53        COND_CC, //  3
54        COND_MI, //  4
55        COND_PL, //  5
56        COND_VS, //  6
57        COND_VC, //  7
58        COND_HI, //  8
59        COND_LS, //  9
60        COND_GE, // 10
61        COND_LT, // 11
62        COND_GT, // 12
63        COND_LE, // 13
64        COND_AL, // 14
65        COND_UC  // 15
66    };
67
68    enum MiscRegIndex {
69        MISCREG_CPSR = 0,
70        MISCREG_ITSTATE,
71        MISCREG_SPSR,
72        MISCREG_SPSR_FIQ,
73        MISCREG_SPSR_IRQ,
74        MISCREG_SPSR_SVC,
75        MISCREG_SPSR_MON,
76        MISCREG_SPSR_UND,
77        MISCREG_SPSR_ABT,
78        MISCREG_FPSR,
79        MISCREG_FPSID,
80        MISCREG_FPSCR,
81        MISCREG_FPEXC,
82        MISCREG_MVFR0,
83        MISCREG_MVFR1,
84        MISCREG_SCTLR_RST,
85        MISCREG_SEV_MAILBOX,
86
87        // CP15 registers
88        MISCREG_CP15_START,
89        MISCREG_SCTLR = MISCREG_CP15_START,
90        MISCREG_DCCISW,
91        MISCREG_DCCIMVAC,
92        MISCREG_DCCMVAC,
93        MISCREG_CONTEXTIDR,
94        MISCREG_TPIDRURW,
95        MISCREG_TPIDRURO,
96        MISCREG_TPIDRPRW,
97        MISCREG_CP15ISB,
98        MISCREG_CP15DSB,
99        MISCREG_CP15DMB,
100        MISCREG_CPACR,
101        MISCREG_CLIDR,
102        MISCREG_CCSIDR,
103        MISCREG_CSSELR,
104        MISCREG_ICIALLUIS,
105        MISCREG_ICIALLU,
106        MISCREG_ICIMVAU,
107        MISCREG_BPIMVA,
108        MISCREG_BPIALLIS,
109        MISCREG_BPIALL,
110        MISCREG_MIDR,
111        MISCREG_TTBR0,
112        MISCREG_TTBR1,
113        MISCREG_TLBTR,
114        MISCREG_DACR,
115        MISCREG_TLBIALLIS,
116        MISCREG_TLBIMVAIS,
117        MISCREG_TLBIASIDIS,
118        MISCREG_TLBIMVAAIS,
119        MISCREG_ITLBIALL,
120        MISCREG_ITLBIMVA,
121        MISCREG_ITLBIASID,
122        MISCREG_DTLBIALL,
123        MISCREG_DTLBIMVA,
124        MISCREG_DTLBIASID,
125        MISCREG_TLBIALL,
126        MISCREG_TLBIMVA,
127        MISCREG_TLBIASID,
128        MISCREG_TLBIMVAA,
129        MISCREG_DFSR,
130        MISCREG_IFSR,
131        MISCREG_DFAR,
132        MISCREG_IFAR,
133        MISCREG_MPIDR,
134        MISCREG_PRRR,
135        MISCREG_NMRR,
136        MISCREG_TTBCR,
137        MISCREG_ID_PFR0,
138        MISCREG_CTR,
139        MISCREG_SCR,
140        MISCREG_SDER,
141        MISCREG_PAR,
142        MISCREG_V2PCWPR,
143        MISCREG_V2PCWPW,
144        MISCREG_V2PCWUR,
145        MISCREG_V2PCWUW,
146        MISCREG_V2POWPR,
147        MISCREG_V2POWPW,
148        MISCREG_V2POWUR,
149        MISCREG_V2POWUW,
150        MISCREG_ID_MMFR0,
151        MISCREG_ACTLR,
152        MISCREG_PMCR,
153        MISCREG_PMCCNTR,
154        MISCREG_PMCNTENSET,
155        MISCREG_PMCNTENCLR,
156        MISCREG_PMOVSR,
157        MISCREG_PMSWINC,
158        MISCREG_PMSELR,
159        MISCREG_PMCEID0,
160        MISCREG_PMCEID1,
161        MISCREG_PMC_OTHER,
162        MISCREG_PMXEVCNTR,
163        MISCREG_PMUSERENR,
164        MISCREG_PMINTENSET,
165        MISCREG_PMINTENCLR,
166        MISCREG_CP15_UNIMP_START,
167        MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
168        MISCREG_ID_PFR1,
169        MISCREG_ID_DFR0,
170        MISCREG_ID_AFR0,
171        MISCREG_ID_MMFR1,
172        MISCREG_ID_MMFR2,
173        MISCREG_ID_MMFR3,
174        MISCREG_ID_ISAR0,
175        MISCREG_ID_ISAR1,
176        MISCREG_ID_ISAR2,
177        MISCREG_ID_ISAR3,
178        MISCREG_ID_ISAR4,
179        MISCREG_ID_ISAR5,
180        MISCREG_AIDR,
181        MISCREG_ADFSR,
182        MISCREG_AIFSR,
183        MISCREG_DCIMVAC,
184        MISCREG_DCISW,
185        MISCREG_MCCSW,
186        MISCREG_DCCMVAU,
187        MISCREG_NSACR,
188        MISCREG_VBAR,
189        MISCREG_MVBAR,
190        MISCREG_ISR,
191        MISCREG_FCEIDR,
192
193
194        MISCREG_CP15_END,
195
196        // Dummy indices
197        MISCREG_NOP = MISCREG_CP15_END,
198        MISCREG_RAZ,
199
200        NUM_MISCREGS
201    };
202
203    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
204                               unsigned crm, unsigned opc2);
205
206    const char * const miscRegName[NUM_MISCREGS] = {
207        "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
208        "spsr_mon", "spsr_und", "spsr_abt",
209        "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
210        "sctlr_rst", "sev_mailbox",
211        "sctlr", "dccisw", "dccimvac", "dccmvac",
212        "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
213        "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
214        "clidr", "ccsidr", "csselr",
215        "icialluis", "iciallu", "icimvau",
216        "bpimva", "bpiallis", "bpiall",
217        "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
218        "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
219        "itlbiall", "itlbimva", "itlbiasid",
220        "dtlbiall", "dtlbimva", "dtlbiasid",
221        "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
222        "dfsr", "ifsr", "dfar", "ifar", "mpidr",
223        "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr",
224        "scr", "sder", "par",
225        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
226        "v2powpr", "v2powpw", "v2powur", "v2powuw",
227        "id_mmfr0","actlr", "pmcr", "pmcntr",
228        "pmcntenset", "pmcntenclr", "pmovsr",
229        "pmswinc", "pmselr", "pmceid0",
230        "pmceid1", "pmc_other", "pmxevcntr",
231        "pmuserenr", "pmintenset", "pmintenclr",
232         // Unimplemented below
233        "tcmtr",
234        "id_pfr1", "id_dfr0", "id_afr0",
235        "id_mmfr1", "id_mmfr2", "id_mmfr3",
236        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
237        "aidr",
238        "adfsr", "aifsr",
239        "dcimvac", "dcisw", "mccsw",
240        "dccmvau",
241        "nsacr",
242        "vbar", "mvbar", "isr", "fceidr",
243        "nop", "raz"
244    };
245
246    BitUnion32(CPSR)
247        Bitfield<31> n;
248        Bitfield<30> z;
249        Bitfield<29> c;
250        Bitfield<28> v;
251        Bitfield<27> q;
252        Bitfield<26,25> it1;
253        Bitfield<24> j;
254        Bitfield<19, 16> ge;
255        Bitfield<15,10> it2;
256        Bitfield<9> e;
257        Bitfield<8> a;
258        Bitfield<7> i;
259        Bitfield<6> f;
260        Bitfield<5> t;
261        Bitfield<4, 0> mode;
262    EndBitUnion(CPSR)
263
264    BitUnion8(ITSTATE)
265        Bitfield<7, 4> cond;
266        Bitfield<3, 0> mask;
267        // Bitfields for moving to/from CPSR
268        Bitfield<7, 2> top6;
269        Bitfield<1, 0> bottom2;
270    EndBitUnion(ITSTATE)
271
272    // This mask selects bits of the CPSR that actually go in the CondCodes
273    // integer register to allow renaming.
274    static const uint32_t CondCodesMask = 0xF80F0000;
275
276    BitUnion32(SCTLR)
277        Bitfield<31> ie;  // Instruction endianness
278        Bitfield<30> te;  // Thumb Exception Enable
279        Bitfield<29> afe; // Access flag enable
280        Bitfield<28> tre; // TEX Remap bit
281        Bitfield<27> nmfi;// Non-maskable fast interrupts enable
282        Bitfield<25> ee;  // Exception Endianness bit
283        Bitfield<24> ve;  // Interrupt vectors enable
284        Bitfield<23> xp; //  Extended page table enable bit
285        Bitfield<22> u;   // Alignment (now unused)
286        Bitfield<21> fi;  // Fast interrupts configuration enable
287        Bitfield<19> dz;  // Divide by Zero fault enable bit
288        Bitfield<18> rao2;// Read as one
289        Bitfield<17> br;  // Background region bit
290        Bitfield<16> rao3;// Read as one
291        Bitfield<14> rr;  // Round robin cache replacement
292        Bitfield<13> v;   // Base address for exception vectors
293        Bitfield<12> i;   // instruction cache enable
294        Bitfield<11> z;   // branch prediction enable bit
295        Bitfield<10> sw;  // Enable swp/swpb
296        Bitfield<9,8> rs;   // deprecated protection bits
297        Bitfield<6,3> rao4;// Read as one
298        Bitfield<7>  b;   // Endianness support (unused)
299        Bitfield<2>  c;   // Cache enable bit
300        Bitfield<1>  a;   // Alignment fault checking
301        Bitfield<0>  m;   // MMU enable bit
302    EndBitUnion(SCTLR)
303
304    BitUnion32(CPACR)
305        Bitfield<1, 0> cp0;
306        Bitfield<3, 2> cp1;
307        Bitfield<5, 4> cp2;
308        Bitfield<7, 6> cp3;
309        Bitfield<9, 8> cp4;
310        Bitfield<11, 10> cp5;
311        Bitfield<13, 12> cp6;
312        Bitfield<15, 14> cp7;
313        Bitfield<17, 16> cp8;
314        Bitfield<19, 18> cp9;
315        Bitfield<21, 20> cp10;
316        Bitfield<23, 22> cp11;
317        Bitfield<25, 24> cp12;
318        Bitfield<27, 26> cp13;
319        Bitfield<30> d32dis;
320        Bitfield<31> asedis;
321    EndBitUnion(CPACR)
322
323    BitUnion32(FSR)
324        Bitfield<3, 0> fsLow;
325        Bitfield<7, 4> domain;
326        Bitfield<10> fsHigh;
327        Bitfield<11> wnr;
328        Bitfield<12> ext;
329    EndBitUnion(FSR)
330
331    BitUnion32(FPSCR)
332        Bitfield<0> ioc;
333        Bitfield<1> dzc;
334        Bitfield<2> ofc;
335        Bitfield<3> ufc;
336        Bitfield<4> ixc;
337        Bitfield<7> idc;
338        Bitfield<8> ioe;
339        Bitfield<9> dze;
340        Bitfield<10> ofe;
341        Bitfield<11> ufe;
342        Bitfield<12> ixe;
343        Bitfield<15> ide;
344        Bitfield<18, 16> len;
345        Bitfield<21, 20> stride;
346        Bitfield<23, 22> rMode;
347        Bitfield<24> fz;
348        Bitfield<25> dn;
349        Bitfield<26> ahp;
350        Bitfield<27> qc;
351        Bitfield<28> v;
352        Bitfield<29> c;
353        Bitfield<30> z;
354        Bitfield<31> n;
355    EndBitUnion(FPSCR)
356
357    // This mask selects bits of the FPSCR that actually go in the FpCondCodes
358    // integer register to allow renaming.
359    static const uint32_t FpCondCodesMask = 0xF800009F;
360
361    BitUnion32(FPEXC)
362        Bitfield<31> ex;
363        Bitfield<30> en;
364        Bitfield<29, 0> subArchDefined;
365    EndBitUnion(FPEXC)
366
367    BitUnion32(MVFR0)
368        Bitfield<3, 0> advSimdRegisters;
369        Bitfield<7, 4> singlePrecision;
370        Bitfield<11, 8> doublePrecision;
371        Bitfield<15, 12> vfpExceptionTrapping;
372        Bitfield<19, 16> divide;
373        Bitfield<23, 20> squareRoot;
374        Bitfield<27, 24> shortVectors;
375        Bitfield<31, 28> roundingModes;
376    EndBitUnion(MVFR0)
377
378    BitUnion32(MVFR1)
379        Bitfield<3, 0> flushToZero;
380        Bitfield<7, 4> defaultNaN;
381        Bitfield<11, 8> advSimdLoadStore;
382        Bitfield<15, 12> advSimdInteger;
383        Bitfield<19, 16> advSimdSinglePrecision;
384        Bitfield<23, 20> advSimdHalfPrecision;
385        Bitfield<27, 24> vfpHalfPrecision;
386        Bitfield<31, 28> raz;
387    EndBitUnion(MVFR1)
388
389    BitUnion32(PRRR)
390       Bitfield<1,0> tr0;
391       Bitfield<3,2> tr1;
392       Bitfield<5,4> tr2;
393       Bitfield<7,6> tr3;
394       Bitfield<9,8> tr4;
395       Bitfield<11,10> tr5;
396       Bitfield<13,12> tr6;
397       Bitfield<15,14> tr7;
398       Bitfield<16> ds0;
399       Bitfield<17> ds1;
400       Bitfield<18> ns0;
401       Bitfield<19> ns1;
402       Bitfield<24> nos0;
403       Bitfield<25> nos1;
404       Bitfield<26> nos2;
405       Bitfield<27> nos3;
406       Bitfield<28> nos4;
407       Bitfield<29> nos5;
408       Bitfield<30> nos6;
409       Bitfield<31> nos7;
410   EndBitUnion(PRRR)
411
412   BitUnion32(NMRR)
413       Bitfield<1,0> ir0;
414       Bitfield<3,2> ir1;
415       Bitfield<5,4> ir2;
416       Bitfield<7,6> ir3;
417       Bitfield<9,8> ir4;
418       Bitfield<11,10> ir5;
419       Bitfield<13,12> ir6;
420       Bitfield<15,14> ir7;
421       Bitfield<17,16> or0;
422       Bitfield<19,18> or1;
423       Bitfield<21,20> or2;
424       Bitfield<23,22> or3;
425       Bitfield<25,24> or4;
426       Bitfield<27,26> or5;
427       Bitfield<29,28> or6;
428       Bitfield<31,30> or7;
429   EndBitUnion(NMRR)
430
431};
432
433#endif // __ARCH_ARM_MISCREGS_HH__
434