miscregs.hh revision 7406
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49    enum ConditionCode {
50        COND_EQ  =   0,
51        COND_NE, //  1
52        COND_CS, //  2
53        COND_CC, //  3
54        COND_MI, //  4
55        COND_PL, //  5
56        COND_VS, //  6
57        COND_VC, //  7
58        COND_HI, //  8
59        COND_LS, //  9
60        COND_GE, // 10
61        COND_LT, // 11
62        COND_GT, // 12
63        COND_LE, // 13
64        COND_AL, // 14
65        COND_UC  // 15
66    };
67
68    enum MiscRegIndex {
69        MISCREG_CPSR = 0,
70        MISCREG_SPSR,
71        MISCREG_SPSR_FIQ,
72        MISCREG_SPSR_IRQ,
73        MISCREG_SPSR_SVC,
74        MISCREG_SPSR_MON,
75        MISCREG_SPSR_UND,
76        MISCREG_SPSR_ABT,
77        MISCREG_FPSR,
78        MISCREG_FPSID,
79        MISCREG_FPSCR,
80        MISCREG_FPEXC,
81        MISCREG_MVFR0,
82        MISCREG_MVFR1,
83        MISCREG_SCTLR_RST,
84        MISCREG_SEV_MAILBOX,
85
86        // CP15 registers
87        MISCREG_CP15_START,
88        MISCREG_SCTLR = MISCREG_CP15_START,
89        MISCREG_DCCISW,
90        MISCREG_DCCIMVAC,
91        MISCREG_DCCMVAC,
92        MISCREG_CONTEXTIDR,
93        MISCREG_TPIDRURW,
94        MISCREG_TPIDRURO,
95        MISCREG_TPIDRPRW,
96        MISCREG_CP15ISB,
97        MISCREG_CP15DSB,
98        MISCREG_CP15DMB,
99        MISCREG_CPACR,
100        MISCREG_CLIDR,
101        MISCREG_CCSIDR,
102        MISCREG_CSSELR,
103        MISCREG_ICIALLUIS,
104        MISCREG_ICIALLU,
105        MISCREG_ICIMVAU,
106        MISCREG_BPIMVA,
107        MISCREG_BPIALLIS,
108        MISCREG_BPIALL,
109        MISCREG_MIDR,
110        MISCREG_TTBR0,
111        MISCREG_TTBR1,
112        MISCREG_TLBTR,
113        MISCREG_DACR,
114        MISCREG_TLBIALLIS,
115        MISCREG_TLBIMVAIS,
116        MISCREG_TLBIASIDIS,
117        MISCREG_TLBIMVAAIS,
118        MISCREG_ITLBIALL,
119        MISCREG_ITLBIMVA,
120        MISCREG_ITLBIASID,
121        MISCREG_DTLBIALL,
122        MISCREG_DTLBIMVA,
123        MISCREG_DTLBIASID,
124        MISCREG_TLBIALL,
125        MISCREG_TLBIMVA,
126        MISCREG_TLBIASID,
127        MISCREG_TLBIMVAA,
128        MISCREG_DFSR,
129        MISCREG_IFSR,
130        MISCREG_DFAR,
131        MISCREG_IFAR,
132        MISCREG_MPIDR,
133        MISCREG_PRRR,
134        MISCREG_NMRR,
135        MISCREG_TTBCR,
136        MISCREG_ID_PFR0,
137        MISCREG_CTR,
138        MISCREG_SCR,
139        MISCREG_SDER,
140        MISCREG_CP15_UNIMP_START,
141        MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
142        MISCREG_ID_PFR1,
143        MISCREG_ID_DFR0,
144        MISCREG_ID_AFR0,
145        MISCREG_ID_MMFR0,
146        MISCREG_ID_MMFR1,
147        MISCREG_ID_MMFR2,
148        MISCREG_ID_MMFR3,
149        MISCREG_ID_ISAR0,
150        MISCREG_ID_ISAR1,
151        MISCREG_ID_ISAR2,
152        MISCREG_ID_ISAR3,
153        MISCREG_ID_ISAR4,
154        MISCREG_ID_ISAR5,
155        MISCREG_PAR,
156        MISCREG_AIDR,
157        MISCREG_ACTLR,
158        MISCREG_ADFSR,
159        MISCREG_AIFSR,
160        MISCREG_DCIMVAC,
161        MISCREG_DCISW,
162        MISCREG_MCCSW,
163        MISCREG_DCCMVAU,
164        MISCREG_NSACR,
165        MISCREG_V2PCWPR,
166        MISCREG_V2PCWPW,
167        MISCREG_V2PCWUR,
168        MISCREG_V2PCWUW,
169        MISCREG_V2POWPR,
170        MISCREG_V2POWPW,
171        MISCREG_V2POWUR,
172        MISCREG_V2POWUW,
173        MISCREG_VBAR,
174        MISCREG_MVBAR,
175        MISCREG_ISR,
176        MISCREG_FCEIDR,
177
178
179        MISCREG_CP15_END,
180
181        // Dummy indices
182        MISCREG_NOP = MISCREG_CP15_END,
183        MISCREG_RAZ,
184
185        NUM_MISCREGS
186    };
187
188    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
189                               unsigned crm, unsigned opc2);
190
191    const char * const miscRegName[NUM_MISCREGS] = {
192        "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
193        "spsr_mon", "spsr_und", "spsr_abt",
194        "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
195        "sctlr_rst", "sev_mailbox",
196        "sctlr", "dccisw", "dccimvac", "dccmvac",
197        "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
198        "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
199        "clidr", "ccsidr", "csselr",
200        "icialluis", "iciallu", "icimvau",
201        "bpimva", "bpiallis", "bpiall",
202        "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
203        "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
204        "itlbiall", "itlbimva", "itlbiasid",
205        "dtlbiall", "dtlbimva", "dtlbiasid",
206        "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
207        "dfsr", "ifsr", "dfar", "ifar", "mpidr",
208        "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr"
209        "scr", "sder"
210        // Unimplemented below
211        "tcmtr",
212        "id_pfr1", "id_dfr0", "id_afr0",
213        "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
214        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
215        "par", "aidr", "actlr",
216        "adfsr", "aifsr",
217        "dcimvac", "dcisw", "mccsw",
218        "dccmvau",
219        "nsacr",
220        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
221        "v2powpr", "v2powpw", "v2powur", "v2powuw",
222        "vbar", "mvbar", "isr", "fceidr",
223        "nop", "raz"
224    };
225
226    BitUnion32(CPSR)
227        Bitfield<31> n;
228        Bitfield<30> z;
229        Bitfield<29> c;
230        Bitfield<28> v;
231        Bitfield<27> q;
232        Bitfield<26,25> it1;
233        Bitfield<24> j;
234        Bitfield<19, 16> ge;
235        Bitfield<15,10> it2;
236        Bitfield<9> e;
237        Bitfield<8> a;
238        Bitfield<7> i;
239        Bitfield<6> f;
240        Bitfield<5> t;
241        Bitfield<4, 0> mode;
242    EndBitUnion(CPSR)
243
244    // This mask selects bits of the CPSR that actually go in the CondCodes
245    // integer register to allow renaming.
246    static const uint32_t CondCodesMask = 0xF80F0000;
247
248    BitUnion32(SCTLR)
249        Bitfield<31> ie;  // Instruction endianness
250        Bitfield<30> te;  // Thumb Exception Enable
251        Bitfield<29> afe; // Access flag enable
252        Bitfield<28> tre; // TEX Remap bit
253        Bitfield<27> nmfi;// Non-maskable fast interrupts enable
254        Bitfield<25> ee;  // Exception Endianness bit
255        Bitfield<24> ve;  // Interrupt vectors enable
256        Bitfield<23> xp; //  Extended page table enable bit
257        Bitfield<22> u;   // Alignment (now unused)
258        Bitfield<21> fi;  // Fast interrupts configuration enable
259        Bitfield<19> dz;  // Divide by Zero fault enable bit
260        Bitfield<18> rao2;// Read as one
261        Bitfield<17> br;  // Background region bit
262        Bitfield<16> rao3;// Read as one
263        Bitfield<14> rr;  // Round robin cache replacement
264        Bitfield<13> v;   // Base address for exception vectors
265        Bitfield<12> i;   // instruction cache enable
266        Bitfield<11> z;   // branch prediction enable bit
267        Bitfield<10> sw;  // Enable swp/swpb
268        Bitfield<9,8> rs;   // deprecated protection bits
269        Bitfield<6,3> rao4;// Read as one
270        Bitfield<7>  b;   // Endianness support (unused)
271        Bitfield<2>  c;   // Cache enable bit
272        Bitfield<1>  a;   // Alignment fault checking
273        Bitfield<0>  m;   // MMU enable bit
274    EndBitUnion(SCTLR)
275
276    BitUnion32(CPACR)
277        Bitfield<1, 0> cp0;
278        Bitfield<3, 2> cp1;
279        Bitfield<5, 4> cp2;
280        Bitfield<7, 6> cp3;
281        Bitfield<9, 8> cp4;
282        Bitfield<11, 10> cp5;
283        Bitfield<13, 12> cp6;
284        Bitfield<15, 14> cp7;
285        Bitfield<17, 16> cp8;
286        Bitfield<19, 18> cp9;
287        Bitfield<21, 20> cp10;
288        Bitfield<23, 22> cp11;
289        Bitfield<25, 24> cp12;
290        Bitfield<27, 26> cp13;
291        Bitfield<30> d32dis;
292        Bitfield<31> asedis;
293    EndBitUnion(CPACR)
294
295    BitUnion32(FSR)
296        Bitfield<3, 0> fsLow;
297        Bitfield<7, 4> domain;
298        Bitfield<10> fsHigh;
299        Bitfield<11> wnr;
300        Bitfield<12> ext;
301    EndBitUnion(FSR)
302
303    BitUnion32(FPSCR)
304        Bitfield<0> ioc;
305        Bitfield<1> dzc;
306        Bitfield<2> ofc;
307        Bitfield<3> ufc;
308        Bitfield<4> ixc;
309        Bitfield<7> idc;
310        Bitfield<8> ioe;
311        Bitfield<9> dze;
312        Bitfield<10> ofe;
313        Bitfield<11> ufe;
314        Bitfield<12> ixe;
315        Bitfield<15> ide;
316        Bitfield<18, 16> len;
317        Bitfield<21, 20> stride;
318        Bitfield<23, 22> rMode;
319        Bitfield<24> fz;
320        Bitfield<25> dn;
321        Bitfield<26> ahp;
322        Bitfield<27> qc;
323        Bitfield<28> v;
324        Bitfield<29> c;
325        Bitfield<30> z;
326        Bitfield<31> n;
327    EndBitUnion(FPSCR)
328
329    BitUnion32(MVFR0)
330        Bitfield<3, 0> advSimdRegisters;
331        Bitfield<7, 4> singlePrecision;
332        Bitfield<11, 8> doublePrecision;
333        Bitfield<15, 12> vfpExceptionTrapping;
334        Bitfield<19, 16> divide;
335        Bitfield<23, 20> squareRoot;
336        Bitfield<27, 24> shortVectors;
337        Bitfield<31, 28> roundingModes;
338    EndBitUnion(MVFR0)
339
340    BitUnion32(MVFR1)
341        Bitfield<3, 0> flushToZero;
342        Bitfield<7, 4> defaultNaN;
343        Bitfield<11, 8> advSimdLoadStore;
344        Bitfield<15, 12> advSimdInteger;
345        Bitfield<19, 16> advSimdSinglePrecision;
346        Bitfield<23, 20> advSimdHalfPrecision;
347        Bitfield<27, 24> vfpHalfPrecision;
348        Bitfield<31, 28> raz;
349    EndBitUnion(MVFR1)
350
351    BitUnion32(PRRR)
352       Bitfield<1,0> tr0;
353       Bitfield<3,2> tr1;
354       Bitfield<5,4> tr2;
355       Bitfield<7,6> tr3;
356       Bitfield<9,8> tr4;
357       Bitfield<11,10> tr5;
358       Bitfield<13,12> tr6;
359       Bitfield<15,14> tr7;
360       Bitfield<16> ds0;
361       Bitfield<17> ds1;
362       Bitfield<18> ns0;
363       Bitfield<19> ns1;
364       Bitfield<24> nos0;
365       Bitfield<25> nos1;
366       Bitfield<26> nos2;
367       Bitfield<27> nos3;
368       Bitfield<28> nos4;
369       Bitfield<29> nos5;
370       Bitfield<30> nos6;
371       Bitfield<31> nos7;
372   EndBitUnion(PRRR)
373
374   BitUnion32(NMRR)
375       Bitfield<1,0> ir0;
376       Bitfield<3,2> ir1;
377       Bitfield<5,4> ir2;
378       Bitfield<7,6> ir3;
379       Bitfield<9,8> ir4;
380       Bitfield<11,10> ir5;
381       Bitfield<13,12> ir6;
382       Bitfield<15,14> ir7;
383       Bitfield<17,16> or0;
384       Bitfield<19,18> or1;
385       Bitfield<21,20> or2;
386       Bitfield<23,22> or3;
387       Bitfield<25,24> or4;
388       Bitfield<27,26> or5;
389       Bitfield<29,28> or6;
390       Bitfield<31,30> or7;
391   EndBitUnion(NMRR)
392
393};
394
395#endif // __ARCH_ARM_MISCREGS_HH__
396