miscregs.hh revision 7355
12068SN/A/* 22068SN/A * Copyright (c) 2010 ARM Limited 32188SN/A * All rights reserved 42068SN/A * 52068SN/A * The license below extends only to copyright in the software and shall 62068SN/A * not be construed as granting a license to any other intellectual 72068SN/A * property including but not limited to intellectual property relating 82068SN/A * to a hardware implementation of the functionality of the software 92068SN/A * licensed hereunder. You may use the software subject to the license 102068SN/A * terms below provided that you ensure that this notice is replicated 112068SN/A * unmodified and in its entirety in all distributions of the software, 122068SN/A * modified or unmodified, in source code or in binary form. 132068SN/A * 142068SN/A * Copyright (c) 2009 The Regents of The University of Michigan 152068SN/A * All rights reserved. 162068SN/A * 172068SN/A * Redistribution and use in source and binary forms, with or without 182068SN/A * modification, are permitted provided that the following conditions are 192068SN/A * met: redistributions of source code must retain the above copyright 202068SN/A * notice, this list of conditions and the following disclaimer; 212068SN/A * redistributions in binary form must reproduce the above copyright 222068SN/A * notice, this list of conditions and the following disclaimer in the 232068SN/A * documentation and/or other materials provided with the distribution; 242068SN/A * neither the name of the copyright holders nor the names of its 252068SN/A * contributors may be used to endorse or promote products derived from 262068SN/A * this software without specific prior written permission. 272068SN/A * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302068SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312649Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322649Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332649Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342649Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352649Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362068SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372068SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382068SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392068SN/A * 402068SN/A * Authors: Gabe Black 412068SN/A */ 422068SN/A#ifndef __ARCH_ARM_MISCREGS_HH__ 432068SN/A#define __ARCH_ARM_MISCREGS_HH__ 442075SN/A 452075SN/A#include "base/bitunion.hh" 462075SN/A 472075SN/Anamespace ArmISA 482075SN/A{ 492075SN/A enum ConditionCode { 502069SN/A COND_EQ = 0, 512069SN/A COND_NE, // 1 522075SN/A COND_CS, // 2 532068SN/A COND_CC, // 3 542068SN/A COND_MI, // 4 552068SN/A COND_PL, // 5 562075SN/A COND_VS, // 6 572075SN/A COND_VC, // 7 582068SN/A COND_HI, // 8 592068SN/A COND_LS, // 9 602075SN/A COND_GE, // 10 612075SN/A COND_LT, // 11 622068SN/A COND_GT, // 12 632068SN/A COND_LE, // 13 642068SN/A COND_AL, // 14 652075SN/A COND_UC // 15 662075SN/A }; 672075SN/A 682075SN/A enum MiscRegIndex { 692075SN/A MISCREG_CPSR = 0, 702075SN/A MISCREG_SPSR, 712075SN/A MISCREG_SPSR_FIQ, 722069SN/A MISCREG_SPSR_IRQ, 732069SN/A MISCREG_SPSR_SVC, 742075SN/A MISCREG_SPSR_MON, 752068SN/A MISCREG_SPSR_UND, 762068SN/A MISCREG_SPSR_ABT, 772068SN/A MISCREG_FPSR, 782075SN/A MISCREG_FPSID, 792068SN/A MISCREG_FPSCR, 802069SN/A MISCREG_FPEXC, 812068SN/A MISCREG_MVFR0, 822068SN/A MISCREG_MVFR1, 832075SN/A MISCREG_SEV_MAILBOX, 842075SN/A 852068SN/A // CP15 registers 862069SN/A MISCREG_CP15_START, 872068SN/A MISCREG_SCTLR = MISCREG_CP15_START, 882068SN/A MISCREG_DCCISW, 892068SN/A MISCREG_DCCIMVAC, 902068SN/A MISCREG_DCCMVAC, 912068SN/A MISCREG_CONTEXTIDR, 922068SN/A MISCREG_TPIDRURW, 932068SN/A MISCREG_TPIDRURO, 942068SN/A MISCREG_TPIDRPRW, 952075SN/A MISCREG_CP15ISB, 962068SN/A MISCREG_CP15DSB, 972068SN/A MISCREG_CP15DMB, 982068SN/A MISCREG_CPACR, 992068SN/A MISCREG_CLIDR, 1002068SN/A MISCREG_CCSIDR, 1012068SN/A MISCREG_CSSELR, 1022068SN/A MISCREG_ICIALLUIS, 1032068SN/A MISCREG_ICIALLU, 1042068SN/A MISCREG_ICIMVAU, 1052068SN/A MISCREG_BPIMVA, 1062068SN/A MISCREG_BPIALLIS, 1072068SN/A MISCREG_BPIALL, 1082147SN/A MISCREG_MIDR, 1092068SN/A MISCREG_TTBR0, 1102068SN/A MISCREG_TTBR1, 1112068SN/A MISCREG_TLBTR, 1122068SN/A MISCREG_DACR, 1132068SN/A MISCREG_TLBIALLIS, 1142068SN/A MISCREG_TLBIMVAIS, 1152068SN/A MISCREG_TLBIASIDIS, 1162068SN/A MISCREG_TLBIMVAAIS, 1172068SN/A MISCREG_ITLBIALL, 1182068SN/A MISCREG_ITLBIMVA, 1192068SN/A MISCREG_ITLBIASID, 1202147SN/A MISCREG_DTLBIALL, 1212068SN/A MISCREG_DTLBIMVA, 1222068SN/A MISCREG_DTLBIASID, 1232068SN/A MISCREG_TLBIALL, 1242068SN/A MISCREG_TLBIMVA, 1252068SN/A MISCREG_TLBIASID, 1262068SN/A MISCREG_TLBIMVAA, 1272068SN/A MISCREG_CP15_UNIMP_START, 1282068SN/A MISCREG_CTR = MISCREG_CP15_UNIMP_START, 1292068SN/A MISCREG_TCMTR, 1302068SN/A MISCREG_MPIDR, 1312068SN/A MISCREG_ID_PFR0, 1322068SN/A MISCREG_ID_PFR1, 1332068SN/A MISCREG_ID_DFR0, 1342147SN/A MISCREG_ID_AFR0, 1352068SN/A MISCREG_ID_MMFR0, 1362068SN/A MISCREG_ID_MMFR1, 1372068SN/A MISCREG_ID_MMFR2, 1382068SN/A MISCREG_ID_MMFR3, 1392068SN/A MISCREG_ID_ISAR0, 1402068SN/A MISCREG_ID_ISAR1, 1412068SN/A MISCREG_ID_ISAR2, 1422068SN/A MISCREG_ID_ISAR3, 1432068SN/A MISCREG_ID_ISAR4, 1442068SN/A MISCREG_ID_ISAR5, 1452068SN/A MISCREG_PAR, 1462068SN/A MISCREG_AIDR, 1472068SN/A MISCREG_ACTLR, 1482147SN/A MISCREG_DFSR, 1492068SN/A MISCREG_IFSR, 1502068SN/A MISCREG_ADFSR, 1512068SN/A MISCREG_AIFSR, 1522068SN/A MISCREG_DFAR, 1532068SN/A MISCREG_IFAR, 1542068SN/A MISCREG_DCIMVAC, 1552068SN/A MISCREG_DCISW, 1562068SN/A MISCREG_MCCSW, 1572068SN/A MISCREG_DCCMVAU, 1582068SN/A MISCREG_SCR, 1592068SN/A MISCREG_SDER, 1602068SN/A MISCREG_NSACR, 1612068SN/A MISCREG_TTBCR, 1622068SN/A MISCREG_V2PCWPR, 1632068SN/A MISCREG_V2PCWPW, 1642068SN/A MISCREG_V2PCWUR, 1652068SN/A MISCREG_V2PCWUW, 1662068SN/A MISCREG_V2POWPR, 1672068SN/A MISCREG_V2POWPW, 1682068SN/A MISCREG_V2POWUR, 1692068SN/A MISCREG_V2POWUW, 1702068SN/A MISCREG_PRRR, 1712068SN/A MISCREG_NMRR, 1722068SN/A MISCREG_VBAR, 1732068SN/A MISCREG_MVBAR, 1742068SN/A MISCREG_ISR, 1752068SN/A MISCREG_FCEIDR, 1762068SN/A 1772068SN/A 1782068SN/A MISCREG_CP15_END, 1792068SN/A 1802068SN/A // Dummy indices 1812068SN/A MISCREG_NOP = MISCREG_CP15_END, 1822068SN/A MISCREG_RAZ, 1832068SN/A 1842068SN/A NUM_MISCREGS 1852068SN/A }; 1862068SN/A 1872068SN/A MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 1882068SN/A unsigned crm, unsigned opc2); 1892068SN/A 1902068SN/A const char * const miscRegName[NUM_MISCREGS] = { 1912068SN/A "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 1922068SN/A "spsr_mon", "spsr_und", "spsr_abt", 1932068SN/A "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1", 1942068SN/A "sev_mailbox", 1952068SN/A "sctlr", "dccisw", "dccimvac", "dccmvac", 1962068SN/A "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 1972068SN/A "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 1982068SN/A "clidr", "ccsidr", "csselr", 1992068SN/A "icialluis", "iciallu", "icimvau", 2002068SN/A "bpimva", "bpiallis", "bpiall", 2012068SN/A "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", 2022068SN/A "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 2032068SN/A "itlbiall", "itlbimva", "itlbiasid", 2042068SN/A "dtlbiall", "dtlbimva", "dtlbiasid", 2052068SN/A "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 2062068SN/A "ctr", "tcmtr", "mpidr", 2072068SN/A "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", 2082068SN/A "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", 2092068SN/A "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 2102068SN/A "par", "aidr", "actlr", 2112068SN/A "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", 2122068SN/A "dcimvac", "dcisw", "mccsw", 2132068SN/A "dccmvau", 2142068SN/A "scr", "sder", "nsacr", "ttbcr", 2152068SN/A "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 2162068SN/A "v2powpr", "v2powpw", "v2powur", "v2powuw", 2172068SN/A "prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr", 2182068SN/A "nop", "raz" 2192068SN/A }; 2202068SN/A 2212068SN/A BitUnion32(CPSR) 2222068SN/A Bitfield<31> n; 2232068SN/A Bitfield<30> z; 2242068SN/A Bitfield<29> c; 2252068SN/A Bitfield<28> v; 2262068SN/A Bitfield<27> q; 2272068SN/A Bitfield<26,25> it1; 2282068SN/A Bitfield<24> j; 2292068SN/A Bitfield<19, 16> ge; 2302068SN/A Bitfield<15,10> it2; 2312068SN/A Bitfield<9> e; 2322068SN/A Bitfield<8> a; 2332068SN/A Bitfield<7> i; 2342068SN/A Bitfield<6> f; 2352068SN/A Bitfield<5> t; 2362068SN/A Bitfield<4, 0> mode; 2372068SN/A EndBitUnion(CPSR) 2382068SN/A 2392068SN/A // This mask selects bits of the CPSR that actually go in the CondCodes 2402068SN/A // integer register to allow renaming. 2412068SN/A static const uint32_t CondCodesMask = 0xF80F0000; 2422068SN/A 2432068SN/A BitUnion32(SCTLR) 2442068SN/A Bitfield<30> te; // Thumb Exception Enable 2452068SN/A Bitfield<29> afe; // Access flag enable 2462068SN/A Bitfield<28> tre; // TEX Remap bit 2472068SN/A Bitfield<27> nmfi;// Non-maskable fast interrupts enable 2482068SN/A Bitfield<25> ee; // Exception Endianness bit 2492068SN/A Bitfield<24> ve; // Interrupt vectors enable 2502068SN/A Bitfield<23> rao1;// Read as one 2512068SN/A Bitfield<22> u; // Alignment (now unused) 2522068SN/A Bitfield<21> fi; // Fast interrupts configuration enable 2532068SN/A Bitfield<18> rao2;// Read as one 2542068SN/A Bitfield<17> ha; // Hardware access flag enable 2552068SN/A Bitfield<16> rao3;// Read as one 2562068SN/A Bitfield<14> rr; // Round robin cache replacement 2572068SN/A Bitfield<13> v; // Base address for exception vectors 2582068SN/A Bitfield<12> i; // instruction cache enable 2592068SN/A Bitfield<11> z; // branch prediction enable bit 2602068SN/A Bitfield<10> sw; // Enable swp/swpb 2612068SN/A Bitfield<6,3> rao4;// Read as one 2622068SN/A Bitfield<7> b; // Endianness support (unused) 2632068SN/A Bitfield<2> c; // Cache enable bit 2642068SN/A Bitfield<1> a; // Alignment fault checking 2652068SN/A Bitfield<0> m; // MMU enable bit 2662068SN/A EndBitUnion(SCTLR) 2672068SN/A 2682068SN/A BitUnion32(CPACR) 2692068SN/A Bitfield<1, 0> cp0; 2702068SN/A Bitfield<3, 2> cp1; 2712068SN/A Bitfield<5, 4> cp2; 2722068SN/A Bitfield<7, 6> cp3; 2732068SN/A Bitfield<9, 8> cp4; 2742068SN/A Bitfield<11, 10> cp5; 2752068SN/A Bitfield<13, 12> cp6; 2762068SN/A Bitfield<15, 14> cp7; 2772068SN/A Bitfield<17, 16> cp8; 2782068SN/A Bitfield<19, 18> cp9; 2792068SN/A Bitfield<21, 20> cp10; 2802068SN/A Bitfield<23, 22> cp11; 2812068SN/A Bitfield<25, 24> cp12; 2822068SN/A Bitfield<27, 26> cp13; 2832068SN/A Bitfield<30> d32dis; 2842068SN/A Bitfield<31> asedis; 2852068SN/A EndBitUnion(CPACR) 2862068SN/A}; 2872068SN/A 2882068SN/A#endif // __ARCH_ARM_MISCREGS_HH__ 2892068SN/A