miscregs.hh revision 7352
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42#ifndef __ARCH_ARM_MISCREGS_HH__ 43#define __ARCH_ARM_MISCREGS_HH__ 44 45#include "base/bitunion.hh" 46 47namespace ArmISA 48{ 49 enum ConditionCode { 50 COND_EQ = 0, 51 COND_NE, // 1 52 COND_CS, // 2 53 COND_CC, // 3 54 COND_MI, // 4 55 COND_PL, // 5 56 COND_VS, // 6 57 COND_VC, // 7 58 COND_HI, // 8 59 COND_LS, // 9 60 COND_GE, // 10 61 COND_LT, // 11 62 COND_GT, // 12 63 COND_LE, // 13 64 COND_AL, // 14 65 COND_UC // 15 66 }; 67 68 enum MiscRegIndex { 69 MISCREG_CPSR = 0, 70 MISCREG_SPSR, 71 MISCREG_SPSR_FIQ, 72 MISCREG_SPSR_IRQ, 73 MISCREG_SPSR_SVC, 74 MISCREG_SPSR_MON, 75 MISCREG_SPSR_UND, 76 MISCREG_SPSR_ABT, 77 MISCREG_FPSR, 78 MISCREG_FPSID, 79 MISCREG_FPSCR, 80 MISCREG_FPEXC, 81 MISCREG_MVFR0, 82 MISCREG_MVFR1, 83 MISCREG_SEV_MAILBOX, 84 85 // CP15 registers 86 MISCREG_CP15_START, 87 MISCREG_SCTLR = MISCREG_CP15_START, 88 MISCREG_DCCISW, 89 MISCREG_DCCIMVAC, 90 MISCREG_DCCMVAC, 91 MISCREG_CONTEXTIDR, 92 MISCREG_TPIDRURW, 93 MISCREG_TPIDRURO, 94 MISCREG_TPIDRPRW, 95 MISCREG_CP15ISB, 96 MISCREG_CP15DSB, 97 MISCREG_CP15DMB, 98 MISCREG_CPACR, 99 MISCREG_CLIDR, 100 MISCREG_CCSIDR, 101 MISCREG_CSSELR, 102 MISCREG_ICIALLUIS, 103 MISCREG_ICIALLU, 104 MISCREG_ICIMVAU, 105 MISCREG_BPIMVA, 106 MISCREG_BPIALLIS, 107 MISCREG_BPIALL, 108 MISCREG_MIDR, 109 MISCREG_TTBR0, 110 MISCREG_TTBR1, 111 MISCREG_CP15_UNIMP_START, 112 MISCREG_CTR = MISCREG_CP15_UNIMP_START, 113 MISCREG_TLBTR, 114 MISCREG_TCMTR, 115 MISCREG_MPIDR, 116 MISCREG_ID_PFR0, 117 MISCREG_ID_PFR1, 118 MISCREG_ID_DFR0, 119 MISCREG_ID_AFR0, 120 MISCREG_ID_MMFR0, 121 MISCREG_ID_MMFR1, 122 MISCREG_ID_MMFR2, 123 MISCREG_ID_MMFR3, 124 MISCREG_ID_ISAR0, 125 MISCREG_ID_ISAR1, 126 MISCREG_ID_ISAR2, 127 MISCREG_ID_ISAR3, 128 MISCREG_ID_ISAR4, 129 MISCREG_ID_ISAR5, 130 MISCREG_PAR, 131 MISCREG_AIDR, 132 MISCREG_ACTLR, 133 MISCREG_DACR, 134 MISCREG_DFSR, 135 MISCREG_IFSR, 136 MISCREG_ADFSR, 137 MISCREG_AIFSR, 138 MISCREG_DFAR, 139 MISCREG_IFAR, 140 MISCREG_DCIMVAC, 141 MISCREG_DCISW, 142 MISCREG_MCCSW, 143 MISCREG_DCCMVAU, 144 MISCREG_SCR, 145 MISCREG_SDER, 146 MISCREG_NSACR, 147 MISCREG_TTBCR, 148 MISCREG_V2PCWPR, 149 MISCREG_V2PCWPW, 150 MISCREG_V2PCWUR, 151 MISCREG_V2PCWUW, 152 MISCREG_V2POWPR, 153 MISCREG_V2POWPW, 154 MISCREG_V2POWUR, 155 MISCREG_V2POWUW, 156 MISCREG_TLBIALLIS, 157 MISCREG_TLBIMVAIS, 158 MISCREG_TLBIASIDIS, 159 MISCREG_TLBIMVAAIS, 160 MISCREG_ITLBIALL, 161 MISCREG_ITLBIMVA, 162 MISCREG_ITLBIASID, 163 MISCREG_DTLBIALL, 164 MISCREG_DTLBIMVA, 165 MISCREG_DTLBIASID, 166 MISCREG_TLBIALL, 167 MISCREG_TLBIMVA, 168 MISCREG_TLBIASID, 169 MISCREG_TLBIMVAA, 170 MISCREG_PRRR, 171 MISCREG_NMRR, 172 MISCREG_VBAR, 173 MISCREG_MVBAR, 174 MISCREG_ISR, 175 MISCREG_FCEIDR, 176 177 178 MISCREG_CP15_END, 179 180 // Dummy indices 181 MISCREG_NOP = MISCREG_CP15_END, 182 MISCREG_RAZ, 183 184 NUM_MISCREGS 185 }; 186 187 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 188 unsigned crm, unsigned opc2); 189 190 const char * const miscRegName[NUM_MISCREGS] = { 191 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", 192 "spsr_mon", "spsr_und", "spsr_abt", 193 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1", 194 "sev_mailbox", 195 "sctlr", "dccisw", "dccimvac", "dccmvac", 196 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 197 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 198 "clidr", "ccsidr", "csselr", 199 "icialluis", "iciallu", "icimvau", 200 "bpimva", "bpiallis", "bpiall", 201 "midr", "ttbr0", "ttbr1", "ctr", "tlbtr", "tcmtr", "mpidr", 202 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", 203 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", 204 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", 205 "par", "aidr", "actlr", "dacr", 206 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", 207 "dcimvac", "dcisw", "mccsw", 208 "dccmvau", 209 "scr", "sder", "nsacr", "ttbcr", 210 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", 211 "v2powpr", "v2powpw", "v2powur", "v2powuw", 212 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais", 213 "itlbiall", "itlbimva", "itlbiasid", 214 "dtlbiall", "dtlbimva", "dtlbiasid", 215 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", 216 "prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr", 217 "nop", "raz" 218 }; 219 220 BitUnion32(CPSR) 221 Bitfield<31> n; 222 Bitfield<30> z; 223 Bitfield<29> c; 224 Bitfield<28> v; 225 Bitfield<27> q; 226 Bitfield<26,25> it1; 227 Bitfield<24> j; 228 Bitfield<19, 16> ge; 229 Bitfield<15,10> it2; 230 Bitfield<9> e; 231 Bitfield<8> a; 232 Bitfield<7> i; 233 Bitfield<6> f; 234 Bitfield<5> t; 235 Bitfield<4, 0> mode; 236 EndBitUnion(CPSR) 237 238 // This mask selects bits of the CPSR that actually go in the CondCodes 239 // integer register to allow renaming. 240 static const uint32_t CondCodesMask = 0xF80F0000; 241 242 BitUnion32(SCTLR) 243 Bitfield<30> te; // Thumb Exception Enable 244 Bitfield<29> afe; // Access flag enable 245 Bitfield<28> tre; // TEX Remap bit 246 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 247 Bitfield<25> ee; // Exception Endianness bit 248 Bitfield<24> ve; // Interrupt vectors enable 249 Bitfield<23> rao1;// Read as one 250 Bitfield<22> u; // Alignment (now unused) 251 Bitfield<21> fi; // Fast interrupts configuration enable 252 Bitfield<18> rao2;// Read as one 253 Bitfield<17> ha; // Hardware access flag enable 254 Bitfield<16> rao3;// Read as one 255 Bitfield<14> rr; // Round robin cache replacement 256 Bitfield<13> v; // Base address for exception vectors 257 Bitfield<12> i; // instruction cache enable 258 Bitfield<11> z; // branch prediction enable bit 259 Bitfield<10> sw; // Enable swp/swpb 260 Bitfield<6,3> rao4;// Read as one 261 Bitfield<7> b; // Endianness support (unused) 262 Bitfield<2> c; // Cache enable bit 263 Bitfield<1> a; // Alignment fault checking 264 Bitfield<0> m; // MMU enable bit 265 EndBitUnion(SCTLR) 266 267 BitUnion32(CPACR) 268 Bitfield<1, 0> cp0; 269 Bitfield<3, 2> cp1; 270 Bitfield<5, 4> cp2; 271 Bitfield<7, 6> cp3; 272 Bitfield<9, 8> cp4; 273 Bitfield<11, 10> cp5; 274 Bitfield<13, 12> cp6; 275 Bitfield<15, 14> cp7; 276 Bitfield<17, 16> cp8; 277 Bitfield<19, 18> cp9; 278 Bitfield<21, 20> cp10; 279 Bitfield<23, 22> cp11; 280 Bitfield<25, 24> cp12; 281 Bitfield<27, 26> cp13; 282 Bitfield<30> d32dis; 283 Bitfield<31> asedis; 284 EndBitUnion(CPACR) 285}; 286 287#endif // __ARCH_ARM_MISCREGS_HH__ 288