miscregs.hh revision 7350:41e3ee23125e 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49    enum ConditionCode {
50        COND_EQ  =   0,
51        COND_NE, //  1
52        COND_CS, //  2
53        COND_CC, //  3
54        COND_MI, //  4
55        COND_PL, //  5
56        COND_VS, //  6
57        COND_VC, //  7
58        COND_HI, //  8
59        COND_LS, //  9
60        COND_GE, // 10
61        COND_LT, // 11
62        COND_GT, // 12
63        COND_LE, // 13
64        COND_AL, // 14
65        COND_UC  // 15
66    };
67
68    enum MiscRegIndex {
69        MISCREG_CPSR = 0,
70        MISCREG_SPSR,
71        MISCREG_SPSR_FIQ,
72        MISCREG_SPSR_IRQ,
73        MISCREG_SPSR_SVC,
74        MISCREG_SPSR_MON,
75        MISCREG_SPSR_UND,
76        MISCREG_SPSR_ABT,
77        MISCREG_FPSR,
78        MISCREG_FPSID,
79        MISCREG_FPSCR,
80        MISCREG_FPEXC,
81        MISCREG_MVFR0,
82        MISCREG_MVFR1,
83        MISCREG_SEV_MAILBOX,
84
85        // CP15 registers
86        MISCREG_CP15_START,
87        MISCREG_SCTLR = MISCREG_CP15_START,
88        MISCREG_DCCISW,
89        MISCREG_DCCIMVAC,
90        MISCREG_DCCMVAC,
91        MISCREG_CONTEXTIDR,
92        MISCREG_TPIDRURW,
93        MISCREG_TPIDRURO,
94        MISCREG_TPIDRPRW,
95        MISCREG_CP15ISB,
96        MISCREG_CP15DSB,
97        MISCREG_CP15DMB,
98        MISCREG_CPACR,
99        MISCREG_CLIDR,
100        MISCREG_CCSIDR,
101        MISCREG_CSSELR,
102        MISCREG_ICIALLUIS,
103        MISCREG_ICIALLU,
104        MISCREG_ICIMVAU,
105        MISCREG_BPIMVA,
106        MISCREG_BPIALLIS,
107        MISCREG_BPIALL,
108        MISCREG_MPUIR,
109        MISCREG_MIDR,
110        MISCREG_RGNR,
111        MISCREG_DRBAR,
112        MISCREG_DRACR,
113        MISCREG_DRSR,
114        MISCREG_CP15_UNIMP_START,
115        MISCREG_CTR = MISCREG_CP15_UNIMP_START,
116        MISCREG_TCMTR,
117        MISCREG_MPIDR,
118        MISCREG_ID_PFR0,
119        MISCREG_ID_PFR1,
120        MISCREG_ID_DFR0,
121        MISCREG_ID_AFR0,
122        MISCREG_ID_MMFR0,
123        MISCREG_ID_MMFR1,
124        MISCREG_ID_MMFR2,
125        MISCREG_ID_MMFR3,
126        MISCREG_ID_ISAR0,
127        MISCREG_ID_ISAR1,
128        MISCREG_ID_ISAR2,
129        MISCREG_ID_ISAR3,
130        MISCREG_ID_ISAR4,
131        MISCREG_ID_ISAR5,
132        MISCREG_AIDR,
133        MISCREG_ACTLR,
134        MISCREG_DFSR,
135        MISCREG_IFSR,
136        MISCREG_ADFSR,
137        MISCREG_AIFSR,
138        MISCREG_DFAR,
139        MISCREG_IFAR,
140        MISCREG_IRBAR,
141        MISCREG_IRSR,
142        MISCREG_IRACR,
143        MISCREG_DCIMVAC,
144        MISCREG_DCISW,
145        MISCREG_MCCSW,
146        MISCREG_DCCMVAU,
147
148        MISCREG_CP15_END,
149
150        // Dummy indices
151        MISCREG_NOP = MISCREG_CP15_END,
152        MISCREG_RAZ,
153
154        NUM_MISCREGS
155    };
156
157    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
158                               unsigned crm, unsigned opc2);
159
160    const char * const miscRegName[NUM_MISCREGS] = {
161        "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
162        "spsr_mon", "spsr_und", "spsr_abt",
163        "fpsr", "fpsid", "fpscr", "fpexc", "sev_mailbox",
164        "sctlr", "dccisw", "dccimvac", "dccmvac",
165        "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
166        "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
167        "clidr", "ccsidr", "csselr",
168        "icialluis", "iciallu", "icimvau",
169        "bpimva", "bpiallis", "bpiall",
170        "mpuir", "midr", "rgnr", "drbar", "dracr", "drsr",
171        "ctr", "tcmtr", "mpidr",
172        "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
173        "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
174        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
175        "aidr", "actlr",
176        "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
177        "irbar", "irsr", "iracr",
178        "dcimvac", "dcisw", "mccsw",
179        "dccmvau",
180        "nop", "raz"
181    };
182
183    BitUnion32(CPSR)
184        Bitfield<31> n;
185        Bitfield<30> z;
186        Bitfield<29> c;
187        Bitfield<28> v;
188        Bitfield<27> q;
189        Bitfield<26,25> it1;
190        Bitfield<24> j;
191        Bitfield<19, 16> ge;
192        Bitfield<15,10> it2;
193        Bitfield<9> e;
194        Bitfield<8> a;
195        Bitfield<7> i;
196        Bitfield<6> f;
197        Bitfield<5> t;
198        Bitfield<4, 0> mode;
199    EndBitUnion(CPSR)
200
201    // This mask selects bits of the CPSR that actually go in the CondCodes
202    // integer register to allow renaming.
203    static const uint32_t CondCodesMask = 0xF80F0000;
204
205    BitUnion32(SCTLR)
206        Bitfield<30> te;  // Thumb Exception Enable
207        Bitfield<29> afe; // Access flag enable
208        Bitfield<28> tre; // TEX Remap bit
209        Bitfield<27> nmfi;// Non-maskable fast interrupts enable
210        Bitfield<25> ee;  // Exception Endianness bit
211        Bitfield<24> ve;  // Interrupt vectors enable
212        Bitfield<23> rao1;// Read as one
213        Bitfield<22> u;   // Alignment (now unused)
214        Bitfield<21> fi;  // Fast interrupts configuration enable
215        Bitfield<18> rao2;// Read as one
216        Bitfield<17> ha;  // Hardware access flag enable
217        Bitfield<16> rao3;// Read as one
218        Bitfield<14> rr;  // Round robin cache replacement
219        Bitfield<13> v;   // Base address for exception vectors
220        Bitfield<12> i;   // instruction cache enable
221        Bitfield<11> z;   // branch prediction enable bit
222        Bitfield<10> sw;  // Enable swp/swpb
223        Bitfield<6,3> rao4;// Read as one
224        Bitfield<7>  b;   // Endianness support (unused)
225        Bitfield<2>  c;   // Cache enable bit
226        Bitfield<1>  a;   // Alignment fault checking
227        Bitfield<0>  m;   // MMU enable bit
228    EndBitUnion(SCTLR)
229
230    BitUnion32(CPACR)
231        Bitfield<1, 0> cp0;
232        Bitfield<3, 2> cp1;
233        Bitfield<5, 4> cp2;
234        Bitfield<7, 6> cp3;
235        Bitfield<9, 8> cp4;
236        Bitfield<11, 10> cp5;
237        Bitfield<13, 12> cp6;
238        Bitfield<15, 14> cp7;
239        Bitfield<17, 16> cp8;
240        Bitfield<19, 18> cp9;
241        Bitfield<21, 20> cp10;
242        Bitfield<23, 22> cp11;
243        Bitfield<25, 24> cp12;
244        Bitfield<27, 26> cp13;
245        Bitfield<30> d32dis;
246        Bitfield<31> asedis;
247    EndBitUnion(CPACR)
248};
249
250#endif // __ARCH_ARM_MISCREGS_HH__
251