miscregs.hh revision 6750
1955SN/A/* 2955SN/A * Copyright (c) 2009 The Regents of The University of Michigan 31762SN/A * All rights reserved. 4955SN/A * 5955SN/A * Redistribution and use in source and binary forms, with or without 6955SN/A * modification, are permitted provided that the following conditions are 7955SN/A * met: redistributions of source code must retain the above copyright 8955SN/A * notice, this list of conditions and the following disclaimer; 9955SN/A * redistributions in binary form must reproduce the above copyright 10955SN/A * notice, this list of conditions and the following disclaimer in the 11955SN/A * documentation and/or other materials provided with the distribution; 12955SN/A * neither the name of the copyright holders nor the names of its 13955SN/A * contributors may be used to endorse or promote products derived from 14955SN/A * this software without specific prior written permission. 15955SN/A * 16955SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17955SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 294762Snate@binkert.org */ 30955SN/A#ifndef __ARCH_ARM_MISCREGS_HH__ 314762Snate@binkert.org#define __ARCH_ARM_MISCREGS_HH__ 32955SN/A 33955SN/A#include "base/bitunion.hh" 344202Sbinkertn@umich.edu 354382Sbinkertn@umich.edunamespace ArmISA 364202Sbinkertn@umich.edu{ 374762Snate@binkert.org enum ConditionCode { 384762Snate@binkert.org COND_EQ = 0, 394762Snate@binkert.org COND_NE, // 1 40955SN/A COND_CS, // 2 414381Sbinkertn@umich.edu COND_CC, // 3 424381Sbinkertn@umich.edu COND_MI, // 4 43955SN/A COND_PL, // 5 44955SN/A COND_VS, // 6 45955SN/A COND_VC, // 7 464202Sbinkertn@umich.edu COND_HI, // 8 47955SN/A COND_LS, // 9 484382Sbinkertn@umich.edu COND_GE, // 10 494382Sbinkertn@umich.edu COND_LT, // 11 504382Sbinkertn@umich.edu COND_GT, // 12 514762Snate@binkert.org COND_LE, // 13 524762Snate@binkert.org COND_AL, // 14 534762Snate@binkert.org COND_NV // 15 544762Snate@binkert.org }; 554762Snate@binkert.org 564762Snate@binkert.org enum MiscRegIndex { 574762Snate@binkert.org MISCREG_CPSR = 0, 584762Snate@binkert.org MISCREG_SPSR, 594762Snate@binkert.org MISCREG_SPSR_FIQ, 604762Snate@binkert.org MISCREG_SPSR_IRQ, 614762Snate@binkert.org MISCREG_SPSR_SVC, 624762Snate@binkert.org MISCREG_SPSR_MON, 634762Snate@binkert.org MISCREG_SPSR_UND, 644762Snate@binkert.org MISCREG_SPSR_ABT, 654762Snate@binkert.org MISCREG_FPSR, 664762Snate@binkert.org MISCREG_FPSID, 674762Snate@binkert.org MISCREG_FPSCR, 684762Snate@binkert.org MISCREG_FPEXC, 694762Snate@binkert.org MISCREG_SCTLR, 704762Snate@binkert.org NUM_MISCREGS 714762Snate@binkert.org }; 724762Snate@binkert.org 734762Snate@binkert.org const char * const miscRegName[NUM_MISCREGS] = { 744762Snate@binkert.org "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", 754762Snate@binkert.org "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr" 764762Snate@binkert.org }; 774762Snate@binkert.org 784762Snate@binkert.org BitUnion32(CPSR) 794762Snate@binkert.org Bitfield<31> n; 804762Snate@binkert.org Bitfield<30> z; 814762Snate@binkert.org Bitfield<29> c; 824762Snate@binkert.org Bitfield<28> v; 834762Snate@binkert.org Bitfield<27> q; 844382Sbinkertn@umich.edu Bitfield<26,25> it1; 854762Snate@binkert.org Bitfield<24> j; 864382Sbinkertn@umich.edu Bitfield<19, 16> ge; 874762Snate@binkert.org Bitfield<15,10> it2; 884381Sbinkertn@umich.edu Bitfield<9> e; 894762Snate@binkert.org Bitfield<8> a; 904762Snate@binkert.org Bitfield<7> i; 914762Snate@binkert.org Bitfield<6> f; 924762Snate@binkert.org Bitfield<5> t; 934762Snate@binkert.org Bitfield<4, 0> mode; 944762Snate@binkert.org EndBitUnion(CPSR) 954762Snate@binkert.org 964762Snate@binkert.org // This mask selects bits of the CPSR that actually go in the CondCodes 974762Snate@binkert.org // integer register to allow renaming. 984762Snate@binkert.org static const uint32_t CondCodesMask = 0xF80F0000; 994762Snate@binkert.org 1004762Snate@binkert.org BitUnion32(SCTLR) 1014762Snate@binkert.org Bitfield<30> te; // Thumb Exception Enable 1024762Snate@binkert.org Bitfield<29> afe; // Access flag enable 1034762Snate@binkert.org Bitfield<28> tre; // TEX Remap bit 1044762Snate@binkert.org Bitfield<27> nmfi;// Non-maskable fast interrupts enable 1054762Snate@binkert.org Bitfield<25> ee; // Exception Endianness bit 1064762Snate@binkert.org Bitfield<24> ve; // Interrupt vectors enable 1074762Snate@binkert.org Bitfield<23> rao1;// Read as one 1084762Snate@binkert.org Bitfield<22> u; // Alignment (now unused) 1094762Snate@binkert.org Bitfield<21> fi; // Fast interrupts configuration enable 1104762Snate@binkert.org Bitfield<18> rao2;// Read as one 1114762Snate@binkert.org Bitfield<17> ha; // Hardware access flag enable 1124762Snate@binkert.org Bitfield<16> rao3;// Read as one 1134762Snate@binkert.org Bitfield<14> rr; // Round robin cache replacement 1144762Snate@binkert.org Bitfield<13> v; // Base address for exception vectors 1154762Snate@binkert.org Bitfield<12> i; // instruction cache enable 1164762Snate@binkert.org Bitfield<11> z; // branch prediction enable bit 1174762Snate@binkert.org Bitfield<10> sw; // Enable swp/swpb 1184762Snate@binkert.org Bitfield<6,3> rao4;// Read as one 1194762Snate@binkert.org Bitfield<7> b; // Endianness support (unused) 1204762Snate@binkert.org Bitfield<2> c; // Cache enable bit 1214762Snate@binkert.org Bitfield<1> a; // Alignment fault checking 1224762Snate@binkert.org Bitfield<0> m; // MMU enable bit 1234762Snate@binkert.org EndBitUnion(SCTLR) 1244762Snate@binkert.org}; 1254762Snate@binkert.org 1264762Snate@binkert.org#endif // __ARCH_ARM_MISCREGS_HH__ 1274762Snate@binkert.org