miscregs.hh revision 6735:6437ad24a8a0 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30#ifndef __ARCH_ARM_MISCREGS_HH__
31#define __ARCH_ARM_MISCREGS_HH__
32
33#include "base/bitunion.hh"
34
35namespace ArmISA
36{
37    enum ConditionCode {
38        COND_EQ  =   0,
39        COND_NE, //  1
40        COND_CS, //  2
41        COND_CC, //  3
42        COND_MI, //  4
43        COND_PL, //  5
44        COND_VS, //  6
45        COND_VC, //  7
46        COND_HI, //  8
47        COND_LS, //  9
48        COND_GE, // 10
49        COND_LT, // 11
50        COND_GT, // 12
51        COND_LE, // 13
52        COND_AL, // 14
53        COND_NV  // 15
54    };
55
56    enum MiscRegIndex {
57        MISCREG_CPSR = 0,
58        MISCREG_SPSR,
59        MISCREG_SPSR_FIQ,
60        MISCREG_SPSR_IRQ,
61        MISCREG_SPSR_SVC,
62        MISCREG_SPSR_MON,
63        MISCREG_SPSR_UND,
64        MISCREG_SPSR_ABT,
65        MISCREG_FPSR,
66        MISCREG_FPSID,
67        MISCREG_FPSCR,
68        MISCREG_FPEXC,
69        MISCREG_SCTLR,
70        NUM_MISCREGS
71    };
72
73    const char * const miscRegName[NUM_MISCREGS] = {
74        "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
75        "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
76    };
77
78    BitUnion32(CPSR)
79        Bitfield<31> n;
80        Bitfield<30> z;
81        Bitfield<29> c;
82        Bitfield<28> v;
83        Bitfield<27> q;
84        Bitfield<26,25> it1;
85        Bitfield<24> j;
86        Bitfield<19, 16> ge;
87        Bitfield<15,10> it2;
88        Bitfield<9> e;
89        Bitfield<8> a;
90        Bitfield<7> i;
91        Bitfield<6> f;
92        Bitfield<5> t;
93        Bitfield<4, 0> mode;
94    EndBitUnion(CPSR)
95
96    BitUnion32(SCTLR)
97        Bitfield<30> te;  // Thumb Exception Enable
98        Bitfield<29> afe; // Access flag enable
99        Bitfield<28> tre; // TEX Remap bit
100        Bitfield<27> nmfi;// Non-maskable fast interrupts enable
101        Bitfield<25> ee;  // Exception Endianness bit
102        Bitfield<24> ve;  // Interrupt vectors enable
103        Bitfield<23> rao1;// Read as one
104        Bitfield<22> u;   // Alignment (now unused)
105        Bitfield<21> fi;  // Fast interrupts configuration enable
106        Bitfield<18> rao2;// Read as one
107        Bitfield<17> ha;  // Hardware access flag enable
108        Bitfield<16> rao3;// Read as one
109        Bitfield<14> rr;  // Round robin cache replacement
110        Bitfield<13> v;   // Base address for exception vectors
111        Bitfield<12> i;   // instruction cache enable
112        Bitfield<11> z;   // branch prediction enable bit
113        Bitfield<10> sw;  // Enable swp/swpb
114        Bitfield<6,3> rao4;// Read as one
115        Bitfield<7>  b;   // Endianness support (unused)
116        Bitfield<2>  c;   // Cache enable bit
117        Bitfield<1>  a;   // Alignment fault checking
118        Bitfield<0>  m;   // MMU enable bit
119    EndBitUnion(SCTLR)
120};
121
122#endif // __ARCH_ARM_MISCREGS_HH__
123