miscregs.hh revision 6242:1cee707c1228 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30#ifndef __ARCH_ARM_MISCREGS_HH__
31#define __ARCH_ARM_MISCREGS_HH__
32
33#include "base/bitunion.hh"
34
35namespace ArmISA
36{
37    enum ConditionCode {
38        COND_EQ  =   0,
39        COND_NE, //  1
40        COND_CS, //  2
41        COND_CC, //  3
42        COND_MI, //  4
43        COND_PL, //  5
44        COND_VS, //  6
45        COND_VC, //  7
46        COND_HI, //  8
47        COND_LS, //  9
48        COND_GE, // 10
49        COND_LT, // 11
50        COND_GT, // 12
51        COND_LE, // 13
52        COND_AL, // 14
53        COND_NV  // 15
54    };
55
56    enum MiscRegIndex {
57        MISCREG_CPSR = 0,
58        MISCREG_SPSR_FIQ,
59        MISCREG_SPSR_IRQ,
60        MISCREG_SPSR_SVC,
61        MISCREG_SPSR_UND,
62        MISCREG_SPSR_ABT,
63        MISCREG_FPSR
64    };
65
66    BitUnion32(CPSR)
67        Bitfield<31> n;
68        Bitfield<30> z;
69        Bitfield<29> c;
70        Bitfield<28> v;
71        Bitfield<27> q;
72        Bitfield<24> j;
73        Bitfield<19, 16> ge;
74        Bitfield<9> e;
75        Bitfield<8> a;
76        Bitfield<7> i;
77        Bitfield<6> f;
78        Bitfield<5> t;
79        Bitfield<4, 0> mode;
80    EndBitUnion(CPSR)
81};
82
83#endif // __ARCH_ARM_MISCREGS_HH__
84