miscregs.cc revision 9959:ad4564da49b5 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/miscregs.hh"
43#include "base/misc.hh"
44
45namespace ArmISA
46{
47
48MiscRegIndex
49decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
50{
51    switch(crn) {
52      case 0:
53        switch (opc2) {
54          case 0:
55            switch (crm) {
56              case 0:
57                return MISCREG_DBGDIDR;
58              case 1:
59                return MISCREG_DBGDSCR_INT;
60              default:
61                warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
62                     crn, opc1, crm, opc2);
63                return NUM_MISCREGS;
64            }
65          default:
66            warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
67                 crn, opc1, crm, opc2);
68            return NUM_MISCREGS;
69        }
70      case 1:
71        switch (opc1) {
72          case 6:
73            switch (crm) {
74              case 0:
75                switch (opc2) {
76                  case 0:
77                    return MISCREG_TEEHBR;
78                  default:
79                    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
80                         crn, opc1, crm, opc2);
81                    return NUM_MISCREGS;
82                }
83              default:
84                warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
85                     crn, opc1, crm, opc2);
86                return NUM_MISCREGS;
87            }
88          default:
89            warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
90                 crn, opc1, crm, opc2);
91            return NUM_MISCREGS;
92        }
93      default:
94        warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
95             crn, opc1, crm, opc2);
96        return NUM_MISCREGS;
97    }
98
99}
100
101MiscRegIndex
102decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
103{
104    switch (crn) {
105      case 0:
106        switch (opc1) {
107          case 0:
108            switch (crm) {
109              case 0:
110                switch (opc2) {
111                  case 1:
112                    return MISCREG_CTR;
113                  case 2:
114                    return MISCREG_TCMTR;
115                  case 3:
116                    return MISCREG_TLBTR;
117                  case 5:
118                    return MISCREG_MPIDR;
119                  default:
120                    return MISCREG_MIDR;
121                }
122                break;
123              case 1:
124                switch (opc2) {
125                  case 0:
126                    return MISCREG_ID_PFR0;
127                  case 1:
128                    return MISCREG_ID_PFR1;
129                  case 2:
130                    return MISCREG_ID_DFR0;
131                  case 3:
132                    return MISCREG_ID_AFR0;
133                  case 4:
134                    return MISCREG_ID_MMFR0;
135                  case 5:
136                    return MISCREG_ID_MMFR1;
137                  case 6:
138                    return MISCREG_ID_MMFR2;
139                  case 7:
140                    return MISCREG_ID_MMFR3;
141                }
142                break;
143              case 2:
144                switch (opc2) {
145                  case 0:
146                    return MISCREG_ID_ISAR0;
147                  case 1:
148                    return MISCREG_ID_ISAR1;
149                  case 2:
150                    return MISCREG_ID_ISAR2;
151                  case 3:
152                    return MISCREG_ID_ISAR3;
153                  case 4:
154                    return MISCREG_ID_ISAR4;
155                  case 5:
156                    return MISCREG_ID_ISAR5;
157                  case 6:
158                  case 7:
159                    return MISCREG_RAZ; // read as zero
160                }
161                break;
162              default:
163                return MISCREG_RAZ; // read as zero
164            }
165            break;
166          case 1:
167            if (crm == 0) {
168                switch (opc2) {
169                  case 0:
170                    return MISCREG_CCSIDR;
171                  case 1:
172                    return MISCREG_CLIDR;
173                  case 7:
174                    return MISCREG_AIDR;
175                }
176            }
177            break;
178          case 2:
179            if (crm == 0 && opc2 == 0) {
180                return MISCREG_CSSELR;
181            }
182            break;
183        }
184        break;
185      case 1:
186        if (opc1 == 0) {
187            if (crm == 0) {
188                switch (opc2) {
189                  case 0:
190                    return MISCREG_SCTLR;
191                  case 1:
192                    return MISCREG_ACTLR;
193                  case 0x2:
194                    return MISCREG_CPACR;
195                }
196            } else if (crm == 1) {
197                switch (opc2) {
198                  case 0:
199                    return MISCREG_SCR;
200                  case 1:
201                    return MISCREG_SDER;
202                  case 2:
203                    return MISCREG_NSACR;
204                }
205            }
206        }
207        break;
208      case 2:
209        if (opc1 == 0 && crm == 0) {
210            switch (opc2) {
211              case 0:
212                return MISCREG_TTBR0;
213              case 1:
214                return MISCREG_TTBR1;
215              case 2:
216                return MISCREG_TTBCR;
217            }
218        }
219        break;
220      case 3:
221        if (opc1 == 0 && crm == 0 && opc2 == 0) {
222            return MISCREG_DACR;
223        }
224        break;
225      case 5:
226        if (opc1 == 0) {
227            if (crm == 0) {
228                if (opc2 == 0) {
229                    return MISCREG_DFSR;
230                } else if (opc2 == 1) {
231                    return MISCREG_IFSR;
232                }
233            } else if (crm == 1) {
234                if (opc2 == 0) {
235                    return MISCREG_ADFSR;
236                } else if (opc2 == 1) {
237                    return MISCREG_AIFSR;
238                }
239            }
240        }
241        break;
242      case 6:
243        if (opc1 == 0 && crm == 0) {
244            switch (opc2) {
245              case 0:
246                return MISCREG_DFAR;
247              case 2:
248                return MISCREG_IFAR;
249            }
250        }
251        break;
252      case 7:
253        if (opc1 == 0) {
254            switch (crm) {
255              case 0:
256                if (opc2 == 4) {
257                    return MISCREG_NOP;
258                }
259                break;
260              case 1:
261                switch (opc2) {
262                  case 0:
263                    return MISCREG_ICIALLUIS;
264                  case 6:
265                    return MISCREG_BPIALLIS;
266                }
267                break;
268              case 4:
269                if (opc2 == 0) {
270                    return MISCREG_PAR;
271                }
272                break;
273              case 5:
274                switch (opc2) {
275                  case 0:
276                    return MISCREG_ICIALLU;
277                  case 1:
278                    return MISCREG_ICIMVAU;
279                  case 4:
280                    return MISCREG_CP15ISB;
281                  case 6:
282                    return MISCREG_BPIALL;
283                  case 7:
284                    return MISCREG_BPIMVA;
285                }
286                break;
287              case 6:
288                if (opc2 == 1) {
289                    return MISCREG_DCIMVAC;
290                } else if (opc2 == 2) {
291                    return MISCREG_DCISW;
292                }
293                break;
294              case 8:
295                switch (opc2) {
296                  case 0:
297                    return MISCREG_V2PCWPR;
298                  case 1:
299                    return MISCREG_V2PCWPW;
300                  case 2:
301                    return MISCREG_V2PCWUR;
302                  case 3:
303                    return MISCREG_V2PCWUW;
304                  case 4:
305                    return MISCREG_V2POWPR;
306                  case 5:
307                    return MISCREG_V2POWPW;
308                  case 6:
309                    return MISCREG_V2POWUR;
310                  case 7:
311                    return MISCREG_V2POWUW;
312                }
313                break;
314              case 10:
315                switch (opc2) {
316                  case 1:
317                    return MISCREG_DCCMVAC;
318                  case 2:
319                    return MISCREG_MCCSW;
320                  case 4:
321                    return MISCREG_CP15DSB;
322                  case 5:
323                    return MISCREG_CP15DMB;
324                }
325                break;
326              case 11:
327                if (opc2 == 1) {
328                    return MISCREG_DCCMVAU;
329                }
330                break;
331              case 13:
332                if (opc2 == 1) {
333                    return MISCREG_NOP;
334                }
335                break;
336              case 14:
337                if (opc2 == 1) {
338                    return MISCREG_DCCIMVAC;
339                } else if (opc2 == 2) {
340                    return MISCREG_DCCISW;
341                }
342                break;
343            }
344        }
345        break;
346      case 8:
347        if (opc1 == 0) {
348            switch (crm) {
349              case 3:
350                switch (opc2) {
351                  case 0:
352                    return MISCREG_TLBIALLIS;
353                  case 1:
354                    return MISCREG_TLBIMVAIS;
355                  case 2:
356                    return MISCREG_TLBIASIDIS;
357                  case 3:
358                    return MISCREG_TLBIMVAAIS;
359                }
360                break;
361              case 5:
362                switch (opc2) {
363                  case 0:
364                    return MISCREG_ITLBIALL;
365                  case 1:
366                    return MISCREG_ITLBIMVA;
367                  case 2:
368                    return MISCREG_ITLBIASID;
369                }
370                break;
371              case 6:
372                switch (opc2) {
373                  case 0:
374                    return MISCREG_DTLBIALL;
375                  case 1:
376                    return MISCREG_DTLBIMVA;
377                  case 2:
378                    return MISCREG_DTLBIASID;
379                }
380                break;
381              case 7:
382                switch (opc2) {
383                  case 0:
384                    return MISCREG_TLBIALL;
385                  case 1:
386                    return MISCREG_TLBIMVA;
387                  case 2:
388                    return MISCREG_TLBIASID;
389                  case 3:
390                    return MISCREG_TLBIMVAA;
391                }
392                break;
393            }
394        }
395        break;
396      case 9:
397        if (opc1 == 0) {
398            switch (crm) {
399              case 12:
400                switch (opc2) {
401                  case 0:
402                    return MISCREG_PMCR;
403                  case 1:
404                    return MISCREG_PMCNTENSET;
405                  case 2:
406                    return MISCREG_PMCNTENCLR;
407                  case 3:
408                    return MISCREG_PMOVSR;
409                  case 4:
410                    return MISCREG_PMSWINC;
411                  case 5:
412                    return MISCREG_PMSELR;
413                  case 6:
414                    return MISCREG_PMCEID0;
415                  case 7:
416                    return MISCREG_PMCEID1;
417                }
418                break;
419              case 13:
420                switch (opc2) {
421                  case 0:
422                    return MISCREG_PMCCNTR;
423                  case 1:
424                    return MISCREG_PMC_OTHER;
425                  case 2:
426                    return MISCREG_PMXEVCNTR;
427                }
428                break;
429              case 14:
430                switch (opc2) {
431                  case 0:
432                    return MISCREG_PMUSERENR;
433                  case 1:
434                    return MISCREG_PMINTENSET;
435                  case 2:
436                    return MISCREG_PMINTENCLR;
437                }
438                break;
439            }
440        } else if (opc1 == 1) {
441            switch (crm) {
442              case 0:
443                switch (opc2) {
444                  case 2: // L2CTLR, L2 Control Register
445                    return MISCREG_L2CTLR;
446                  default:
447                    warn("Uknown miscregs: crn:%d crm:%d opc1:%d opc2:%d\n",
448                         crn,crm, opc1,opc2);
449                    break;
450                }
451                break;
452              default:
453                return MISCREG_L2LATENCY;
454            }
455        }
456        //Reserved for Branch Predictor, Cache and TCM operations
457        break;
458      case 10:
459        if (opc1 == 0) {
460            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
461            if (crm == 2) { // TEX Remap Registers
462                if (opc2 == 0) {
463                    return MISCREG_PRRR;
464                } else if (opc2 == 1) {
465                    return MISCREG_NMRR;
466                }
467            }
468        }
469        break;
470      case 11:
471        if (opc1 <=7) {
472            switch (crm) {
473              case 0:
474              case 1:
475              case 2:
476              case 3:
477              case 4:
478              case 5:
479              case 6:
480              case 7:
481              case 8:
482              case 15:
483                // Reserved for DMA operations for TCM access
484                break;
485            }
486        }
487        break;
488      case 12:
489        if (opc1 == 0) {
490            if (crm == 0) {
491                if (opc2 == 0) {
492                    return MISCREG_VBAR;
493                } else if (opc2 == 1) {
494                    return MISCREG_MVBAR;
495                }
496            } else if (crm == 1) {
497                if (opc2 == 0) {
498                    return MISCREG_ISR;
499                }
500            }
501        }
502        break;
503      case 13:
504        if (opc1 == 0) {
505            if (crm == 0) {
506                switch (opc2) {
507                  case 0:
508                    return MISCREG_FCEIDR;
509                  case 1:
510                    return MISCREG_CONTEXTIDR;
511                  case 2:
512                    return MISCREG_TPIDRURW;
513                  case 3:
514                    return MISCREG_TPIDRURO;
515                  case 4:
516                    return MISCREG_TPIDRPRW;
517                }
518            }
519        }
520        break;
521      case 15:
522        // Implementation defined
523        return MISCREG_CRN15;
524    }
525    // Unrecognized register
526    return NUM_MISCREGS;
527}
528
529}
530