miscregs.cc revision 13366:c135fac88a78 
1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 *          Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57    switch(crn) {
58      case 0:
59        switch (opc1) {
60          case 0:
61            switch (opc2) {
62              case 0:
63                switch (crm) {
64                  case 0:
65                    return MISCREG_DBGDIDR;
66                  case 1:
67                    return MISCREG_DBGDSCRint;
68                }
69                break;
70            }
71            break;
72          case 7:
73            switch (opc2) {
74              case 0:
75                switch (crm) {
76                  case 0:
77                    return MISCREG_JIDR;
78                }
79              break;
80            }
81            break;
82        }
83        break;
84      case 1:
85        switch (opc1) {
86          case 6:
87            switch (crm) {
88              case 0:
89                switch (opc2) {
90                  case 0:
91                    return MISCREG_TEEHBR;
92                }
93                break;
94            }
95            break;
96          case 7:
97            switch (crm) {
98              case 0:
99                switch (opc2) {
100                  case 0:
101                    return MISCREG_JOSCR;
102                }
103                break;
104            }
105            break;
106        }
107        break;
108      case 2:
109        switch (opc1) {
110          case 7:
111            switch (crm) {
112              case 0:
113                switch (opc2) {
114                  case 0:
115                    return MISCREG_JMCR;
116                }
117                break;
118            }
119            break;
120        }
121        break;
122    }
123    // If we get here then it must be a register that we haven't implemented
124    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125         crn, opc1, crm, opc2);
126    return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134    switch (crn) {
135      case 0:
136        switch (opc1) {
137          case 0:
138            switch (crm) {
139              case 0:
140                switch (opc2) {
141                  case 1:
142                    return MISCREG_CTR;
143                  case 2:
144                    return MISCREG_TCMTR;
145                  case 3:
146                    return MISCREG_TLBTR;
147                  case 5:
148                    return MISCREG_MPIDR;
149                  case 6:
150                    return MISCREG_REVIDR;
151                  default:
152                    return MISCREG_MIDR;
153                }
154                break;
155              case 1:
156                switch (opc2) {
157                  case 0:
158                    return MISCREG_ID_PFR0;
159                  case 1:
160                    return MISCREG_ID_PFR1;
161                  case 2:
162                    return MISCREG_ID_DFR0;
163                  case 3:
164                    return MISCREG_ID_AFR0;
165                  case 4:
166                    return MISCREG_ID_MMFR0;
167                  case 5:
168                    return MISCREG_ID_MMFR1;
169                  case 6:
170                    return MISCREG_ID_MMFR2;
171                  case 7:
172                    return MISCREG_ID_MMFR3;
173                }
174                break;
175              case 2:
176                switch (opc2) {
177                  case 0:
178                    return MISCREG_ID_ISAR0;
179                  case 1:
180                    return MISCREG_ID_ISAR1;
181                  case 2:
182                    return MISCREG_ID_ISAR2;
183                  case 3:
184                    return MISCREG_ID_ISAR3;
185                  case 4:
186                    return MISCREG_ID_ISAR4;
187                  case 5:
188                    return MISCREG_ID_ISAR5;
189                  case 6:
190                  case 7:
191                    return MISCREG_RAZ; // read as zero
192                }
193                break;
194              default:
195                return MISCREG_RAZ; // read as zero
196            }
197            break;
198          case 1:
199            if (crm == 0) {
200                switch (opc2) {
201                  case 0:
202                    return MISCREG_CCSIDR;
203                  case 1:
204                    return MISCREG_CLIDR;
205                  case 7:
206                    return MISCREG_AIDR;
207                }
208            }
209            break;
210          case 2:
211            if (crm == 0 && opc2 == 0) {
212                return MISCREG_CSSELR;
213            }
214            break;
215          case 4:
216            if (crm == 0) {
217                if (opc2 == 0)
218                    return MISCREG_VPIDR;
219                else if (opc2 == 5)
220                    return MISCREG_VMPIDR;
221            }
222            break;
223        }
224        break;
225      case 1:
226        if (opc1 == 0) {
227            if (crm == 0) {
228                switch (opc2) {
229                  case 0:
230                    return MISCREG_SCTLR;
231                  case 1:
232                    return MISCREG_ACTLR;
233                  case 0x2:
234                    return MISCREG_CPACR;
235                }
236            } else if (crm == 1) {
237                switch (opc2) {
238                  case 0:
239                    return MISCREG_SCR;
240                  case 1:
241                    return MISCREG_SDER;
242                  case 2:
243                    return MISCREG_NSACR;
244                }
245            }
246        } else if (opc1 == 4) {
247            if (crm == 0) {
248                if (opc2 == 0)
249                    return MISCREG_HSCTLR;
250                else if (opc2 == 1)
251                    return MISCREG_HACTLR;
252            } else if (crm == 1) {
253                switch (opc2) {
254                  case 0:
255                    return MISCREG_HCR;
256                  case 1:
257                    return MISCREG_HDCR;
258                  case 2:
259                    return MISCREG_HCPTR;
260                  case 3:
261                    return MISCREG_HSTR;
262                  case 7:
263                    return MISCREG_HACR;
264                }
265            }
266        }
267        break;
268      case 2:
269        if (opc1 == 0 && crm == 0) {
270            switch (opc2) {
271              case 0:
272                return MISCREG_TTBR0;
273              case 1:
274                return MISCREG_TTBR1;
275              case 2:
276                return MISCREG_TTBCR;
277            }
278        } else if (opc1 == 4) {
279            if (crm == 0 && opc2 == 2)
280                return MISCREG_HTCR;
281            else if (crm == 1 && opc2 == 2)
282                return MISCREG_VTCR;
283        }
284        break;
285      case 3:
286        if (opc1 == 0 && crm == 0 && opc2 == 0) {
287            return MISCREG_DACR;
288        }
289        break;
290      case 5:
291        if (opc1 == 0) {
292            if (crm == 0) {
293                if (opc2 == 0) {
294                    return MISCREG_DFSR;
295                } else if (opc2 == 1) {
296                    return MISCREG_IFSR;
297                }
298            } else if (crm == 1) {
299                if (opc2 == 0) {
300                    return MISCREG_ADFSR;
301                } else if (opc2 == 1) {
302                    return MISCREG_AIFSR;
303                }
304            }
305        } else if (opc1 == 4) {
306            if (crm == 1) {
307                if (opc2 == 0)
308                    return MISCREG_HADFSR;
309                else if (opc2 == 1)
310                    return MISCREG_HAIFSR;
311            } else if (crm == 2 && opc2 == 0) {
312                return MISCREG_HSR;
313            }
314        }
315        break;
316      case 6:
317        if (opc1 == 0 && crm == 0) {
318            switch (opc2) {
319              case 0:
320                return MISCREG_DFAR;
321              case 2:
322                return MISCREG_IFAR;
323            }
324        } else if (opc1 == 4 && crm == 0) {
325            switch (opc2) {
326              case 0:
327                return MISCREG_HDFAR;
328              case 2:
329                return MISCREG_HIFAR;
330              case 4:
331                return MISCREG_HPFAR;
332            }
333        }
334        break;
335      case 7:
336        if (opc1 == 0) {
337            switch (crm) {
338              case 0:
339                if (opc2 == 4) {
340                    return MISCREG_NOP;
341                }
342                break;
343              case 1:
344                switch (opc2) {
345                  case 0:
346                    return MISCREG_ICIALLUIS;
347                  case 6:
348                    return MISCREG_BPIALLIS;
349                }
350                break;
351              case 4:
352                if (opc2 == 0) {
353                    return MISCREG_PAR;
354                }
355                break;
356              case 5:
357                switch (opc2) {
358                  case 0:
359                    return MISCREG_ICIALLU;
360                  case 1:
361                    return MISCREG_ICIMVAU;
362                  case 4:
363                    return MISCREG_CP15ISB;
364                  case 6:
365                    return MISCREG_BPIALL;
366                  case 7:
367                    return MISCREG_BPIMVA;
368                }
369                break;
370              case 6:
371                if (opc2 == 1) {
372                    return MISCREG_DCIMVAC;
373                } else if (opc2 == 2) {
374                    return MISCREG_DCISW;
375                }
376                break;
377              case 8:
378                switch (opc2) {
379                  case 0:
380                    return MISCREG_ATS1CPR;
381                  case 1:
382                    return MISCREG_ATS1CPW;
383                  case 2:
384                    return MISCREG_ATS1CUR;
385                  case 3:
386                    return MISCREG_ATS1CUW;
387                  case 4:
388                    return MISCREG_ATS12NSOPR;
389                  case 5:
390                    return MISCREG_ATS12NSOPW;
391                  case 6:
392                    return MISCREG_ATS12NSOUR;
393                  case 7:
394                    return MISCREG_ATS12NSOUW;
395                }
396                break;
397              case 10:
398                switch (opc2) {
399                  case 1:
400                    return MISCREG_DCCMVAC;
401                  case 2:
402                    return MISCREG_DCCSW;
403                  case 4:
404                    return MISCREG_CP15DSB;
405                  case 5:
406                    return MISCREG_CP15DMB;
407                }
408                break;
409              case 11:
410                if (opc2 == 1) {
411                    return MISCREG_DCCMVAU;
412                }
413                break;
414              case 13:
415                if (opc2 == 1) {
416                    return MISCREG_NOP;
417                }
418                break;
419              case 14:
420                if (opc2 == 1) {
421                    return MISCREG_DCCIMVAC;
422                } else if (opc2 == 2) {
423                    return MISCREG_DCCISW;
424                }
425                break;
426            }
427        } else if (opc1 == 4 && crm == 8) {
428            if (opc2 == 0)
429                return MISCREG_ATS1HR;
430            else if (opc2 == 1)
431                return MISCREG_ATS1HW;
432        }
433        break;
434      case 8:
435        if (opc1 == 0) {
436            switch (crm) {
437              case 3:
438                switch (opc2) {
439                  case 0:
440                    return MISCREG_TLBIALLIS;
441                  case 1:
442                    return MISCREG_TLBIMVAIS;
443                  case 2:
444                    return MISCREG_TLBIASIDIS;
445                  case 3:
446                    return MISCREG_TLBIMVAAIS;
447                  case 5:
448                    return MISCREG_TLBIMVALIS;
449                  case 7:
450                    return MISCREG_TLBIMVAALIS;
451                }
452                break;
453              case 5:
454                switch (opc2) {
455                  case 0:
456                    return MISCREG_ITLBIALL;
457                  case 1:
458                    return MISCREG_ITLBIMVA;
459                  case 2:
460                    return MISCREG_ITLBIASID;
461                }
462                break;
463              case 6:
464                switch (opc2) {
465                  case 0:
466                    return MISCREG_DTLBIALL;
467                  case 1:
468                    return MISCREG_DTLBIMVA;
469                  case 2:
470                    return MISCREG_DTLBIASID;
471                }
472                break;
473              case 7:
474                switch (opc2) {
475                  case 0:
476                    return MISCREG_TLBIALL;
477                  case 1:
478                    return MISCREG_TLBIMVA;
479                  case 2:
480                    return MISCREG_TLBIASID;
481                  case 3:
482                    return MISCREG_TLBIMVAA;
483                  case 5:
484                    return MISCREG_TLBIMVAL;
485                  case 7:
486                    return MISCREG_TLBIMVAAL;
487                }
488                break;
489            }
490        } else if (opc1 == 4) {
491            if (crm == 0) {
492                switch (opc2) {
493                  case 1:
494                    return MISCREG_TLBIIPAS2IS;
495                  case 5:
496                    return MISCREG_TLBIIPAS2LIS;
497                }
498            } else if (crm == 3) {
499                switch (opc2) {
500                  case 0:
501                    return MISCREG_TLBIALLHIS;
502                  case 1:
503                    return MISCREG_TLBIMVAHIS;
504                  case 4:
505                    return MISCREG_TLBIALLNSNHIS;
506                  case 5:
507                    return MISCREG_TLBIMVALHIS;
508                }
509            } else if (crm == 4) {
510                switch (opc2) {
511                  case 1:
512                    return MISCREG_TLBIIPAS2;
513                  case 5:
514                    return MISCREG_TLBIIPAS2L;
515                }
516            } else if (crm == 7) {
517                switch (opc2) {
518                  case 0:
519                    return MISCREG_TLBIALLH;
520                  case 1:
521                    return MISCREG_TLBIMVAH;
522                  case 4:
523                    return MISCREG_TLBIALLNSNH;
524                  case 5:
525                    return MISCREG_TLBIMVALH;
526                }
527            }
528        }
529        break;
530      case 9:
531        // Every cop register with CRn = 9 and CRm in
532        // {0-2}, {5-8} is implementation defined regardless
533        // of opc1 and opc2.
534        switch (crm) {
535          case 0:
536          case 1:
537          case 2:
538          case 5:
539          case 6:
540          case 7:
541          case 8:
542            return MISCREG_IMPDEF_UNIMPL;
543        }
544        if (opc1 == 0) {
545            switch (crm) {
546              case 12:
547                switch (opc2) {
548                  case 0:
549                    return MISCREG_PMCR;
550                  case 1:
551                    return MISCREG_PMCNTENSET;
552                  case 2:
553                    return MISCREG_PMCNTENCLR;
554                  case 3:
555                    return MISCREG_PMOVSR;
556                  case 4:
557                    return MISCREG_PMSWINC;
558                  case 5:
559                    return MISCREG_PMSELR;
560                  case 6:
561                    return MISCREG_PMCEID0;
562                  case 7:
563                    return MISCREG_PMCEID1;
564                }
565                break;
566              case 13:
567                switch (opc2) {
568                  case 0:
569                    return MISCREG_PMCCNTR;
570                  case 1:
571                    // Selector is PMSELR.SEL
572                    return MISCREG_PMXEVTYPER_PMCCFILTR;
573                  case 2:
574                    return MISCREG_PMXEVCNTR;
575                }
576                break;
577              case 14:
578                switch (opc2) {
579                  case 0:
580                    return MISCREG_PMUSERENR;
581                  case 1:
582                    return MISCREG_PMINTENSET;
583                  case 2:
584                    return MISCREG_PMINTENCLR;
585                  case 3:
586                    return MISCREG_PMOVSSET;
587                }
588                break;
589            }
590        } else if (opc1 == 1) {
591            switch (crm) {
592              case 0:
593                switch (opc2) {
594                  case 2: // L2CTLR, L2 Control Register
595                    return MISCREG_L2CTLR;
596                  case 3:
597                    return MISCREG_L2ECTLR;
598                }
599                break;
600                break;
601            }
602        }
603        break;
604      case 10:
605        if (opc1 == 0) {
606            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
607            if (crm < 2) {
608                return MISCREG_IMPDEF_UNIMPL;
609            } else if (crm == 2) { // TEX Remap Registers
610                if (opc2 == 0) {
611                    // Selector is TTBCR.EAE
612                    return MISCREG_PRRR_MAIR0;
613                } else if (opc2 == 1) {
614                    // Selector is TTBCR.EAE
615                    return MISCREG_NMRR_MAIR1;
616                }
617            } else if (crm == 3) {
618                if (opc2 == 0) {
619                    return MISCREG_AMAIR0;
620                } else if (opc2 == 1) {
621                    return MISCREG_AMAIR1;
622                }
623            }
624        } else if (opc1 == 4) {
625            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
626            if (crm == 2) {
627                if (opc2 == 0)
628                    return MISCREG_HMAIR0;
629                else if (opc2 == 1)
630                    return MISCREG_HMAIR1;
631            } else if (crm == 3) {
632                if (opc2 == 0)
633                    return MISCREG_HAMAIR0;
634                else if (opc2 == 1)
635                    return MISCREG_HAMAIR1;
636            }
637        }
638        break;
639      case 11:
640        if (opc1 <=7) {
641            switch (crm) {
642              case 0:
643              case 1:
644              case 2:
645              case 3:
646              case 4:
647              case 5:
648              case 6:
649              case 7:
650              case 8:
651              case 15:
652                // Reserved for DMA operations for TCM access
653                return MISCREG_IMPDEF_UNIMPL;
654              default:
655                break;
656            }
657        }
658        break;
659      case 12:
660        if (opc1 == 0) {
661            if (crm == 0) {
662                if (opc2 == 0) {
663                    return MISCREG_VBAR;
664                } else if (opc2 == 1) {
665                    return MISCREG_MVBAR;
666                }
667            } else if (crm == 1) {
668                if (opc2 == 0) {
669                    return MISCREG_ISR;
670                }
671            }
672        } else if (opc1 == 4) {
673            if (crm == 0 && opc2 == 0)
674                return MISCREG_HVBAR;
675        }
676        break;
677      case 13:
678        if (opc1 == 0) {
679            if (crm == 0) {
680                switch (opc2) {
681                  case 0:
682                    return MISCREG_FCSEIDR;
683                  case 1:
684                    return MISCREG_CONTEXTIDR;
685                  case 2:
686                    return MISCREG_TPIDRURW;
687                  case 3:
688                    return MISCREG_TPIDRURO;
689                  case 4:
690                    return MISCREG_TPIDRPRW;
691                }
692            }
693        } else if (opc1 == 4) {
694            if (crm == 0 && opc2 == 2)
695                return MISCREG_HTPIDR;
696        }
697        break;
698      case 14:
699        if (opc1 == 0) {
700            switch (crm) {
701              case 0:
702                if (opc2 == 0)
703                    return MISCREG_CNTFRQ;
704                break;
705              case 1:
706                if (opc2 == 0)
707                    return MISCREG_CNTKCTL;
708                break;
709              case 2:
710                if (opc2 == 0)
711                    return MISCREG_CNTP_TVAL;
712                else if (opc2 == 1)
713                    return MISCREG_CNTP_CTL;
714                break;
715              case 3:
716                if (opc2 == 0)
717                    return MISCREG_CNTV_TVAL;
718                else if (opc2 == 1)
719                    return MISCREG_CNTV_CTL;
720                break;
721            }
722        } else if (opc1 == 4) {
723            if (crm == 1 && opc2 == 0) {
724                return MISCREG_CNTHCTL;
725            } else if (crm == 2) {
726                if (opc2 == 0)
727                    return MISCREG_CNTHP_TVAL;
728                else if (opc2 == 1)
729                    return MISCREG_CNTHP_CTL;
730            }
731        }
732        break;
733      case 15:
734        // Implementation defined
735        return MISCREG_IMPDEF_UNIMPL;
736    }
737    // Unrecognized register
738    return MISCREG_CP15_UNIMPL;
739}
740
741MiscRegIndex
742decodeCP15Reg64(unsigned crm, unsigned opc1)
743{
744    switch (crm) {
745      case 2:
746        switch (opc1) {
747          case 0:
748            return MISCREG_TTBR0;
749          case 1:
750            return MISCREG_TTBR1;
751          case 4:
752            return MISCREG_HTTBR;
753          case 6:
754            return MISCREG_VTTBR;
755        }
756        break;
757      case 7:
758        if (opc1 == 0)
759            return MISCREG_PAR;
760        break;
761      case 14:
762        switch (opc1) {
763          case 0:
764            return MISCREG_CNTPCT;
765          case 1:
766            return MISCREG_CNTVCT;
767          case 2:
768            return MISCREG_CNTP_CVAL;
769          case 3:
770            return MISCREG_CNTV_CVAL;
771          case 4:
772            return MISCREG_CNTVOFF;
773          case 6:
774            return MISCREG_CNTHP_CVAL;
775        }
776        break;
777      case 15:
778        if (opc1 == 0)
779            return MISCREG_CPUMERRSR;
780        else if (opc1 == 1)
781            return MISCREG_L2MERRSR;
782        break;
783    }
784    // Unrecognized register
785    return MISCREG_CP15_UNIMPL;
786}
787
788std::tuple<bool, bool>
789canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
790{
791    bool secure = !scr.ns;
792    bool canRead = false;
793    bool undefined = false;
794
795    switch (cpsr.mode) {
796      case MODE_USER:
797        canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
798                           miscRegInfo[reg][MISCREG_USR_NS_RD];
799        break;
800      case MODE_FIQ:
801      case MODE_IRQ:
802      case MODE_SVC:
803      case MODE_ABORT:
804      case MODE_UNDEFINED:
805      case MODE_SYSTEM:
806        canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
807                           miscRegInfo[reg][MISCREG_PRI_NS_RD];
808        break;
809      case MODE_MON:
810        canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
811                           miscRegInfo[reg][MISCREG_MON_NS1_RD];
812        break;
813      case MODE_HYP:
814        canRead = miscRegInfo[reg][MISCREG_HYP_RD];
815        break;
816      default:
817        undefined = true;
818    }
819    // can't do permissions checkes on the root of a banked pair of regs
820    assert(!miscRegInfo[reg][MISCREG_BANKED]);
821    return std::make_tuple(canRead, undefined);
822}
823
824std::tuple<bool, bool>
825canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
826{
827    bool secure = !scr.ns;
828    bool canWrite = false;
829    bool undefined = false;
830
831    switch (cpsr.mode) {
832      case MODE_USER:
833        canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
834                            miscRegInfo[reg][MISCREG_USR_NS_WR];
835        break;
836      case MODE_FIQ:
837      case MODE_IRQ:
838      case MODE_SVC:
839      case MODE_ABORT:
840      case MODE_UNDEFINED:
841      case MODE_SYSTEM:
842        canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
843                            miscRegInfo[reg][MISCREG_PRI_NS_WR];
844        break;
845      case MODE_MON:
846        canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
847                            miscRegInfo[reg][MISCREG_MON_NS1_WR];
848        break;
849      case MODE_HYP:
850        canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
851        break;
852      default:
853        undefined = true;
854    }
855    // can't do permissions checkes on the root of a banked pair of regs
856    assert(!miscRegInfo[reg][MISCREG_BANKED]);
857    return std::make_tuple(canWrite, undefined);
858}
859
860int
861snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
862{
863    SCR scr = tc->readMiscReg(MISCREG_SCR);
864    return snsBankedIndex(reg, tc, scr.ns);
865}
866
867int
868snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
869{
870    int reg_as_int = static_cast<int>(reg);
871    if (miscRegInfo[reg][MISCREG_BANKED]) {
872        reg_as_int += (ArmSystem::haveSecurity(tc) &&
873                      !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
874    }
875    return reg_as_int;
876}
877
878
879/**
880 * If the reg is a child reg of a banked set, then the parent is the last
881 * banked one in the list. This is messy, and the wish is to eventually have
882 * the bitmap replaced with a better data structure. the preUnflatten function
883 * initializes a lookup table to speed up the search for these banked
884 * registers.
885 */
886
887int unflattenResultMiscReg[NUM_MISCREGS];
888
889void
890preUnflattenMiscReg()
891{
892    int reg = -1;
893    for (int i = 0 ; i < NUM_MISCREGS; i++){
894        if (miscRegInfo[i][MISCREG_BANKED])
895            reg = i;
896        if (miscRegInfo[i][MISCREG_BANKED_CHILD])
897            unflattenResultMiscReg[i] = reg;
898        else
899            unflattenResultMiscReg[i] = i;
900        // if this assert fails, no parent was found, and something is broken
901        assert(unflattenResultMiscReg[i] > -1);
902    }
903}
904
905int
906unflattenMiscReg(int reg)
907{
908    return unflattenResultMiscReg[reg];
909}
910
911bool
912canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
913{
914    // Check for SP_EL0 access while SPSEL == 0
915    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
916        return false;
917
918    // Check for RVBAR access
919    if (reg == MISCREG_RVBAR_EL1) {
920        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
921        if (highest_el == EL2 || highest_el == EL3)
922            return false;
923    }
924    if (reg == MISCREG_RVBAR_EL2) {
925        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
926        if (highest_el == EL3)
927            return false;
928    }
929
930    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
931
932    switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
933      case EL0:
934        return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
935            miscRegInfo[reg][MISCREG_USR_NS_RD];
936      case EL1:
937        return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
938            miscRegInfo[reg][MISCREG_PRI_NS_RD];
939      case EL2:
940        return miscRegInfo[reg][MISCREG_HYP_RD];
941      case EL3:
942        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
943            miscRegInfo[reg][MISCREG_MON_NS1_RD];
944      default:
945        panic("Invalid exception level");
946    }
947}
948
949bool
950canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
951{
952    // Check for SP_EL0 access while SPSEL == 0
953    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
954        return false;
955    ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
956    if (reg == MISCREG_DAIF) {
957        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
958        if (el == EL0 && !sctlr.uma)
959            return false;
960    }
961    if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
962        // In syscall-emulation mode, this test is skipped and DCZVA is always
963        // allowed at EL0
964        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
965        if (el == EL0 && !sctlr.dze)
966            return false;
967    }
968    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
969        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
970        if (el == EL0 && !sctlr.uci)
971            return false;
972    }
973
974    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
975
976    switch (el) {
977      case EL0:
978        return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
979            miscRegInfo[reg][MISCREG_USR_NS_WR];
980      case EL1:
981        return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
982            miscRegInfo[reg][MISCREG_PRI_NS_WR];
983      case EL2:
984        return miscRegInfo[reg][MISCREG_HYP_WR];
985      case EL3:
986        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
987            miscRegInfo[reg][MISCREG_MON_NS1_WR];
988      default:
989        panic("Invalid exception level");
990    }
991}
992
993MiscRegIndex
994decodeAArch64SysReg(unsigned op0, unsigned op1,
995                    unsigned crn, unsigned crm,
996                    unsigned op2)
997{
998    switch (op0) {
999      case 1:
1000        switch (crn) {
1001          case 7:
1002            switch (op1) {
1003              case 0:
1004                switch (crm) {
1005                  case 1:
1006                    switch (op2) {
1007                      case 0:
1008                        return MISCREG_IC_IALLUIS;
1009                    }
1010                    break;
1011                  case 5:
1012                    switch (op2) {
1013                      case 0:
1014                        return MISCREG_IC_IALLU;
1015                    }
1016                    break;
1017                  case 6:
1018                    switch (op2) {
1019                      case 1:
1020                        return MISCREG_DC_IVAC_Xt;
1021                      case 2:
1022                        return MISCREG_DC_ISW_Xt;
1023                    }
1024                    break;
1025                  case 8:
1026                    switch (op2) {
1027                      case 0:
1028                        return MISCREG_AT_S1E1R_Xt;
1029                      case 1:
1030                        return MISCREG_AT_S1E1W_Xt;
1031                      case 2:
1032                        return MISCREG_AT_S1E0R_Xt;
1033                      case 3:
1034                        return MISCREG_AT_S1E0W_Xt;
1035                    }
1036                    break;
1037                  case 10:
1038                    switch (op2) {
1039                      case 2:
1040                        return MISCREG_DC_CSW_Xt;
1041                    }
1042                    break;
1043                  case 14:
1044                    switch (op2) {
1045                      case 2:
1046                        return MISCREG_DC_CISW_Xt;
1047                    }
1048                    break;
1049                }
1050                break;
1051              case 3:
1052                switch (crm) {
1053                  case 4:
1054                    switch (op2) {
1055                      case 1:
1056                        return MISCREG_DC_ZVA_Xt;
1057                    }
1058                    break;
1059                  case 5:
1060                    switch (op2) {
1061                      case 1:
1062                        return MISCREG_IC_IVAU_Xt;
1063                    }
1064                    break;
1065                  case 10:
1066                    switch (op2) {
1067                      case 1:
1068                        return MISCREG_DC_CVAC_Xt;
1069                    }
1070                    break;
1071                  case 11:
1072                    switch (op2) {
1073                      case 1:
1074                        return MISCREG_DC_CVAU_Xt;
1075                    }
1076                    break;
1077                  case 14:
1078                    switch (op2) {
1079                      case 1:
1080                        return MISCREG_DC_CIVAC_Xt;
1081                    }
1082                    break;
1083                }
1084                break;
1085              case 4:
1086                switch (crm) {
1087                  case 8:
1088                    switch (op2) {
1089                      case 0:
1090                        return MISCREG_AT_S1E2R_Xt;
1091                      case 1:
1092                        return MISCREG_AT_S1E2W_Xt;
1093                      case 4:
1094                        return MISCREG_AT_S12E1R_Xt;
1095                      case 5:
1096                        return MISCREG_AT_S12E1W_Xt;
1097                      case 6:
1098                        return MISCREG_AT_S12E0R_Xt;
1099                      case 7:
1100                        return MISCREG_AT_S12E0W_Xt;
1101                    }
1102                    break;
1103                }
1104                break;
1105              case 6:
1106                switch (crm) {
1107                  case 8:
1108                    switch (op2) {
1109                      case 0:
1110                        return MISCREG_AT_S1E3R_Xt;
1111                      case 1:
1112                        return MISCREG_AT_S1E3W_Xt;
1113                    }
1114                    break;
1115                }
1116                break;
1117            }
1118            break;
1119          case 8:
1120            switch (op1) {
1121              case 0:
1122                switch (crm) {
1123                  case 3:
1124                    switch (op2) {
1125                      case 0:
1126                        return MISCREG_TLBI_VMALLE1IS;
1127                      case 1:
1128                        return MISCREG_TLBI_VAE1IS_Xt;
1129                      case 2:
1130                        return MISCREG_TLBI_ASIDE1IS_Xt;
1131                      case 3:
1132                        return MISCREG_TLBI_VAAE1IS_Xt;
1133                      case 5:
1134                        return MISCREG_TLBI_VALE1IS_Xt;
1135                      case 7:
1136                        return MISCREG_TLBI_VAALE1IS_Xt;
1137                    }
1138                    break;
1139                  case 7:
1140                    switch (op2) {
1141                      case 0:
1142                        return MISCREG_TLBI_VMALLE1;
1143                      case 1:
1144                        return MISCREG_TLBI_VAE1_Xt;
1145                      case 2:
1146                        return MISCREG_TLBI_ASIDE1_Xt;
1147                      case 3:
1148                        return MISCREG_TLBI_VAAE1_Xt;
1149                      case 5:
1150                        return MISCREG_TLBI_VALE1_Xt;
1151                      case 7:
1152                        return MISCREG_TLBI_VAALE1_Xt;
1153                    }
1154                    break;
1155                }
1156                break;
1157              case 4:
1158                switch (crm) {
1159                  case 0:
1160                    switch (op2) {
1161                      case 1:
1162                        return MISCREG_TLBI_IPAS2E1IS_Xt;
1163                      case 5:
1164                        return MISCREG_TLBI_IPAS2LE1IS_Xt;
1165                    }
1166                    break;
1167                  case 3:
1168                    switch (op2) {
1169                      case 0:
1170                        return MISCREG_TLBI_ALLE2IS;
1171                      case 1:
1172                        return MISCREG_TLBI_VAE2IS_Xt;
1173                      case 4:
1174                        return MISCREG_TLBI_ALLE1IS;
1175                      case 5:
1176                        return MISCREG_TLBI_VALE2IS_Xt;
1177                      case 6:
1178                        return MISCREG_TLBI_VMALLS12E1IS;
1179                    }
1180                    break;
1181                  case 4:
1182                    switch (op2) {
1183                      case 1:
1184                        return MISCREG_TLBI_IPAS2E1_Xt;
1185                      case 5:
1186                        return MISCREG_TLBI_IPAS2LE1_Xt;
1187                    }
1188                    break;
1189                  case 7:
1190                    switch (op2) {
1191                      case 0:
1192                        return MISCREG_TLBI_ALLE2;
1193                      case 1:
1194                        return MISCREG_TLBI_VAE2_Xt;
1195                      case 4:
1196                        return MISCREG_TLBI_ALLE1;
1197                      case 5:
1198                        return MISCREG_TLBI_VALE2_Xt;
1199                      case 6:
1200                        return MISCREG_TLBI_VMALLS12E1;
1201                    }
1202                    break;
1203                }
1204                break;
1205              case 6:
1206                switch (crm) {
1207                  case 3:
1208                    switch (op2) {
1209                      case 0:
1210                        return MISCREG_TLBI_ALLE3IS;
1211                      case 1:
1212                        return MISCREG_TLBI_VAE3IS_Xt;
1213                      case 5:
1214                        return MISCREG_TLBI_VALE3IS_Xt;
1215                    }
1216                    break;
1217                  case 7:
1218                    switch (op2) {
1219                      case 0:
1220                        return MISCREG_TLBI_ALLE3;
1221                      case 1:
1222                        return MISCREG_TLBI_VAE3_Xt;
1223                      case 5:
1224                        return MISCREG_TLBI_VALE3_Xt;
1225                    }
1226                    break;
1227                }
1228                break;
1229            }
1230            break;
1231          case 11:
1232          case 15:
1233            // SYS Instruction with CRn = { 11, 15 }
1234            // (Trappable by HCR_EL2.TIDCP)
1235            return MISCREG_IMPDEF_UNIMPL;
1236        }
1237        break;
1238      case 2:
1239        switch (crn) {
1240          case 0:
1241            switch (op1) {
1242              case 0:
1243                switch (crm) {
1244                  case 0:
1245                    switch (op2) {
1246                      case 2:
1247                        return MISCREG_OSDTRRX_EL1;
1248                      case 4:
1249                        return MISCREG_DBGBVR0_EL1;
1250                      case 5:
1251                        return MISCREG_DBGBCR0_EL1;
1252                      case 6:
1253                        return MISCREG_DBGWVR0_EL1;
1254                      case 7:
1255                        return MISCREG_DBGWCR0_EL1;
1256                    }
1257                    break;
1258                  case 1:
1259                    switch (op2) {
1260                      case 4:
1261                        return MISCREG_DBGBVR1_EL1;
1262                      case 5:
1263                        return MISCREG_DBGBCR1_EL1;
1264                      case 6:
1265                        return MISCREG_DBGWVR1_EL1;
1266                      case 7:
1267                        return MISCREG_DBGWCR1_EL1;
1268                    }
1269                    break;
1270                  case 2:
1271                    switch (op2) {
1272                      case 0:
1273                        return MISCREG_MDCCINT_EL1;
1274                      case 2:
1275                        return MISCREG_MDSCR_EL1;
1276                      case 4:
1277                        return MISCREG_DBGBVR2_EL1;
1278                      case 5:
1279                        return MISCREG_DBGBCR2_EL1;
1280                      case 6:
1281                        return MISCREG_DBGWVR2_EL1;
1282                      case 7:
1283                        return MISCREG_DBGWCR2_EL1;
1284                    }
1285                    break;
1286                  case 3:
1287                    switch (op2) {
1288                      case 2:
1289                        return MISCREG_OSDTRTX_EL1;
1290                      case 4:
1291                        return MISCREG_DBGBVR3_EL1;
1292                      case 5:
1293                        return MISCREG_DBGBCR3_EL1;
1294                      case 6:
1295                        return MISCREG_DBGWVR3_EL1;
1296                      case 7:
1297                        return MISCREG_DBGWCR3_EL1;
1298                    }
1299                    break;
1300                  case 4:
1301                    switch (op2) {
1302                      case 4:
1303                        return MISCREG_DBGBVR4_EL1;
1304                      case 5:
1305                        return MISCREG_DBGBCR4_EL1;
1306                    }
1307                    break;
1308                  case 5:
1309                    switch (op2) {
1310                      case 4:
1311                        return MISCREG_DBGBVR5_EL1;
1312                      case 5:
1313                        return MISCREG_DBGBCR5_EL1;
1314                    }
1315                    break;
1316                  case 6:
1317                    switch (op2) {
1318                      case 2:
1319                        return MISCREG_OSECCR_EL1;
1320                    }
1321                    break;
1322                }
1323                break;
1324              case 2:
1325                switch (crm) {
1326                  case 0:
1327                    switch (op2) {
1328                      case 0:
1329                        return MISCREG_TEECR32_EL1;
1330                    }
1331                    break;
1332                }
1333                break;
1334              case 3:
1335                switch (crm) {
1336                  case 1:
1337                    switch (op2) {
1338                      case 0:
1339                        return MISCREG_MDCCSR_EL0;
1340                    }
1341                    break;
1342                  case 4:
1343                    switch (op2) {
1344                      case 0:
1345                        return MISCREG_MDDTR_EL0;
1346                    }
1347                    break;
1348                  case 5:
1349                    switch (op2) {
1350                      case 0:
1351                        return MISCREG_MDDTRRX_EL0;
1352                    }
1353                    break;
1354                }
1355                break;
1356              case 4:
1357                switch (crm) {
1358                  case 7:
1359                    switch (op2) {
1360                      case 0:
1361                        return MISCREG_DBGVCR32_EL2;
1362                    }
1363                    break;
1364                }
1365                break;
1366            }
1367            break;
1368          case 1:
1369            switch (op1) {
1370              case 0:
1371                switch (crm) {
1372                  case 0:
1373                    switch (op2) {
1374                      case 0:
1375                        return MISCREG_MDRAR_EL1;
1376                      case 4:
1377                        return MISCREG_OSLAR_EL1;
1378                    }
1379                    break;
1380                  case 1:
1381                    switch (op2) {
1382                      case 4:
1383                        return MISCREG_OSLSR_EL1;
1384                    }
1385                    break;
1386                  case 3:
1387                    switch (op2) {
1388                      case 4:
1389                        return MISCREG_OSDLR_EL1;
1390                    }
1391                    break;
1392                  case 4:
1393                    switch (op2) {
1394                      case 4:
1395                        return MISCREG_DBGPRCR_EL1;
1396                    }
1397                    break;
1398                }
1399                break;
1400              case 2:
1401                switch (crm) {
1402                  case 0:
1403                    switch (op2) {
1404                      case 0:
1405                        return MISCREG_TEEHBR32_EL1;
1406                    }
1407                    break;
1408                }
1409                break;
1410            }
1411            break;
1412          case 7:
1413            switch (op1) {
1414              case 0:
1415                switch (crm) {
1416                  case 8:
1417                    switch (op2) {
1418                      case 6:
1419                        return MISCREG_DBGCLAIMSET_EL1;
1420                    }
1421                    break;
1422                  case 9:
1423                    switch (op2) {
1424                      case 6:
1425                        return MISCREG_DBGCLAIMCLR_EL1;
1426                    }
1427                    break;
1428                  case 14:
1429                    switch (op2) {
1430                      case 6:
1431                        return MISCREG_DBGAUTHSTATUS_EL1;
1432                    }
1433                    break;
1434                }
1435                break;
1436            }
1437            break;
1438        }
1439        break;
1440      case 3:
1441        switch (crn) {
1442          case 0:
1443            switch (op1) {
1444              case 0:
1445                switch (crm) {
1446                  case 0:
1447                    switch (op2) {
1448                      case 0:
1449                        return MISCREG_MIDR_EL1;
1450                      case 5:
1451                        return MISCREG_MPIDR_EL1;
1452                      case 6:
1453                        return MISCREG_REVIDR_EL1;
1454                    }
1455                    break;
1456                  case 1:
1457                    switch (op2) {
1458                      case 0:
1459                        return MISCREG_ID_PFR0_EL1;
1460                      case 1:
1461                        return MISCREG_ID_PFR1_EL1;
1462                      case 2:
1463                        return MISCREG_ID_DFR0_EL1;
1464                      case 3:
1465                        return MISCREG_ID_AFR0_EL1;
1466                      case 4:
1467                        return MISCREG_ID_MMFR0_EL1;
1468                      case 5:
1469                        return MISCREG_ID_MMFR1_EL1;
1470                      case 6:
1471                        return MISCREG_ID_MMFR2_EL1;
1472                      case 7:
1473                        return MISCREG_ID_MMFR3_EL1;
1474                    }
1475                    break;
1476                  case 2:
1477                    switch (op2) {
1478                      case 0:
1479                        return MISCREG_ID_ISAR0_EL1;
1480                      case 1:
1481                        return MISCREG_ID_ISAR1_EL1;
1482                      case 2:
1483                        return MISCREG_ID_ISAR2_EL1;
1484                      case 3:
1485                        return MISCREG_ID_ISAR3_EL1;
1486                      case 4:
1487                        return MISCREG_ID_ISAR4_EL1;
1488                      case 5:
1489                        return MISCREG_ID_ISAR5_EL1;
1490                    }
1491                    break;
1492                  case 3:
1493                    switch (op2) {
1494                      case 0:
1495                        return MISCREG_MVFR0_EL1;
1496                      case 1:
1497                        return MISCREG_MVFR1_EL1;
1498                      case 2:
1499                        return MISCREG_MVFR2_EL1;
1500                      case 3 ... 7:
1501                        return MISCREG_RAZ;
1502                    }
1503                    break;
1504                  case 4:
1505                    switch (op2) {
1506                      case 0:
1507                        return MISCREG_ID_AA64PFR0_EL1;
1508                      case 1:
1509                        return MISCREG_ID_AA64PFR1_EL1;
1510                      case 2 ... 7:
1511                        return MISCREG_RAZ;
1512                    }
1513                    break;
1514                  case 5:
1515                    switch (op2) {
1516                      case 0:
1517                        return MISCREG_ID_AA64DFR0_EL1;
1518                      case 1:
1519                        return MISCREG_ID_AA64DFR1_EL1;
1520                      case 4:
1521                        return MISCREG_ID_AA64AFR0_EL1;
1522                      case 5:
1523                        return MISCREG_ID_AA64AFR1_EL1;
1524                      case 2:
1525                      case 3:
1526                      case 6:
1527                      case 7:
1528                        return MISCREG_RAZ;
1529                    }
1530                    break;
1531                  case 6:
1532                    switch (op2) {
1533                      case 0:
1534                        return MISCREG_ID_AA64ISAR0_EL1;
1535                      case 1:
1536                        return MISCREG_ID_AA64ISAR1_EL1;
1537                      case 2 ... 7:
1538                        return MISCREG_RAZ;
1539                    }
1540                    break;
1541                  case 7:
1542                    switch (op2) {
1543                      case 0:
1544                        return MISCREG_ID_AA64MMFR0_EL1;
1545                      case 1:
1546                        return MISCREG_ID_AA64MMFR1_EL1;
1547                      case 2:
1548                        return MISCREG_ID_AA64MMFR2_EL1;
1549                      case 3 ... 7:
1550                        return MISCREG_RAZ;
1551                    }
1552                    break;
1553                }
1554                break;
1555              case 1:
1556                switch (crm) {
1557                  case 0:
1558                    switch (op2) {
1559                      case 0:
1560                        return MISCREG_CCSIDR_EL1;
1561                      case 1:
1562                        return MISCREG_CLIDR_EL1;
1563                      case 7:
1564                        return MISCREG_AIDR_EL1;
1565                    }
1566                    break;
1567                }
1568                break;
1569              case 2:
1570                switch (crm) {
1571                  case 0:
1572                    switch (op2) {
1573                      case 0:
1574                        return MISCREG_CSSELR_EL1;
1575                    }
1576                    break;
1577                }
1578                break;
1579              case 3:
1580                switch (crm) {
1581                  case 0:
1582                    switch (op2) {
1583                      case 1:
1584                        return MISCREG_CTR_EL0;
1585                      case 7:
1586                        return MISCREG_DCZID_EL0;
1587                    }
1588                    break;
1589                }
1590                break;
1591              case 4:
1592                switch (crm) {
1593                  case 0:
1594                    switch (op2) {
1595                      case 0:
1596                        return MISCREG_VPIDR_EL2;
1597                      case 5:
1598                        return MISCREG_VMPIDR_EL2;
1599                    }
1600                    break;
1601                }
1602                break;
1603            }
1604            break;
1605          case 1:
1606            switch (op1) {
1607              case 0:
1608                switch (crm) {
1609                  case 0:
1610                    switch (op2) {
1611                      case 0:
1612                        return MISCREG_SCTLR_EL1;
1613                      case 1:
1614                        return MISCREG_ACTLR_EL1;
1615                      case 2:
1616                        return MISCREG_CPACR_EL1;
1617                    }
1618                    break;
1619                }
1620                break;
1621              case 4:
1622                switch (crm) {
1623                  case 0:
1624                    switch (op2) {
1625                      case 0:
1626                        return MISCREG_SCTLR_EL2;
1627                      case 1:
1628                        return MISCREG_ACTLR_EL2;
1629                    }
1630                    break;
1631                  case 1:
1632                    switch (op2) {
1633                      case 0:
1634                        return MISCREG_HCR_EL2;
1635                      case 1:
1636                        return MISCREG_MDCR_EL2;
1637                      case 2:
1638                        return MISCREG_CPTR_EL2;
1639                      case 3:
1640                        return MISCREG_HSTR_EL2;
1641                      case 7:
1642                        return MISCREG_HACR_EL2;
1643                    }
1644                    break;
1645                }
1646                break;
1647              case 6:
1648                switch (crm) {
1649                  case 0:
1650                    switch (op2) {
1651                      case 0:
1652                        return MISCREG_SCTLR_EL3;
1653                      case 1:
1654                        return MISCREG_ACTLR_EL3;
1655                    }
1656                    break;
1657                  case 1:
1658                    switch (op2) {
1659                      case 0:
1660                        return MISCREG_SCR_EL3;
1661                      case 1:
1662                        return MISCREG_SDER32_EL3;
1663                      case 2:
1664                        return MISCREG_CPTR_EL3;
1665                    }
1666                    break;
1667                  case 3:
1668                    switch (op2) {
1669                      case 1:
1670                        return MISCREG_MDCR_EL3;
1671                    }
1672                    break;
1673                }
1674                break;
1675            }
1676            break;
1677          case 2:
1678            switch (op1) {
1679              case 0:
1680                switch (crm) {
1681                  case 0:
1682                    switch (op2) {
1683                      case 0:
1684                        return MISCREG_TTBR0_EL1;
1685                      case 1:
1686                        return MISCREG_TTBR1_EL1;
1687                      case 2:
1688                        return MISCREG_TCR_EL1;
1689                    }
1690                    break;
1691                }
1692                break;
1693              case 4:
1694                switch (crm) {
1695                  case 0:
1696                    switch (op2) {
1697                      case 0:
1698                        return MISCREG_TTBR0_EL2;
1699                      case 1:
1700                        return MISCREG_TTBR1_EL2;
1701                      case 2:
1702                        return MISCREG_TCR_EL2;
1703                    }
1704                    break;
1705                  case 1:
1706                    switch (op2) {
1707                      case 0:
1708                        return MISCREG_VTTBR_EL2;
1709                      case 2:
1710                        return MISCREG_VTCR_EL2;
1711                    }
1712                    break;
1713                }
1714                break;
1715              case 6:
1716                switch (crm) {
1717                  case 0:
1718                    switch (op2) {
1719                      case 0:
1720                        return MISCREG_TTBR0_EL3;
1721                      case 2:
1722                        return MISCREG_TCR_EL3;
1723                    }
1724                    break;
1725                }
1726                break;
1727            }
1728            break;
1729          case 3:
1730            switch (op1) {
1731              case 4:
1732                switch (crm) {
1733                  case 0:
1734                    switch (op2) {
1735                      case 0:
1736                        return MISCREG_DACR32_EL2;
1737                    }
1738                    break;
1739                }
1740                break;
1741            }
1742            break;
1743          case 4:
1744            switch (op1) {
1745              case 0:
1746                switch (crm) {
1747                  case 0:
1748                    switch (op2) {
1749                      case 0:
1750                        return MISCREG_SPSR_EL1;
1751                      case 1:
1752                        return MISCREG_ELR_EL1;
1753                    }
1754                    break;
1755                  case 1:
1756                    switch (op2) {
1757                      case 0:
1758                        return MISCREG_SP_EL0;
1759                    }
1760                    break;
1761                  case 2:
1762                    switch (op2) {
1763                      case 0:
1764                        return MISCREG_SPSEL;
1765                      case 2:
1766                        return MISCREG_CURRENTEL;
1767                    }
1768                    break;
1769                }
1770                break;
1771              case 3:
1772                switch (crm) {
1773                  case 2:
1774                    switch (op2) {
1775                      case 0:
1776                        return MISCREG_NZCV;
1777                      case 1:
1778                        return MISCREG_DAIF;
1779                    }
1780                    break;
1781                  case 4:
1782                    switch (op2) {
1783                      case 0:
1784                        return MISCREG_FPCR;
1785                      case 1:
1786                        return MISCREG_FPSR;
1787                    }
1788                    break;
1789                  case 5:
1790                    switch (op2) {
1791                      case 0:
1792                        return MISCREG_DSPSR_EL0;
1793                      case 1:
1794                        return MISCREG_DLR_EL0;
1795                    }
1796                    break;
1797                }
1798                break;
1799              case 4:
1800                switch (crm) {
1801                  case 0:
1802                    switch (op2) {
1803                      case 0:
1804                        return MISCREG_SPSR_EL2;
1805                      case 1:
1806                        return MISCREG_ELR_EL2;
1807                    }
1808                    break;
1809                  case 1:
1810                    switch (op2) {
1811                      case 0:
1812                        return MISCREG_SP_EL1;
1813                    }
1814                    break;
1815                  case 3:
1816                    switch (op2) {
1817                      case 0:
1818                        return MISCREG_SPSR_IRQ_AA64;
1819                      case 1:
1820                        return MISCREG_SPSR_ABT_AA64;
1821                      case 2:
1822                        return MISCREG_SPSR_UND_AA64;
1823                      case 3:
1824                        return MISCREG_SPSR_FIQ_AA64;
1825                    }
1826                    break;
1827                }
1828                break;
1829              case 6:
1830                switch (crm) {
1831                  case 0:
1832                    switch (op2) {
1833                      case 0:
1834                        return MISCREG_SPSR_EL3;
1835                      case 1:
1836                        return MISCREG_ELR_EL3;
1837                    }
1838                    break;
1839                  case 1:
1840                    switch (op2) {
1841                      case 0:
1842                        return MISCREG_SP_EL2;
1843                    }
1844                    break;
1845                }
1846                break;
1847            }
1848            break;
1849          case 5:
1850            switch (op1) {
1851              case 0:
1852                switch (crm) {
1853                  case 1:
1854                    switch (op2) {
1855                      case 0:
1856                        return MISCREG_AFSR0_EL1;
1857                      case 1:
1858                        return MISCREG_AFSR1_EL1;
1859                    }
1860                    break;
1861                  case 2:
1862                    switch (op2) {
1863                      case 0:
1864                        return MISCREG_ESR_EL1;
1865                    }
1866                    break;
1867                  case 3:
1868                    switch (op2) {
1869                      case 0:
1870                        return MISCREG_ERRIDR_EL1;
1871                      case 1:
1872                        return MISCREG_ERRSELR_EL1;
1873                    }
1874                    break;
1875                  case 4:
1876                    switch (op2) {
1877                      case 0:
1878                        return MISCREG_ERXFR_EL1;
1879                      case 1:
1880                        return MISCREG_ERXCTLR_EL1;
1881                      case 2:
1882                        return MISCREG_ERXSTATUS_EL1;
1883                      case 3:
1884                        return MISCREG_ERXADDR_EL1;
1885                    }
1886                    break;
1887                  case 5:
1888                    switch (op2) {
1889                      case 0:
1890                        return MISCREG_ERXMISC0_EL1;
1891                      case 1:
1892                        return MISCREG_ERXMISC1_EL1;
1893                    }
1894                    break;
1895                }
1896                break;
1897              case 4:
1898                switch (crm) {
1899                  case 0:
1900                    switch (op2) {
1901                      case 1:
1902                        return MISCREG_IFSR32_EL2;
1903                    }
1904                    break;
1905                  case 1:
1906                    switch (op2) {
1907                      case 0:
1908                        return MISCREG_AFSR0_EL2;
1909                      case 1:
1910                        return MISCREG_AFSR1_EL2;
1911                    }
1912                    break;
1913                  case 2:
1914                    switch (op2) {
1915                      case 0:
1916                        return MISCREG_ESR_EL2;
1917                      case 3:
1918                        return MISCREG_VSESR_EL2;
1919                    }
1920                    break;
1921                  case 3:
1922                    switch (op2) {
1923                      case 0:
1924                        return MISCREG_FPEXC32_EL2;
1925                    }
1926                    break;
1927                }
1928                break;
1929              case 6:
1930                switch (crm) {
1931                  case 1:
1932                    switch (op2) {
1933                      case 0:
1934                        return MISCREG_AFSR0_EL3;
1935                      case 1:
1936                        return MISCREG_AFSR1_EL3;
1937                    }
1938                    break;
1939                  case 2:
1940                    switch (op2) {
1941                      case 0:
1942                        return MISCREG_ESR_EL3;
1943                    }
1944                    break;
1945                }
1946                break;
1947            }
1948            break;
1949          case 6:
1950            switch (op1) {
1951              case 0:
1952                switch (crm) {
1953                  case 0:
1954                    switch (op2) {
1955                      case 0:
1956                        return MISCREG_FAR_EL1;
1957                    }
1958                    break;
1959                }
1960                break;
1961              case 4:
1962                switch (crm) {
1963                  case 0:
1964                    switch (op2) {
1965                      case 0:
1966                        return MISCREG_FAR_EL2;
1967                      case 4:
1968                        return MISCREG_HPFAR_EL2;
1969                    }
1970                    break;
1971                }
1972                break;
1973              case 6:
1974                switch (crm) {
1975                  case 0:
1976                    switch (op2) {
1977                      case 0:
1978                        return MISCREG_FAR_EL3;
1979                    }
1980                    break;
1981                }
1982                break;
1983            }
1984            break;
1985          case 7:
1986            switch (op1) {
1987              case 0:
1988                switch (crm) {
1989                  case 4:
1990                    switch (op2) {
1991                      case 0:
1992                        return MISCREG_PAR_EL1;
1993                    }
1994                    break;
1995                }
1996                break;
1997            }
1998            break;
1999          case 9:
2000            switch (op1) {
2001              case 0:
2002                switch (crm) {
2003                  case 14:
2004                    switch (op2) {
2005                      case 1:
2006                        return MISCREG_PMINTENSET_EL1;
2007                      case 2:
2008                        return MISCREG_PMINTENCLR_EL1;
2009                    }
2010                    break;
2011                }
2012                break;
2013              case 3:
2014                switch (crm) {
2015                  case 12:
2016                    switch (op2) {
2017                      case 0:
2018                        return MISCREG_PMCR_EL0;
2019                      case 1:
2020                        return MISCREG_PMCNTENSET_EL0;
2021                      case 2:
2022                        return MISCREG_PMCNTENCLR_EL0;
2023                      case 3:
2024                        return MISCREG_PMOVSCLR_EL0;
2025                      case 4:
2026                        return MISCREG_PMSWINC_EL0;
2027                      case 5:
2028                        return MISCREG_PMSELR_EL0;
2029                      case 6:
2030                        return MISCREG_PMCEID0_EL0;
2031                      case 7:
2032                        return MISCREG_PMCEID1_EL0;
2033                    }
2034                    break;
2035                  case 13:
2036                    switch (op2) {
2037                      case 0:
2038                        return MISCREG_PMCCNTR_EL0;
2039                      case 1:
2040                        return MISCREG_PMXEVTYPER_EL0;
2041                      case 2:
2042                        return MISCREG_PMXEVCNTR_EL0;
2043                    }
2044                    break;
2045                  case 14:
2046                    switch (op2) {
2047                      case 0:
2048                        return MISCREG_PMUSERENR_EL0;
2049                      case 3:
2050                        return MISCREG_PMOVSSET_EL0;
2051                    }
2052                    break;
2053                }
2054                break;
2055            }
2056            break;
2057          case 10:
2058            switch (op1) {
2059              case 0:
2060                switch (crm) {
2061                  case 2:
2062                    switch (op2) {
2063                      case 0:
2064                        return MISCREG_MAIR_EL1;
2065                    }
2066                    break;
2067                  case 3:
2068                    switch (op2) {
2069                      case 0:
2070                        return MISCREG_AMAIR_EL1;
2071                    }
2072                    break;
2073                }
2074                break;
2075              case 4:
2076                switch (crm) {
2077                  case 2:
2078                    switch (op2) {
2079                      case 0:
2080                        return MISCREG_MAIR_EL2;
2081                    }
2082                    break;
2083                  case 3:
2084                    switch (op2) {
2085                      case 0:
2086                        return MISCREG_AMAIR_EL2;
2087                    }
2088                    break;
2089                }
2090                break;
2091              case 6:
2092                switch (crm) {
2093                  case 2:
2094                    switch (op2) {
2095                      case 0:
2096                        return MISCREG_MAIR_EL3;
2097                    }
2098                    break;
2099                  case 3:
2100                    switch (op2) {
2101                      case 0:
2102                        return MISCREG_AMAIR_EL3;
2103                    }
2104                    break;
2105                }
2106                break;
2107            }
2108            break;
2109          case 11:
2110            switch (op1) {
2111              case 1:
2112                switch (crm) {
2113                  case 0:
2114                    switch (op2) {
2115                      case 2:
2116                        return MISCREG_L2CTLR_EL1;
2117                      case 3:
2118                        return MISCREG_L2ECTLR_EL1;
2119                    }
2120                    break;
2121                }
2122                M5_FALLTHROUGH;
2123              default:
2124                // S3_<op1>_11_<Cm>_<op2>
2125                return MISCREG_IMPDEF_UNIMPL;
2126            }
2127            M5_UNREACHABLE;
2128          case 12:
2129            switch (op1) {
2130              case 0:
2131                switch (crm) {
2132                  case 0:
2133                    switch (op2) {
2134                      case 0:
2135                        return MISCREG_VBAR_EL1;
2136                      case 1:
2137                        return MISCREG_RVBAR_EL1;
2138                    }
2139                    break;
2140                  case 1:
2141                    switch (op2) {
2142                      case 0:
2143                        return MISCREG_ISR_EL1;
2144                      case 1:
2145                        return MISCREG_DISR_EL1;
2146                    }
2147                    break;
2148                }
2149                break;
2150              case 4:
2151                switch (crm) {
2152                  case 0:
2153                    switch (op2) {
2154                      case 0:
2155                        return MISCREG_VBAR_EL2;
2156                      case 1:
2157                        return MISCREG_RVBAR_EL2;
2158                    }
2159                    break;
2160                  case 1:
2161                    switch (op2) {
2162                      case 1:
2163                        return MISCREG_VDISR_EL2;
2164                    }
2165                    break;
2166                }
2167                break;
2168              case 6:
2169                switch (crm) {
2170                  case 0:
2171                    switch (op2) {
2172                      case 0:
2173                        return MISCREG_VBAR_EL3;
2174                      case 1:
2175                        return MISCREG_RVBAR_EL3;
2176                      case 2:
2177                        return MISCREG_RMR_EL3;
2178                    }
2179                    break;
2180                }
2181                break;
2182            }
2183            break;
2184          case 13:
2185            switch (op1) {
2186              case 0:
2187                switch (crm) {
2188                  case 0:
2189                    switch (op2) {
2190                      case 1:
2191                        return MISCREG_CONTEXTIDR_EL1;
2192                      case 4:
2193                        return MISCREG_TPIDR_EL1;
2194                    }
2195                    break;
2196                }
2197                break;
2198              case 3:
2199                switch (crm) {
2200                  case 0:
2201                    switch (op2) {
2202                      case 2:
2203                        return MISCREG_TPIDR_EL0;
2204                      case 3:
2205                        return MISCREG_TPIDRRO_EL0;
2206                    }
2207                    break;
2208                }
2209                break;
2210              case 4:
2211                switch (crm) {
2212                  case 0:
2213                    switch (op2) {
2214                      case 1:
2215                        return MISCREG_CONTEXTIDR_EL2;
2216                      case 2:
2217                        return MISCREG_TPIDR_EL2;
2218                    }
2219                    break;
2220                }
2221                break;
2222              case 6:
2223                switch (crm) {
2224                  case 0:
2225                    switch (op2) {
2226                      case 2:
2227                        return MISCREG_TPIDR_EL3;
2228                    }
2229                    break;
2230                }
2231                break;
2232            }
2233            break;
2234          case 14:
2235            switch (op1) {
2236              case 0:
2237                switch (crm) {
2238                  case 1:
2239                    switch (op2) {
2240                      case 0:
2241                        return MISCREG_CNTKCTL_EL1;
2242                    }
2243                    break;
2244                }
2245                break;
2246              case 3:
2247                switch (crm) {
2248                  case 0:
2249                    switch (op2) {
2250                      case 0:
2251                        return MISCREG_CNTFRQ_EL0;
2252                      case 1:
2253                        return MISCREG_CNTPCT_EL0;
2254                      case 2:
2255                        return MISCREG_CNTVCT_EL0;
2256                    }
2257                    break;
2258                  case 2:
2259                    switch (op2) {
2260                      case 0:
2261                        return MISCREG_CNTP_TVAL_EL0;
2262                      case 1:
2263                        return MISCREG_CNTP_CTL_EL0;
2264                      case 2:
2265                        return MISCREG_CNTP_CVAL_EL0;
2266                    }
2267                    break;
2268                  case 3:
2269                    switch (op2) {
2270                      case 0:
2271                        return MISCREG_CNTV_TVAL_EL0;
2272                      case 1:
2273                        return MISCREG_CNTV_CTL_EL0;
2274                      case 2:
2275                        return MISCREG_CNTV_CVAL_EL0;
2276                    }
2277                    break;
2278                  case 8:
2279                    switch (op2) {
2280                      case 0:
2281                        return MISCREG_PMEVCNTR0_EL0;
2282                      case 1:
2283                        return MISCREG_PMEVCNTR1_EL0;
2284                      case 2:
2285                        return MISCREG_PMEVCNTR2_EL0;
2286                      case 3:
2287                        return MISCREG_PMEVCNTR3_EL0;
2288                      case 4:
2289                        return MISCREG_PMEVCNTR4_EL0;
2290                      case 5:
2291                        return MISCREG_PMEVCNTR5_EL0;
2292                    }
2293                    break;
2294                  case 12:
2295                    switch (op2) {
2296                      case 0:
2297                        return MISCREG_PMEVTYPER0_EL0;
2298                      case 1:
2299                        return MISCREG_PMEVTYPER1_EL0;
2300                      case 2:
2301                        return MISCREG_PMEVTYPER2_EL0;
2302                      case 3:
2303                        return MISCREG_PMEVTYPER3_EL0;
2304                      case 4:
2305                        return MISCREG_PMEVTYPER4_EL0;
2306                      case 5:
2307                        return MISCREG_PMEVTYPER5_EL0;
2308                    }
2309                    break;
2310                  case 15:
2311                    switch (op2) {
2312                      case 7:
2313                        return MISCREG_PMCCFILTR_EL0;
2314                    }
2315                }
2316                break;
2317              case 4:
2318                switch (crm) {
2319                  case 0:
2320                    switch (op2) {
2321                      case 3:
2322                        return MISCREG_CNTVOFF_EL2;
2323                    }
2324                    break;
2325                  case 1:
2326                    switch (op2) {
2327                      case 0:
2328                        return MISCREG_CNTHCTL_EL2;
2329                    }
2330                    break;
2331                  case 2:
2332                    switch (op2) {
2333                      case 0:
2334                        return MISCREG_CNTHP_TVAL_EL2;
2335                      case 1:
2336                        return MISCREG_CNTHP_CTL_EL2;
2337                      case 2:
2338                        return MISCREG_CNTHP_CVAL_EL2;
2339                    }
2340                    break;
2341                  case 3:
2342                    switch (op2) {
2343                      case 0:
2344                        return MISCREG_CNTHV_TVAL_EL2;
2345                      case 1:
2346                        return MISCREG_CNTHV_CTL_EL2;
2347                      case 2:
2348                        return MISCREG_CNTHV_CVAL_EL2;
2349                    }
2350                    break;
2351                }
2352                break;
2353              case 7:
2354                switch (crm) {
2355                  case 2:
2356                    switch (op2) {
2357                      case 0:
2358                        return MISCREG_CNTPS_TVAL_EL1;
2359                      case 1:
2360                        return MISCREG_CNTPS_CTL_EL1;
2361                      case 2:
2362                        return MISCREG_CNTPS_CVAL_EL1;
2363                    }
2364                    break;
2365                }
2366                break;
2367            }
2368            break;
2369          case 15:
2370            switch (op1) {
2371              case 0:
2372                switch (crm) {
2373                  case 0:
2374                    switch (op2) {
2375                      case 0:
2376                        return MISCREG_IL1DATA0_EL1;
2377                      case 1:
2378                        return MISCREG_IL1DATA1_EL1;
2379                      case 2:
2380                        return MISCREG_IL1DATA2_EL1;
2381                      case 3:
2382                        return MISCREG_IL1DATA3_EL1;
2383                    }
2384                    break;
2385                  case 1:
2386                    switch (op2) {
2387                      case 0:
2388                        return MISCREG_DL1DATA0_EL1;
2389                      case 1:
2390                        return MISCREG_DL1DATA1_EL1;
2391                      case 2:
2392                        return MISCREG_DL1DATA2_EL1;
2393                      case 3:
2394                        return MISCREG_DL1DATA3_EL1;
2395                      case 4:
2396                        return MISCREG_DL1DATA4_EL1;
2397                    }
2398                    break;
2399                }
2400                break;
2401              case 1:
2402                switch (crm) {
2403                  case 0:
2404                    switch (op2) {
2405                      case 0:
2406                        return MISCREG_L2ACTLR_EL1;
2407                    }
2408                    break;
2409                  case 2:
2410                    switch (op2) {
2411                      case 0:
2412                        return MISCREG_CPUACTLR_EL1;
2413                      case 1:
2414                        return MISCREG_CPUECTLR_EL1;
2415                      case 2:
2416                        return MISCREG_CPUMERRSR_EL1;
2417                      case 3:
2418                        return MISCREG_L2MERRSR_EL1;
2419                    }
2420                    break;
2421                  case 3:
2422                    switch (op2) {
2423                      case 0:
2424                        return MISCREG_CBAR_EL1;
2425
2426                    }
2427                    break;
2428                }
2429                break;
2430            }
2431            // S3_<op1>_15_<Cm>_<op2>
2432            return MISCREG_IMPDEF_UNIMPL;
2433        }
2434        break;
2435    }
2436
2437    return MISCREG_UNKNOWN;
2438}
2439
2440bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2441
2442void
2443ISA::initializeMiscRegMetadata()
2444{
2445    // the MiscReg metadata tables are shared across all instances of the
2446    // ISA object, so there's no need to initialize them multiple times.
2447    static bool completed = false;
2448    if (completed)
2449        return;
2450
2451    // This boolean variable specifies if the system is running in aarch32 at
2452    // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2453    // is running in aarch64 (aarch32EL3 = false)
2454    bool aarch32EL3 = haveSecurity && !highestELIs64;
2455
2456    /**
2457     * Some registers alias with others, and therefore need to be translated.
2458     * When two mapping registers are given, they are the 32b lower and
2459     * upper halves, respectively, of the 64b register being mapped.
2460     * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2461     *
2462     * NAM = "not architecturally mandated",
2463     * from ARM DDI 0487A.i, template text
2464     * "AArch64 System register ___ can be mapped to
2465     *  AArch32 System register ___, but this is not
2466     *  architecturally mandated."
2467     */
2468
2469    InitReg(MISCREG_CPSR)
2470      .allPrivileges();
2471    InitReg(MISCREG_SPSR)
2472      .allPrivileges();
2473    InitReg(MISCREG_SPSR_FIQ)
2474      .allPrivileges();
2475    InitReg(MISCREG_SPSR_IRQ)
2476      .allPrivileges();
2477    InitReg(MISCREG_SPSR_SVC)
2478      .allPrivileges();
2479    InitReg(MISCREG_SPSR_MON)
2480      .allPrivileges();
2481    InitReg(MISCREG_SPSR_ABT)
2482      .allPrivileges();
2483    InitReg(MISCREG_SPSR_HYP)
2484      .allPrivileges();
2485    InitReg(MISCREG_SPSR_UND)
2486      .allPrivileges();
2487    InitReg(MISCREG_ELR_HYP)
2488      .allPrivileges();
2489    InitReg(MISCREG_FPSID)
2490      .allPrivileges();
2491    InitReg(MISCREG_FPSCR)
2492      .allPrivileges();
2493    InitReg(MISCREG_MVFR1)
2494      .allPrivileges();
2495    InitReg(MISCREG_MVFR0)
2496      .allPrivileges();
2497    InitReg(MISCREG_FPEXC)
2498      .allPrivileges();
2499
2500    // Helper registers
2501    InitReg(MISCREG_CPSR_MODE)
2502      .allPrivileges();
2503    InitReg(MISCREG_CPSR_Q)
2504      .allPrivileges();
2505    InitReg(MISCREG_FPSCR_EXC)
2506      .allPrivileges();
2507    InitReg(MISCREG_FPSCR_QC)
2508      .allPrivileges();
2509    InitReg(MISCREG_LOCKADDR)
2510      .allPrivileges();
2511    InitReg(MISCREG_LOCKFLAG)
2512      .allPrivileges();
2513    InitReg(MISCREG_PRRR_MAIR0)
2514      .mutex()
2515      .banked();
2516    InitReg(MISCREG_PRRR_MAIR0_NS)
2517      .mutex()
2518      .privSecure(!aarch32EL3)
2519      .bankedChild();
2520    InitReg(MISCREG_PRRR_MAIR0_S)
2521      .mutex()
2522      .bankedChild();
2523    InitReg(MISCREG_NMRR_MAIR1)
2524      .mutex()
2525      .banked();
2526    InitReg(MISCREG_NMRR_MAIR1_NS)
2527      .mutex()
2528      .privSecure(!aarch32EL3)
2529      .bankedChild();
2530    InitReg(MISCREG_NMRR_MAIR1_S)
2531      .mutex()
2532      .bankedChild();
2533    InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2534      .mutex();
2535    InitReg(MISCREG_SCTLR_RST)
2536      .allPrivileges();
2537    InitReg(MISCREG_SEV_MAILBOX)
2538      .allPrivileges();
2539
2540    // AArch32 CP14 registers
2541    InitReg(MISCREG_DBGDIDR)
2542      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2543    InitReg(MISCREG_DBGDSCRint)
2544      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2545    InitReg(MISCREG_DBGDCCINT)
2546      .unimplemented()
2547      .allPrivileges();
2548    InitReg(MISCREG_DBGDTRTXint)
2549      .unimplemented()
2550      .allPrivileges();
2551    InitReg(MISCREG_DBGDTRRXint)
2552      .unimplemented()
2553      .allPrivileges();
2554    InitReg(MISCREG_DBGWFAR)
2555      .unimplemented()
2556      .allPrivileges();
2557    InitReg(MISCREG_DBGVCR)
2558      .unimplemented()
2559      .allPrivileges();
2560    InitReg(MISCREG_DBGDTRRXext)
2561      .unimplemented()
2562      .allPrivileges();
2563    InitReg(MISCREG_DBGDSCRext)
2564      .unimplemented()
2565      .warnNotFail()
2566      .allPrivileges();
2567    InitReg(MISCREG_DBGDTRTXext)
2568      .unimplemented()
2569      .allPrivileges();
2570    InitReg(MISCREG_DBGOSECCR)
2571      .unimplemented()
2572      .allPrivileges();
2573    InitReg(MISCREG_DBGBVR0)
2574      .unimplemented()
2575      .allPrivileges();
2576    InitReg(MISCREG_DBGBVR1)
2577      .unimplemented()
2578      .allPrivileges();
2579    InitReg(MISCREG_DBGBVR2)
2580      .unimplemented()
2581      .allPrivileges();
2582    InitReg(MISCREG_DBGBVR3)
2583      .unimplemented()
2584      .allPrivileges();
2585    InitReg(MISCREG_DBGBVR4)
2586      .unimplemented()
2587      .allPrivileges();
2588    InitReg(MISCREG_DBGBVR5)
2589      .unimplemented()
2590      .allPrivileges();
2591    InitReg(MISCREG_DBGBCR0)
2592      .unimplemented()
2593      .allPrivileges();
2594    InitReg(MISCREG_DBGBCR1)
2595      .unimplemented()
2596      .allPrivileges();
2597    InitReg(MISCREG_DBGBCR2)
2598      .unimplemented()
2599      .allPrivileges();
2600    InitReg(MISCREG_DBGBCR3)
2601      .unimplemented()
2602      .allPrivileges();
2603    InitReg(MISCREG_DBGBCR4)
2604      .unimplemented()
2605      .allPrivileges();
2606    InitReg(MISCREG_DBGBCR5)
2607      .unimplemented()
2608      .allPrivileges();
2609    InitReg(MISCREG_DBGWVR0)
2610      .unimplemented()
2611      .allPrivileges();
2612    InitReg(MISCREG_DBGWVR1)
2613      .unimplemented()
2614      .allPrivileges();
2615    InitReg(MISCREG_DBGWVR2)
2616      .unimplemented()
2617      .allPrivileges();
2618    InitReg(MISCREG_DBGWVR3)
2619      .unimplemented()
2620      .allPrivileges();
2621    InitReg(MISCREG_DBGWCR0)
2622      .unimplemented()
2623      .allPrivileges();
2624    InitReg(MISCREG_DBGWCR1)
2625      .unimplemented()
2626      .allPrivileges();
2627    InitReg(MISCREG_DBGWCR2)
2628      .unimplemented()
2629      .allPrivileges();
2630    InitReg(MISCREG_DBGWCR3)
2631      .unimplemented()
2632      .allPrivileges();
2633    InitReg(MISCREG_DBGDRAR)
2634      .unimplemented()
2635      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2636    InitReg(MISCREG_DBGBXVR4)
2637      .unimplemented()
2638      .allPrivileges();
2639    InitReg(MISCREG_DBGBXVR5)
2640      .unimplemented()
2641      .allPrivileges();
2642    InitReg(MISCREG_DBGOSLAR)
2643      .unimplemented()
2644      .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2645    InitReg(MISCREG_DBGOSLSR)
2646      .unimplemented()
2647      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2648    InitReg(MISCREG_DBGOSDLR)
2649      .unimplemented()
2650      .allPrivileges();
2651    InitReg(MISCREG_DBGPRCR)
2652      .unimplemented()
2653      .allPrivileges();
2654    InitReg(MISCREG_DBGDSAR)
2655      .unimplemented()
2656      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2657    InitReg(MISCREG_DBGCLAIMSET)
2658      .unimplemented()
2659      .allPrivileges();
2660    InitReg(MISCREG_DBGCLAIMCLR)
2661      .unimplemented()
2662      .allPrivileges();
2663    InitReg(MISCREG_DBGAUTHSTATUS)
2664      .unimplemented()
2665      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2666    InitReg(MISCREG_DBGDEVID2)
2667      .unimplemented()
2668      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2669    InitReg(MISCREG_DBGDEVID1)
2670      .unimplemented()
2671      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2672    InitReg(MISCREG_DBGDEVID0)
2673      .unimplemented()
2674      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2675    InitReg(MISCREG_TEECR)
2676      .unimplemented()
2677      .allPrivileges();
2678    InitReg(MISCREG_JIDR)
2679      .allPrivileges();
2680    InitReg(MISCREG_TEEHBR)
2681      .allPrivileges();
2682    InitReg(MISCREG_JOSCR)
2683      .allPrivileges();
2684    InitReg(MISCREG_JMCR)
2685      .allPrivileges();
2686
2687    // AArch32 CP15 registers
2688    InitReg(MISCREG_MIDR)
2689      .allPrivileges().exceptUserMode().writes(0);
2690    InitReg(MISCREG_CTR)
2691      .allPrivileges().exceptUserMode().writes(0);
2692    InitReg(MISCREG_TCMTR)
2693      .allPrivileges().exceptUserMode().writes(0);
2694    InitReg(MISCREG_TLBTR)
2695      .allPrivileges().exceptUserMode().writes(0);
2696    InitReg(MISCREG_MPIDR)
2697      .allPrivileges().exceptUserMode().writes(0);
2698    InitReg(MISCREG_REVIDR)
2699      .unimplemented()
2700      .warnNotFail()
2701      .allPrivileges().exceptUserMode().writes(0);
2702    InitReg(MISCREG_ID_PFR0)
2703      .allPrivileges().exceptUserMode().writes(0);
2704    InitReg(MISCREG_ID_PFR1)
2705      .allPrivileges().exceptUserMode().writes(0);
2706    InitReg(MISCREG_ID_DFR0)
2707      .allPrivileges().exceptUserMode().writes(0);
2708    InitReg(MISCREG_ID_AFR0)
2709      .allPrivileges().exceptUserMode().writes(0);
2710    InitReg(MISCREG_ID_MMFR0)
2711      .allPrivileges().exceptUserMode().writes(0);
2712    InitReg(MISCREG_ID_MMFR1)
2713      .allPrivileges().exceptUserMode().writes(0);
2714    InitReg(MISCREG_ID_MMFR2)
2715      .allPrivileges().exceptUserMode().writes(0);
2716    InitReg(MISCREG_ID_MMFR3)
2717      .allPrivileges().exceptUserMode().writes(0);
2718    InitReg(MISCREG_ID_ISAR0)
2719      .allPrivileges().exceptUserMode().writes(0);
2720    InitReg(MISCREG_ID_ISAR1)
2721      .allPrivileges().exceptUserMode().writes(0);
2722    InitReg(MISCREG_ID_ISAR2)
2723      .allPrivileges().exceptUserMode().writes(0);
2724    InitReg(MISCREG_ID_ISAR3)
2725      .allPrivileges().exceptUserMode().writes(0);
2726    InitReg(MISCREG_ID_ISAR4)
2727      .allPrivileges().exceptUserMode().writes(0);
2728    InitReg(MISCREG_ID_ISAR5)
2729      .allPrivileges().exceptUserMode().writes(0);
2730    InitReg(MISCREG_CCSIDR)
2731      .allPrivileges().exceptUserMode().writes(0);
2732    InitReg(MISCREG_CLIDR)
2733      .allPrivileges().exceptUserMode().writes(0);
2734    InitReg(MISCREG_AIDR)
2735      .allPrivileges().exceptUserMode().writes(0);
2736    InitReg(MISCREG_CSSELR)
2737      .banked();
2738    InitReg(MISCREG_CSSELR_NS)
2739      .bankedChild()
2740      .privSecure(!aarch32EL3)
2741      .nonSecure().exceptUserMode();
2742    InitReg(MISCREG_CSSELR_S)
2743      .bankedChild()
2744      .secure().exceptUserMode();
2745    InitReg(MISCREG_VPIDR)
2746      .hyp().monNonSecure();
2747    InitReg(MISCREG_VMPIDR)
2748      .hyp().monNonSecure();
2749    InitReg(MISCREG_SCTLR)
2750      .banked();
2751    InitReg(MISCREG_SCTLR_NS)
2752      .bankedChild()
2753      .privSecure(!aarch32EL3)
2754      .nonSecure().exceptUserMode();
2755    InitReg(MISCREG_SCTLR_S)
2756      .bankedChild()
2757      .secure().exceptUserMode();
2758    InitReg(MISCREG_ACTLR)
2759      .banked();
2760    InitReg(MISCREG_ACTLR_NS)
2761      .bankedChild()
2762      .privSecure(!aarch32EL3)
2763      .nonSecure().exceptUserMode();
2764    InitReg(MISCREG_ACTLR_S)
2765      .bankedChild()
2766      .secure().exceptUserMode();
2767    InitReg(MISCREG_CPACR)
2768      .allPrivileges().exceptUserMode();
2769    InitReg(MISCREG_SCR)
2770      .mon().secure().exceptUserMode()
2771      .res0(0xff40)  // [31:16], [6]
2772      .res1(0x0030); // [5:4]
2773    InitReg(MISCREG_SDER)
2774      .mon();
2775    InitReg(MISCREG_NSACR)
2776      .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2777    InitReg(MISCREG_HSCTLR)
2778      .hyp().monNonSecure();
2779    InitReg(MISCREG_HACTLR)
2780      .hyp().monNonSecure();
2781    InitReg(MISCREG_HCR)
2782      .hyp().monNonSecure();
2783    InitReg(MISCREG_HDCR)
2784      .hyp().monNonSecure();
2785    InitReg(MISCREG_HCPTR)
2786      .hyp().monNonSecure();
2787    InitReg(MISCREG_HSTR)
2788      .hyp().monNonSecure();
2789    InitReg(MISCREG_HACR)
2790      .unimplemented()
2791      .warnNotFail()
2792      .hyp().monNonSecure();
2793    InitReg(MISCREG_TTBR0)
2794      .banked();
2795    InitReg(MISCREG_TTBR0_NS)
2796      .bankedChild()
2797      .privSecure(!aarch32EL3)
2798      .nonSecure().exceptUserMode();
2799    InitReg(MISCREG_TTBR0_S)
2800      .bankedChild()
2801      .secure().exceptUserMode();
2802    InitReg(MISCREG_TTBR1)
2803      .banked();
2804    InitReg(MISCREG_TTBR1_NS)
2805      .bankedChild()
2806      .privSecure(!aarch32EL3)
2807      .nonSecure().exceptUserMode();
2808    InitReg(MISCREG_TTBR1_S)
2809      .bankedChild()
2810      .secure().exceptUserMode();
2811    InitReg(MISCREG_TTBCR)
2812      .banked();
2813    InitReg(MISCREG_TTBCR_NS)
2814      .bankedChild()
2815      .privSecure(!aarch32EL3)
2816      .nonSecure().exceptUserMode();
2817    InitReg(MISCREG_TTBCR_S)
2818      .bankedChild()
2819      .secure().exceptUserMode();
2820    InitReg(MISCREG_HTCR)
2821      .hyp().monNonSecure();
2822    InitReg(MISCREG_VTCR)
2823      .hyp().monNonSecure();
2824    InitReg(MISCREG_DACR)
2825      .banked();
2826    InitReg(MISCREG_DACR_NS)
2827      .bankedChild()
2828      .privSecure(!aarch32EL3)
2829      .nonSecure().exceptUserMode();
2830    InitReg(MISCREG_DACR_S)
2831      .bankedChild()
2832      .secure().exceptUserMode();
2833    InitReg(MISCREG_DFSR)
2834      .banked();
2835    InitReg(MISCREG_DFSR_NS)
2836      .bankedChild()
2837      .privSecure(!aarch32EL3)
2838      .nonSecure().exceptUserMode();
2839    InitReg(MISCREG_DFSR_S)
2840      .bankedChild()
2841      .secure().exceptUserMode();
2842    InitReg(MISCREG_IFSR)
2843      .banked();
2844    InitReg(MISCREG_IFSR_NS)
2845      .bankedChild()
2846      .privSecure(!aarch32EL3)
2847      .nonSecure().exceptUserMode();
2848    InitReg(MISCREG_IFSR_S)
2849      .bankedChild()
2850      .secure().exceptUserMode();
2851    InitReg(MISCREG_ADFSR)
2852      .unimplemented()
2853      .warnNotFail()
2854      .banked();
2855    InitReg(MISCREG_ADFSR_NS)
2856      .unimplemented()
2857      .warnNotFail()
2858      .bankedChild()
2859      .privSecure(!aarch32EL3)
2860      .nonSecure().exceptUserMode();
2861    InitReg(MISCREG_ADFSR_S)
2862      .unimplemented()
2863      .warnNotFail()
2864      .bankedChild()
2865      .secure().exceptUserMode();
2866    InitReg(MISCREG_AIFSR)
2867      .unimplemented()
2868      .warnNotFail()
2869      .banked();
2870    InitReg(MISCREG_AIFSR_NS)
2871      .unimplemented()
2872      .warnNotFail()
2873      .bankedChild()
2874      .privSecure(!aarch32EL3)
2875      .nonSecure().exceptUserMode();
2876    InitReg(MISCREG_AIFSR_S)
2877      .unimplemented()
2878      .warnNotFail()
2879      .bankedChild()
2880      .secure().exceptUserMode();
2881    InitReg(MISCREG_HADFSR)
2882      .hyp().monNonSecure();
2883    InitReg(MISCREG_HAIFSR)
2884      .hyp().monNonSecure();
2885    InitReg(MISCREG_HSR)
2886      .hyp().monNonSecure();
2887    InitReg(MISCREG_DFAR)
2888      .banked();
2889    InitReg(MISCREG_DFAR_NS)
2890      .bankedChild()
2891      .privSecure(!aarch32EL3)
2892      .nonSecure().exceptUserMode();
2893    InitReg(MISCREG_DFAR_S)
2894      .bankedChild()
2895      .secure().exceptUserMode();
2896    InitReg(MISCREG_IFAR)
2897      .banked();
2898    InitReg(MISCREG_IFAR_NS)
2899      .bankedChild()
2900      .privSecure(!aarch32EL3)
2901      .nonSecure().exceptUserMode();
2902    InitReg(MISCREG_IFAR_S)
2903      .bankedChild()
2904      .secure().exceptUserMode();
2905    InitReg(MISCREG_HDFAR)
2906      .hyp().monNonSecure();
2907    InitReg(MISCREG_HIFAR)
2908      .hyp().monNonSecure();
2909    InitReg(MISCREG_HPFAR)
2910      .hyp().monNonSecure();
2911    InitReg(MISCREG_ICIALLUIS)
2912      .unimplemented()
2913      .warnNotFail()
2914      .writes(1).exceptUserMode();
2915    InitReg(MISCREG_BPIALLIS)
2916      .unimplemented()
2917      .warnNotFail()
2918      .writes(1).exceptUserMode();
2919    InitReg(MISCREG_PAR)
2920      .banked();
2921    InitReg(MISCREG_PAR_NS)
2922      .bankedChild()
2923      .privSecure(!aarch32EL3)
2924      .nonSecure().exceptUserMode();
2925    InitReg(MISCREG_PAR_S)
2926      .bankedChild()
2927      .secure().exceptUserMode();
2928    InitReg(MISCREG_ICIALLU)
2929      .writes(1).exceptUserMode();
2930    InitReg(MISCREG_ICIMVAU)
2931      .unimplemented()
2932      .warnNotFail()
2933      .writes(1).exceptUserMode();
2934    InitReg(MISCREG_CP15ISB)
2935      .writes(1);
2936    InitReg(MISCREG_BPIALL)
2937      .unimplemented()
2938      .warnNotFail()
2939      .writes(1).exceptUserMode();
2940    InitReg(MISCREG_BPIMVA)
2941      .unimplemented()
2942      .warnNotFail()
2943      .writes(1).exceptUserMode();
2944    InitReg(MISCREG_DCIMVAC)
2945      .unimplemented()
2946      .warnNotFail()
2947      .writes(1).exceptUserMode();
2948    InitReg(MISCREG_DCISW)
2949      .unimplemented()
2950      .warnNotFail()
2951      .writes(1).exceptUserMode();
2952    InitReg(MISCREG_ATS1CPR)
2953      .writes(1).exceptUserMode();
2954    InitReg(MISCREG_ATS1CPW)
2955      .writes(1).exceptUserMode();
2956    InitReg(MISCREG_ATS1CUR)
2957      .writes(1).exceptUserMode();
2958    InitReg(MISCREG_ATS1CUW)
2959      .writes(1).exceptUserMode();
2960    InitReg(MISCREG_ATS12NSOPR)
2961      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2962    InitReg(MISCREG_ATS12NSOPW)
2963      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2964    InitReg(MISCREG_ATS12NSOUR)
2965      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2966    InitReg(MISCREG_ATS12NSOUW)
2967      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2968    InitReg(MISCREG_DCCMVAC)
2969      .writes(1).exceptUserMode();
2970    InitReg(MISCREG_DCCSW)
2971      .unimplemented()
2972      .warnNotFail()
2973      .writes(1).exceptUserMode();
2974    InitReg(MISCREG_CP15DSB)
2975      .writes(1);
2976    InitReg(MISCREG_CP15DMB)
2977      .writes(1);
2978    InitReg(MISCREG_DCCMVAU)
2979      .unimplemented()
2980      .warnNotFail()
2981      .writes(1).exceptUserMode();
2982    InitReg(MISCREG_DCCIMVAC)
2983      .unimplemented()
2984      .warnNotFail()
2985      .writes(1).exceptUserMode();
2986    InitReg(MISCREG_DCCISW)
2987      .unimplemented()
2988      .warnNotFail()
2989      .writes(1).exceptUserMode();
2990    InitReg(MISCREG_ATS1HR)
2991      .monNonSecureWrite().hypWrite();
2992    InitReg(MISCREG_ATS1HW)
2993      .monNonSecureWrite().hypWrite();
2994    InitReg(MISCREG_TLBIALLIS)
2995      .writes(1).exceptUserMode();
2996    InitReg(MISCREG_TLBIMVAIS)
2997      .writes(1).exceptUserMode();
2998    InitReg(MISCREG_TLBIASIDIS)
2999      .writes(1).exceptUserMode();
3000    InitReg(MISCREG_TLBIMVAAIS)
3001      .writes(1).exceptUserMode();
3002    InitReg(MISCREG_TLBIMVALIS)
3003      .writes(1).exceptUserMode();
3004    InitReg(MISCREG_TLBIMVAALIS)
3005      .writes(1).exceptUserMode();
3006    InitReg(MISCREG_ITLBIALL)
3007      .writes(1).exceptUserMode();
3008    InitReg(MISCREG_ITLBIMVA)
3009      .writes(1).exceptUserMode();
3010    InitReg(MISCREG_ITLBIASID)
3011      .writes(1).exceptUserMode();
3012    InitReg(MISCREG_DTLBIALL)
3013      .writes(1).exceptUserMode();
3014    InitReg(MISCREG_DTLBIMVA)
3015      .writes(1).exceptUserMode();
3016    InitReg(MISCREG_DTLBIASID)
3017      .writes(1).exceptUserMode();
3018    InitReg(MISCREG_TLBIALL)
3019      .writes(1).exceptUserMode();
3020    InitReg(MISCREG_TLBIMVA)
3021      .writes(1).exceptUserMode();
3022    InitReg(MISCREG_TLBIASID)
3023      .writes(1).exceptUserMode();
3024    InitReg(MISCREG_TLBIMVAA)
3025      .writes(1).exceptUserMode();
3026    InitReg(MISCREG_TLBIMVAL)
3027      .writes(1).exceptUserMode();
3028    InitReg(MISCREG_TLBIMVAAL)
3029      .writes(1).exceptUserMode();
3030    InitReg(MISCREG_TLBIIPAS2IS)
3031      .monNonSecureWrite().hypWrite();
3032    InitReg(MISCREG_TLBIIPAS2LIS)
3033      .monNonSecureWrite().hypWrite();
3034    InitReg(MISCREG_TLBIALLHIS)
3035      .monNonSecureWrite().hypWrite();
3036    InitReg(MISCREG_TLBIMVAHIS)
3037      .monNonSecureWrite().hypWrite();
3038    InitReg(MISCREG_TLBIALLNSNHIS)
3039      .monNonSecureWrite().hypWrite();
3040    InitReg(MISCREG_TLBIMVALHIS)
3041      .monNonSecureWrite().hypWrite();
3042    InitReg(MISCREG_TLBIIPAS2)
3043      .monNonSecureWrite().hypWrite();
3044    InitReg(MISCREG_TLBIIPAS2L)
3045      .monNonSecureWrite().hypWrite();
3046    InitReg(MISCREG_TLBIALLH)
3047      .monNonSecureWrite().hypWrite();
3048    InitReg(MISCREG_TLBIMVAH)
3049      .monNonSecureWrite().hypWrite();
3050    InitReg(MISCREG_TLBIALLNSNH)
3051      .monNonSecureWrite().hypWrite();
3052    InitReg(MISCREG_TLBIMVALH)
3053      .monNonSecureWrite().hypWrite();
3054    InitReg(MISCREG_PMCR)
3055      .allPrivileges();
3056    InitReg(MISCREG_PMCNTENSET)
3057      .allPrivileges();
3058    InitReg(MISCREG_PMCNTENCLR)
3059      .allPrivileges();
3060    InitReg(MISCREG_PMOVSR)
3061      .allPrivileges();
3062    InitReg(MISCREG_PMSWINC)
3063      .allPrivileges();
3064    InitReg(MISCREG_PMSELR)
3065      .allPrivileges();
3066    InitReg(MISCREG_PMCEID0)
3067      .allPrivileges();
3068    InitReg(MISCREG_PMCEID1)
3069      .allPrivileges();
3070    InitReg(MISCREG_PMCCNTR)
3071      .allPrivileges();
3072    InitReg(MISCREG_PMXEVTYPER)
3073      .allPrivileges();
3074    InitReg(MISCREG_PMCCFILTR)
3075      .allPrivileges();
3076    InitReg(MISCREG_PMXEVCNTR)
3077      .allPrivileges();
3078    InitReg(MISCREG_PMUSERENR)
3079      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3080    InitReg(MISCREG_PMINTENSET)
3081      .allPrivileges().exceptUserMode();
3082    InitReg(MISCREG_PMINTENCLR)
3083      .allPrivileges().exceptUserMode();
3084    InitReg(MISCREG_PMOVSSET)
3085      .unimplemented()
3086      .allPrivileges();
3087    InitReg(MISCREG_L2CTLR)
3088      .allPrivileges().exceptUserMode();
3089    InitReg(MISCREG_L2ECTLR)
3090      .unimplemented()
3091      .allPrivileges().exceptUserMode();
3092    InitReg(MISCREG_PRRR)
3093      .banked();
3094    InitReg(MISCREG_PRRR_NS)
3095      .bankedChild()
3096      .privSecure(!aarch32EL3)
3097      .nonSecure().exceptUserMode();
3098    InitReg(MISCREG_PRRR_S)
3099      .bankedChild()
3100      .secure().exceptUserMode();
3101    InitReg(MISCREG_MAIR0)
3102      .banked();
3103    InitReg(MISCREG_MAIR0_NS)
3104      .bankedChild()
3105      .privSecure(!aarch32EL3)
3106      .nonSecure().exceptUserMode();
3107    InitReg(MISCREG_MAIR0_S)
3108      .bankedChild()
3109      .secure().exceptUserMode();
3110    InitReg(MISCREG_NMRR)
3111      .banked();
3112    InitReg(MISCREG_NMRR_NS)
3113      .bankedChild()
3114      .privSecure(!aarch32EL3)
3115      .nonSecure().exceptUserMode();
3116    InitReg(MISCREG_NMRR_S)
3117      .bankedChild()
3118      .secure().exceptUserMode();
3119    InitReg(MISCREG_MAIR1)
3120      .banked();
3121    InitReg(MISCREG_MAIR1_NS)
3122      .bankedChild()
3123      .privSecure(!aarch32EL3)
3124      .nonSecure().exceptUserMode();
3125    InitReg(MISCREG_MAIR1_S)
3126      .bankedChild()
3127      .secure().exceptUserMode();
3128    InitReg(MISCREG_AMAIR0)
3129      .banked();
3130    InitReg(MISCREG_AMAIR0_NS)
3131      .bankedChild()
3132      .privSecure(!aarch32EL3)
3133      .nonSecure().exceptUserMode();
3134    InitReg(MISCREG_AMAIR0_S)
3135      .bankedChild()
3136      .secure().exceptUserMode();
3137    InitReg(MISCREG_AMAIR1)
3138      .banked();
3139    InitReg(MISCREG_AMAIR1_NS)
3140      .bankedChild()
3141      .privSecure(!aarch32EL3)
3142      .nonSecure().exceptUserMode();
3143    InitReg(MISCREG_AMAIR1_S)
3144      .bankedChild()
3145      .secure().exceptUserMode();
3146    InitReg(MISCREG_HMAIR0)
3147      .hyp().monNonSecure();
3148    InitReg(MISCREG_HMAIR1)
3149      .hyp().monNonSecure();
3150    InitReg(MISCREG_HAMAIR0)
3151      .unimplemented()
3152      .warnNotFail()
3153      .hyp().monNonSecure();
3154    InitReg(MISCREG_HAMAIR1)
3155      .unimplemented()
3156      .warnNotFail()
3157      .hyp().monNonSecure();
3158    InitReg(MISCREG_VBAR)
3159      .banked();
3160    InitReg(MISCREG_VBAR_NS)
3161      .bankedChild()
3162      .privSecure(!aarch32EL3)
3163      .nonSecure().exceptUserMode();
3164    InitReg(MISCREG_VBAR_S)
3165      .bankedChild()
3166      .secure().exceptUserMode();
3167    InitReg(MISCREG_MVBAR)
3168      .mon().secure().exceptUserMode();
3169    InitReg(MISCREG_RMR)
3170      .unimplemented()
3171      .mon().secure().exceptUserMode();
3172    InitReg(MISCREG_ISR)
3173      .allPrivileges().exceptUserMode().writes(0);
3174    InitReg(MISCREG_HVBAR)
3175      .hyp().monNonSecure();
3176    InitReg(MISCREG_FCSEIDR)
3177      .unimplemented()
3178      .warnNotFail()
3179      .allPrivileges().exceptUserMode();
3180    InitReg(MISCREG_CONTEXTIDR)
3181      .banked();
3182    InitReg(MISCREG_CONTEXTIDR_NS)
3183      .bankedChild()
3184      .privSecure(!aarch32EL3)
3185      .nonSecure().exceptUserMode();
3186    InitReg(MISCREG_CONTEXTIDR_S)
3187      .bankedChild()
3188      .secure().exceptUserMode();
3189    InitReg(MISCREG_TPIDRURW)
3190      .banked();
3191    InitReg(MISCREG_TPIDRURW_NS)
3192      .bankedChild()
3193      .allPrivileges()
3194      .privSecure(!aarch32EL3)
3195      .monSecure(0);
3196    InitReg(MISCREG_TPIDRURW_S)
3197      .bankedChild()
3198      .secure();
3199    InitReg(MISCREG_TPIDRURO)
3200      .banked();
3201    InitReg(MISCREG_TPIDRURO_NS)
3202      .bankedChild()
3203      .allPrivileges()
3204      .userNonSecureWrite(0).userSecureRead(1)
3205      .privSecure(!aarch32EL3)
3206      .monSecure(0);
3207    InitReg(MISCREG_TPIDRURO_S)
3208      .bankedChild()
3209      .secure().userSecureWrite(0);
3210    InitReg(MISCREG_TPIDRPRW)
3211      .banked();
3212    InitReg(MISCREG_TPIDRPRW_NS)
3213      .bankedChild()
3214      .nonSecure().exceptUserMode()
3215      .privSecure(!aarch32EL3);
3216    InitReg(MISCREG_TPIDRPRW_S)
3217      .bankedChild()
3218      .secure().exceptUserMode();
3219    InitReg(MISCREG_HTPIDR)
3220      .hyp().monNonSecure();
3221    InitReg(MISCREG_CNTFRQ)
3222      .unverifiable()
3223      .reads(1).mon();
3224    InitReg(MISCREG_CNTKCTL)
3225      .allPrivileges().exceptUserMode();
3226    InitReg(MISCREG_CNTP_TVAL)
3227      .banked();
3228    InitReg(MISCREG_CNTP_TVAL_NS)
3229      .bankedChild()
3230      .allPrivileges()
3231      .privSecure(!aarch32EL3)
3232      .monSecure(0);
3233    InitReg(MISCREG_CNTP_TVAL_S)
3234      .bankedChild()
3235      .secure().user(1);
3236    InitReg(MISCREG_CNTP_CTL)
3237      .banked();
3238    InitReg(MISCREG_CNTP_CTL_NS)
3239      .bankedChild()
3240      .allPrivileges()
3241      .privSecure(!aarch32EL3)
3242      .monSecure(0);
3243    InitReg(MISCREG_CNTP_CTL_S)
3244      .bankedChild()
3245      .secure().user(1);
3246    InitReg(MISCREG_CNTV_TVAL)
3247      .allPrivileges();
3248    InitReg(MISCREG_CNTV_CTL)
3249      .allPrivileges();
3250    InitReg(MISCREG_CNTHCTL)
3251      .hypWrite().monNonSecureRead();
3252    InitReg(MISCREG_CNTHP_TVAL)
3253      .hypWrite().monNonSecureRead();
3254    InitReg(MISCREG_CNTHP_CTL)
3255      .hypWrite().monNonSecureRead();
3256    InitReg(MISCREG_IL1DATA0)
3257      .unimplemented()
3258      .allPrivileges().exceptUserMode();
3259    InitReg(MISCREG_IL1DATA1)
3260      .unimplemented()
3261      .allPrivileges().exceptUserMode();
3262    InitReg(MISCREG_IL1DATA2)
3263      .unimplemented()
3264      .allPrivileges().exceptUserMode();
3265    InitReg(MISCREG_IL1DATA3)
3266      .unimplemented()
3267      .allPrivileges().exceptUserMode();
3268    InitReg(MISCREG_DL1DATA0)
3269      .unimplemented()
3270      .allPrivileges().exceptUserMode();
3271    InitReg(MISCREG_DL1DATA1)
3272      .unimplemented()
3273      .allPrivileges().exceptUserMode();
3274    InitReg(MISCREG_DL1DATA2)
3275      .unimplemented()
3276      .allPrivileges().exceptUserMode();
3277    InitReg(MISCREG_DL1DATA3)
3278      .unimplemented()
3279      .allPrivileges().exceptUserMode();
3280    InitReg(MISCREG_DL1DATA4)
3281      .unimplemented()
3282      .allPrivileges().exceptUserMode();
3283    InitReg(MISCREG_RAMINDEX)
3284      .unimplemented()
3285      .writes(1).exceptUserMode();
3286    InitReg(MISCREG_L2ACTLR)
3287      .unimplemented()
3288      .allPrivileges().exceptUserMode();
3289    InitReg(MISCREG_CBAR)
3290      .unimplemented()
3291      .allPrivileges().exceptUserMode().writes(0);
3292    InitReg(MISCREG_HTTBR)
3293      .hyp().monNonSecure();
3294    InitReg(MISCREG_VTTBR)
3295      .hyp().monNonSecure();
3296    InitReg(MISCREG_CNTPCT)
3297      .reads(1);
3298    InitReg(MISCREG_CNTVCT)
3299      .unverifiable()
3300      .reads(1);
3301    InitReg(MISCREG_CNTP_CVAL)
3302      .banked();
3303    InitReg(MISCREG_CNTP_CVAL_NS)
3304      .bankedChild()
3305      .allPrivileges()
3306      .privSecure(!aarch32EL3)
3307      .monSecure(0);
3308    InitReg(MISCREG_CNTP_CVAL_S)
3309      .bankedChild()
3310      .secure().user(1);
3311    InitReg(MISCREG_CNTV_CVAL)
3312      .allPrivileges();
3313    InitReg(MISCREG_CNTVOFF)
3314      .hyp().monNonSecure();
3315    InitReg(MISCREG_CNTHP_CVAL)
3316      .hypWrite().monNonSecureRead();
3317    InitReg(MISCREG_CPUMERRSR)
3318      .unimplemented()
3319      .allPrivileges().exceptUserMode();
3320    InitReg(MISCREG_L2MERRSR)
3321      .unimplemented()
3322      .warnNotFail()
3323      .allPrivileges().exceptUserMode();
3324
3325    // AArch64 registers (Op0=2);
3326    InitReg(MISCREG_MDCCINT_EL1)
3327      .allPrivileges();
3328    InitReg(MISCREG_OSDTRRX_EL1)
3329      .allPrivileges()
3330      .mapsTo(MISCREG_DBGDTRRXext);
3331    InitReg(MISCREG_MDSCR_EL1)
3332      .allPrivileges()
3333      .mapsTo(MISCREG_DBGDSCRext);
3334    InitReg(MISCREG_OSDTRTX_EL1)
3335      .allPrivileges()
3336      .mapsTo(MISCREG_DBGDTRTXext);
3337    InitReg(MISCREG_OSECCR_EL1)
3338      .allPrivileges()
3339      .mapsTo(MISCREG_DBGOSECCR);
3340    InitReg(MISCREG_DBGBVR0_EL1)
3341      .allPrivileges()
3342      .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3343    InitReg(MISCREG_DBGBVR1_EL1)
3344      .allPrivileges()
3345      .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3346    InitReg(MISCREG_DBGBVR2_EL1)
3347      .allPrivileges()
3348      .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3349    InitReg(MISCREG_DBGBVR3_EL1)
3350      .allPrivileges()
3351      .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3352    InitReg(MISCREG_DBGBVR4_EL1)
3353      .allPrivileges()
3354      .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3355    InitReg(MISCREG_DBGBVR5_EL1)
3356      .allPrivileges()
3357      .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3358    InitReg(MISCREG_DBGBCR0_EL1)
3359      .allPrivileges()
3360      .mapsTo(MISCREG_DBGBCR0);
3361    InitReg(MISCREG_DBGBCR1_EL1)
3362      .allPrivileges()
3363      .mapsTo(MISCREG_DBGBCR1);
3364    InitReg(MISCREG_DBGBCR2_EL1)
3365      .allPrivileges()
3366      .mapsTo(MISCREG_DBGBCR2);
3367    InitReg(MISCREG_DBGBCR3_EL1)
3368      .allPrivileges()
3369      .mapsTo(MISCREG_DBGBCR3);
3370    InitReg(MISCREG_DBGBCR4_EL1)
3371      .allPrivileges()
3372      .mapsTo(MISCREG_DBGBCR4);
3373    InitReg(MISCREG_DBGBCR5_EL1)
3374      .allPrivileges()
3375      .mapsTo(MISCREG_DBGBCR5);
3376    InitReg(MISCREG_DBGWVR0_EL1)
3377      .allPrivileges()
3378      .mapsTo(MISCREG_DBGWVR0);
3379    InitReg(MISCREG_DBGWVR1_EL1)
3380      .allPrivileges()
3381      .mapsTo(MISCREG_DBGWVR1);
3382    InitReg(MISCREG_DBGWVR2_EL1)
3383      .allPrivileges()
3384      .mapsTo(MISCREG_DBGWVR2);
3385    InitReg(MISCREG_DBGWVR3_EL1)
3386      .allPrivileges()
3387      .mapsTo(MISCREG_DBGWVR3);
3388    InitReg(MISCREG_DBGWCR0_EL1)
3389      .allPrivileges()
3390      .mapsTo(MISCREG_DBGWCR0);
3391    InitReg(MISCREG_DBGWCR1_EL1)
3392      .allPrivileges()
3393      .mapsTo(MISCREG_DBGWCR1);
3394    InitReg(MISCREG_DBGWCR2_EL1)
3395      .allPrivileges()
3396      .mapsTo(MISCREG_DBGWCR2);
3397    InitReg(MISCREG_DBGWCR3_EL1)
3398      .allPrivileges()
3399      .mapsTo(MISCREG_DBGWCR3);
3400    InitReg(MISCREG_MDCCSR_EL0)
3401      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3402      .mapsTo(MISCREG_DBGDSCRint);
3403    InitReg(MISCREG_MDDTR_EL0)
3404      .allPrivileges();
3405    InitReg(MISCREG_MDDTRTX_EL0)
3406      .allPrivileges();
3407    InitReg(MISCREG_MDDTRRX_EL0)
3408      .allPrivileges();
3409    InitReg(MISCREG_DBGVCR32_EL2)
3410      .allPrivileges()
3411      .mapsTo(MISCREG_DBGVCR);
3412    InitReg(MISCREG_MDRAR_EL1)
3413      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3414      .mapsTo(MISCREG_DBGDRAR);
3415    InitReg(MISCREG_OSLAR_EL1)
3416      .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3417      .mapsTo(MISCREG_DBGOSLAR);
3418    InitReg(MISCREG_OSLSR_EL1)
3419      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3420      .mapsTo(MISCREG_DBGOSLSR);
3421    InitReg(MISCREG_OSDLR_EL1)
3422      .allPrivileges()
3423      .mapsTo(MISCREG_DBGOSDLR);
3424    InitReg(MISCREG_DBGPRCR_EL1)
3425      .allPrivileges()
3426      .mapsTo(MISCREG_DBGPRCR);
3427    InitReg(MISCREG_DBGCLAIMSET_EL1)
3428      .allPrivileges()
3429      .mapsTo(MISCREG_DBGCLAIMSET);
3430    InitReg(MISCREG_DBGCLAIMCLR_EL1)
3431      .allPrivileges()
3432      .mapsTo(MISCREG_DBGCLAIMCLR);
3433    InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3434      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3435      .mapsTo(MISCREG_DBGAUTHSTATUS);
3436    InitReg(MISCREG_TEECR32_EL1);
3437    InitReg(MISCREG_TEEHBR32_EL1);
3438
3439    // AArch64 registers (Op0=1,3);
3440    InitReg(MISCREG_MIDR_EL1)
3441      .allPrivileges().exceptUserMode().writes(0);
3442    InitReg(MISCREG_MPIDR_EL1)
3443      .allPrivileges().exceptUserMode().writes(0);
3444    InitReg(MISCREG_REVIDR_EL1)
3445      .allPrivileges().exceptUserMode().writes(0);
3446    InitReg(MISCREG_ID_PFR0_EL1)
3447      .allPrivileges().exceptUserMode().writes(0)
3448      .mapsTo(MISCREG_ID_PFR0);
3449    InitReg(MISCREG_ID_PFR1_EL1)
3450      .allPrivileges().exceptUserMode().writes(0)
3451      .mapsTo(MISCREG_ID_PFR1);
3452    InitReg(MISCREG_ID_DFR0_EL1)
3453      .allPrivileges().exceptUserMode().writes(0)
3454      .mapsTo(MISCREG_ID_DFR0);
3455    InitReg(MISCREG_ID_AFR0_EL1)
3456      .allPrivileges().exceptUserMode().writes(0)
3457      .mapsTo(MISCREG_ID_AFR0);
3458    InitReg(MISCREG_ID_MMFR0_EL1)
3459      .allPrivileges().exceptUserMode().writes(0)
3460      .mapsTo(MISCREG_ID_MMFR0);
3461    InitReg(MISCREG_ID_MMFR1_EL1)
3462      .allPrivileges().exceptUserMode().writes(0)
3463      .mapsTo(MISCREG_ID_MMFR1);
3464    InitReg(MISCREG_ID_MMFR2_EL1)
3465      .allPrivileges().exceptUserMode().writes(0)
3466      .mapsTo(MISCREG_ID_MMFR2);
3467    InitReg(MISCREG_ID_MMFR3_EL1)
3468      .allPrivileges().exceptUserMode().writes(0)
3469      .mapsTo(MISCREG_ID_MMFR3);
3470    InitReg(MISCREG_ID_ISAR0_EL1)
3471      .allPrivileges().exceptUserMode().writes(0)
3472      .mapsTo(MISCREG_ID_ISAR0);
3473    InitReg(MISCREG_ID_ISAR1_EL1)
3474      .allPrivileges().exceptUserMode().writes(0)
3475      .mapsTo(MISCREG_ID_ISAR1);
3476    InitReg(MISCREG_ID_ISAR2_EL1)
3477      .allPrivileges().exceptUserMode().writes(0)
3478      .mapsTo(MISCREG_ID_ISAR2);
3479    InitReg(MISCREG_ID_ISAR3_EL1)
3480      .allPrivileges().exceptUserMode().writes(0)
3481      .mapsTo(MISCREG_ID_ISAR3);
3482    InitReg(MISCREG_ID_ISAR4_EL1)
3483      .allPrivileges().exceptUserMode().writes(0)
3484      .mapsTo(MISCREG_ID_ISAR4);
3485    InitReg(MISCREG_ID_ISAR5_EL1)
3486      .allPrivileges().exceptUserMode().writes(0)
3487      .mapsTo(MISCREG_ID_ISAR5);
3488    InitReg(MISCREG_MVFR0_EL1)
3489      .allPrivileges().exceptUserMode().writes(0);
3490    InitReg(MISCREG_MVFR1_EL1)
3491      .allPrivileges().exceptUserMode().writes(0);
3492    InitReg(MISCREG_MVFR2_EL1)
3493      .allPrivileges().exceptUserMode().writes(0);
3494    InitReg(MISCREG_ID_AA64PFR0_EL1)
3495      .allPrivileges().exceptUserMode().writes(0);
3496    InitReg(MISCREG_ID_AA64PFR1_EL1)
3497      .allPrivileges().exceptUserMode().writes(0);
3498    InitReg(MISCREG_ID_AA64DFR0_EL1)
3499      .allPrivileges().exceptUserMode().writes(0);
3500    InitReg(MISCREG_ID_AA64DFR1_EL1)
3501      .allPrivileges().exceptUserMode().writes(0);
3502    InitReg(MISCREG_ID_AA64AFR0_EL1)
3503      .allPrivileges().exceptUserMode().writes(0);
3504    InitReg(MISCREG_ID_AA64AFR1_EL1)
3505      .allPrivileges().exceptUserMode().writes(0);
3506    InitReg(MISCREG_ID_AA64ISAR0_EL1)
3507      .allPrivileges().exceptUserMode().writes(0);
3508    InitReg(MISCREG_ID_AA64ISAR1_EL1)
3509      .allPrivileges().exceptUserMode().writes(0);
3510    InitReg(MISCREG_ID_AA64MMFR0_EL1)
3511      .allPrivileges().exceptUserMode().writes(0);
3512    InitReg(MISCREG_ID_AA64MMFR1_EL1)
3513      .allPrivileges().exceptUserMode().writes(0);
3514    InitReg(MISCREG_ID_AA64MMFR2_EL1)
3515      .allPrivileges().exceptUserMode().writes(0);
3516    InitReg(MISCREG_CCSIDR_EL1)
3517      .allPrivileges().exceptUserMode().writes(0);
3518    InitReg(MISCREG_CLIDR_EL1)
3519      .allPrivileges().exceptUserMode().writes(0);
3520    InitReg(MISCREG_AIDR_EL1)
3521      .allPrivileges().exceptUserMode().writes(0);
3522    InitReg(MISCREG_CSSELR_EL1)
3523      .allPrivileges().exceptUserMode()
3524      .mapsTo(MISCREG_CSSELR_NS);
3525    InitReg(MISCREG_CTR_EL0)
3526      .reads(1);
3527    InitReg(MISCREG_DCZID_EL0)
3528      .reads(1);
3529    InitReg(MISCREG_VPIDR_EL2)
3530      .hyp().mon()
3531      .mapsTo(MISCREG_VPIDR);
3532    InitReg(MISCREG_VMPIDR_EL2)
3533      .hyp().mon()
3534      .mapsTo(MISCREG_VMPIDR);
3535    InitReg(MISCREG_SCTLR_EL1)
3536      .allPrivileges().exceptUserMode()
3537      .mapsTo(MISCREG_SCTLR_NS);
3538    InitReg(MISCREG_ACTLR_EL1)
3539      .allPrivileges().exceptUserMode()
3540      .mapsTo(MISCREG_ACTLR_NS);
3541    InitReg(MISCREG_CPACR_EL1)
3542      .allPrivileges().exceptUserMode()
3543      .mapsTo(MISCREG_CPACR);
3544    InitReg(MISCREG_SCTLR_EL2)
3545      .hyp().mon()
3546      .mapsTo(MISCREG_HSCTLR);
3547    InitReg(MISCREG_ACTLR_EL2)
3548      .hyp().mon()
3549      .mapsTo(MISCREG_HACTLR);
3550    InitReg(MISCREG_HCR_EL2)
3551      .hyp().mon()
3552      .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3553    InitReg(MISCREG_MDCR_EL2)
3554      .hyp().mon()
3555      .mapsTo(MISCREG_HDCR);
3556    InitReg(MISCREG_CPTR_EL2)
3557      .hyp().mon()
3558      .mapsTo(MISCREG_HCPTR);
3559    InitReg(MISCREG_HSTR_EL2)
3560      .hyp().mon()
3561      .mapsTo(MISCREG_HSTR);
3562    InitReg(MISCREG_HACR_EL2)
3563      .hyp().mon()
3564      .mapsTo(MISCREG_HACR);
3565    InitReg(MISCREG_SCTLR_EL3)
3566      .mon();
3567    InitReg(MISCREG_ACTLR_EL3)
3568      .mon();
3569    InitReg(MISCREG_SCR_EL3)
3570      .mon()
3571      .mapsTo(MISCREG_SCR); // NAM D7-2005
3572    InitReg(MISCREG_SDER32_EL3)
3573      .mon()
3574      .mapsTo(MISCREG_SDER);
3575    InitReg(MISCREG_CPTR_EL3)
3576      .mon();
3577    InitReg(MISCREG_MDCR_EL3)
3578      .mon();
3579    InitReg(MISCREG_TTBR0_EL1)
3580      .allPrivileges().exceptUserMode()
3581      .mapsTo(MISCREG_TTBR0_NS);
3582    InitReg(MISCREG_TTBR1_EL1)
3583      .allPrivileges().exceptUserMode()
3584      .mapsTo(MISCREG_TTBR1_NS);
3585    InitReg(MISCREG_TCR_EL1)
3586      .allPrivileges().exceptUserMode()
3587      .mapsTo(MISCREG_TTBCR_NS);
3588    InitReg(MISCREG_TTBR0_EL2)
3589      .hyp().mon()
3590      .mapsTo(MISCREG_HTTBR);
3591    InitReg(MISCREG_TTBR1_EL2)
3592      .hyp().mon();
3593    InitReg(MISCREG_TCR_EL2)
3594      .hyp().mon()
3595      .mapsTo(MISCREG_HTCR);
3596    InitReg(MISCREG_VTTBR_EL2)
3597      .hyp().mon()
3598      .mapsTo(MISCREG_VTTBR);
3599    InitReg(MISCREG_VTCR_EL2)
3600      .hyp().mon()
3601      .mapsTo(MISCREG_VTCR);
3602    InitReg(MISCREG_TTBR0_EL3)
3603      .mon();
3604    InitReg(MISCREG_TCR_EL3)
3605      .mon();
3606    InitReg(MISCREG_DACR32_EL2)
3607      .hyp().mon()
3608      .mapsTo(MISCREG_DACR_NS);
3609    InitReg(MISCREG_SPSR_EL1)
3610      .allPrivileges().exceptUserMode()
3611      .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3612    InitReg(MISCREG_ELR_EL1)
3613      .allPrivileges().exceptUserMode();
3614    InitReg(MISCREG_SP_EL0)
3615      .allPrivileges().exceptUserMode();
3616    InitReg(MISCREG_SPSEL)
3617      .allPrivileges().exceptUserMode();
3618    InitReg(MISCREG_CURRENTEL)
3619      .allPrivileges().exceptUserMode().writes(0);
3620    InitReg(MISCREG_NZCV)
3621      .allPrivileges();
3622    InitReg(MISCREG_DAIF)
3623      .allPrivileges();
3624    InitReg(MISCREG_FPCR)
3625      .allPrivileges();
3626    InitReg(MISCREG_FPSR)
3627      .allPrivileges();
3628    InitReg(MISCREG_DSPSR_EL0)
3629      .allPrivileges();
3630    InitReg(MISCREG_DLR_EL0)
3631      .allPrivileges();
3632    InitReg(MISCREG_SPSR_EL2)
3633      .hyp().mon()
3634      .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3635    InitReg(MISCREG_ELR_EL2)
3636      .hyp().mon();
3637    InitReg(MISCREG_SP_EL1)
3638      .hyp().mon();
3639    InitReg(MISCREG_SPSR_IRQ_AA64)
3640      .hyp().mon();
3641    InitReg(MISCREG_SPSR_ABT_AA64)
3642      .hyp().mon();
3643    InitReg(MISCREG_SPSR_UND_AA64)
3644      .hyp().mon();
3645    InitReg(MISCREG_SPSR_FIQ_AA64)
3646      .hyp().mon();
3647    InitReg(MISCREG_SPSR_EL3)
3648      .mon()
3649      .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3650    InitReg(MISCREG_ELR_EL3)
3651      .mon();
3652    InitReg(MISCREG_SP_EL2)
3653      .mon();
3654    InitReg(MISCREG_AFSR0_EL1)
3655      .allPrivileges().exceptUserMode()
3656      .mapsTo(MISCREG_ADFSR_NS);
3657    InitReg(MISCREG_AFSR1_EL1)
3658      .allPrivileges().exceptUserMode()
3659      .mapsTo(MISCREG_AIFSR_NS);
3660    InitReg(MISCREG_ESR_EL1)
3661      .allPrivileges().exceptUserMode();
3662    InitReg(MISCREG_IFSR32_EL2)
3663      .hyp().mon()
3664      .mapsTo(MISCREG_IFSR_NS);
3665    InitReg(MISCREG_AFSR0_EL2)
3666      .hyp().mon()
3667      .mapsTo(MISCREG_HADFSR);
3668    InitReg(MISCREG_AFSR1_EL2)
3669      .hyp().mon()
3670      .mapsTo(MISCREG_HAIFSR);
3671    InitReg(MISCREG_ESR_EL2)
3672      .hyp().mon()
3673      .mapsTo(MISCREG_HSR);
3674    InitReg(MISCREG_FPEXC32_EL2)
3675      .hyp().mon().mapsTo(MISCREG_FPEXC);
3676    InitReg(MISCREG_AFSR0_EL3)
3677      .mon();
3678    InitReg(MISCREG_AFSR1_EL3)
3679      .mon();
3680    InitReg(MISCREG_ESR_EL3)
3681      .mon();
3682    InitReg(MISCREG_FAR_EL1)
3683      .allPrivileges().exceptUserMode()
3684      .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3685    InitReg(MISCREG_FAR_EL2)
3686      .hyp().mon()
3687      .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3688    InitReg(MISCREG_HPFAR_EL2)
3689      .hyp().mon()
3690      .mapsTo(MISCREG_HPFAR);
3691    InitReg(MISCREG_FAR_EL3)
3692      .mon();
3693    InitReg(MISCREG_IC_IALLUIS)
3694      .warnNotFail()
3695      .writes(1).exceptUserMode();
3696    InitReg(MISCREG_PAR_EL1)
3697      .allPrivileges().exceptUserMode()
3698      .mapsTo(MISCREG_PAR_NS);
3699    InitReg(MISCREG_IC_IALLU)
3700      .warnNotFail()
3701      .writes(1).exceptUserMode();
3702    InitReg(MISCREG_DC_IVAC_Xt)
3703      .warnNotFail()
3704      .writes(1).exceptUserMode();
3705    InitReg(MISCREG_DC_ISW_Xt)
3706      .warnNotFail()
3707      .writes(1).exceptUserMode();
3708    InitReg(MISCREG_AT_S1E1R_Xt)
3709      .writes(1).exceptUserMode();
3710    InitReg(MISCREG_AT_S1E1W_Xt)
3711      .writes(1).exceptUserMode();
3712    InitReg(MISCREG_AT_S1E0R_Xt)
3713      .writes(1).exceptUserMode();
3714    InitReg(MISCREG_AT_S1E0W_Xt)
3715      .writes(1).exceptUserMode();
3716    InitReg(MISCREG_DC_CSW_Xt)
3717      .warnNotFail()
3718      .writes(1).exceptUserMode();
3719    InitReg(MISCREG_DC_CISW_Xt)
3720      .warnNotFail()
3721      .writes(1).exceptUserMode();
3722    InitReg(MISCREG_DC_ZVA_Xt)
3723      .warnNotFail()
3724      .writes(1).userSecureWrite(0);
3725    InitReg(MISCREG_IC_IVAU_Xt)
3726      .writes(1);
3727    InitReg(MISCREG_DC_CVAC_Xt)
3728      .warnNotFail()
3729      .writes(1);
3730    InitReg(MISCREG_DC_CVAU_Xt)
3731      .warnNotFail()
3732      .writes(1);
3733    InitReg(MISCREG_DC_CIVAC_Xt)
3734      .warnNotFail()
3735      .writes(1);
3736    InitReg(MISCREG_AT_S1E2R_Xt)
3737      .monNonSecureWrite().hypWrite();
3738    InitReg(MISCREG_AT_S1E2W_Xt)
3739      .monNonSecureWrite().hypWrite();
3740    InitReg(MISCREG_AT_S12E1R_Xt)
3741      .hypWrite().monSecureWrite().monNonSecureWrite();
3742    InitReg(MISCREG_AT_S12E1W_Xt)
3743      .hypWrite().monSecureWrite().monNonSecureWrite();
3744    InitReg(MISCREG_AT_S12E0R_Xt)
3745      .hypWrite().monSecureWrite().monNonSecureWrite();
3746    InitReg(MISCREG_AT_S12E0W_Xt)
3747      .hypWrite().monSecureWrite().monNonSecureWrite();
3748    InitReg(MISCREG_AT_S1E3R_Xt)
3749      .monSecureWrite().monNonSecureWrite();
3750    InitReg(MISCREG_AT_S1E3W_Xt)
3751      .monSecureWrite().monNonSecureWrite();
3752    InitReg(MISCREG_TLBI_VMALLE1IS)
3753      .writes(1).exceptUserMode();
3754    InitReg(MISCREG_TLBI_VAE1IS_Xt)
3755      .writes(1).exceptUserMode();
3756    InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3757      .writes(1).exceptUserMode();
3758    InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3759      .writes(1).exceptUserMode();
3760    InitReg(MISCREG_TLBI_VALE1IS_Xt)
3761      .writes(1).exceptUserMode();
3762    InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3763      .writes(1).exceptUserMode();
3764    InitReg(MISCREG_TLBI_VMALLE1)
3765      .writes(1).exceptUserMode();
3766    InitReg(MISCREG_TLBI_VAE1_Xt)
3767      .writes(1).exceptUserMode();
3768    InitReg(MISCREG_TLBI_ASIDE1_Xt)
3769      .writes(1).exceptUserMode();
3770    InitReg(MISCREG_TLBI_VAAE1_Xt)
3771      .writes(1).exceptUserMode();
3772    InitReg(MISCREG_TLBI_VALE1_Xt)
3773      .writes(1).exceptUserMode();
3774    InitReg(MISCREG_TLBI_VAALE1_Xt)
3775      .writes(1).exceptUserMode();
3776    InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3777      .hypWrite().monSecureWrite().monNonSecureWrite();
3778    InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3779      .hypWrite().monSecureWrite().monNonSecureWrite();
3780    InitReg(MISCREG_TLBI_ALLE2IS)
3781      .monNonSecureWrite().hypWrite();
3782    InitReg(MISCREG_TLBI_VAE2IS_Xt)
3783      .monNonSecureWrite().hypWrite();
3784    InitReg(MISCREG_TLBI_ALLE1IS)
3785      .hypWrite().monSecureWrite().monNonSecureWrite();
3786    InitReg(MISCREG_TLBI_VALE2IS_Xt)
3787      .monNonSecureWrite().hypWrite();
3788    InitReg(MISCREG_TLBI_VMALLS12E1IS)
3789      .hypWrite().monSecureWrite().monNonSecureWrite();
3790    InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3791      .hypWrite().monSecureWrite().monNonSecureWrite();
3792    InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3793      .hypWrite().monSecureWrite().monNonSecureWrite();
3794    InitReg(MISCREG_TLBI_ALLE2)
3795      .monNonSecureWrite().hypWrite();
3796    InitReg(MISCREG_TLBI_VAE2_Xt)
3797      .monNonSecureWrite().hypWrite();
3798    InitReg(MISCREG_TLBI_ALLE1)
3799      .hypWrite().monSecureWrite().monNonSecureWrite();
3800    InitReg(MISCREG_TLBI_VALE2_Xt)
3801      .monNonSecureWrite().hypWrite();
3802    InitReg(MISCREG_TLBI_VMALLS12E1)
3803      .hypWrite().monSecureWrite().monNonSecureWrite();
3804    InitReg(MISCREG_TLBI_ALLE3IS)
3805      .monSecureWrite().monNonSecureWrite();
3806    InitReg(MISCREG_TLBI_VAE3IS_Xt)
3807      .monSecureWrite().monNonSecureWrite();
3808    InitReg(MISCREG_TLBI_VALE3IS_Xt)
3809      .monSecureWrite().monNonSecureWrite();
3810    InitReg(MISCREG_TLBI_ALLE3)
3811      .monSecureWrite().monNonSecureWrite();
3812    InitReg(MISCREG_TLBI_VAE3_Xt)
3813      .monSecureWrite().monNonSecureWrite();
3814    InitReg(MISCREG_TLBI_VALE3_Xt)
3815      .monSecureWrite().monNonSecureWrite();
3816    InitReg(MISCREG_PMINTENSET_EL1)
3817      .allPrivileges().exceptUserMode()
3818      .mapsTo(MISCREG_PMINTENSET);
3819    InitReg(MISCREG_PMINTENCLR_EL1)
3820      .allPrivileges().exceptUserMode()
3821      .mapsTo(MISCREG_PMINTENCLR);
3822    InitReg(MISCREG_PMCR_EL0)
3823      .allPrivileges()
3824      .mapsTo(MISCREG_PMCR);
3825    InitReg(MISCREG_PMCNTENSET_EL0)
3826      .allPrivileges()
3827      .mapsTo(MISCREG_PMCNTENSET);
3828    InitReg(MISCREG_PMCNTENCLR_EL0)
3829      .allPrivileges()
3830      .mapsTo(MISCREG_PMCNTENCLR);
3831    InitReg(MISCREG_PMOVSCLR_EL0)
3832      .allPrivileges();
3833//    .mapsTo(MISCREG_PMOVSCLR);
3834    InitReg(MISCREG_PMSWINC_EL0)
3835      .writes(1).user()
3836      .mapsTo(MISCREG_PMSWINC);
3837    InitReg(MISCREG_PMSELR_EL0)
3838      .allPrivileges()
3839      .mapsTo(MISCREG_PMSELR);
3840    InitReg(MISCREG_PMCEID0_EL0)
3841      .reads(1).user()
3842      .mapsTo(MISCREG_PMCEID0);
3843    InitReg(MISCREG_PMCEID1_EL0)
3844      .reads(1).user()
3845      .mapsTo(MISCREG_PMCEID1);
3846    InitReg(MISCREG_PMCCNTR_EL0)
3847      .allPrivileges()
3848      .mapsTo(MISCREG_PMCCNTR);
3849    InitReg(MISCREG_PMXEVTYPER_EL0)
3850      .allPrivileges()
3851      .mapsTo(MISCREG_PMXEVTYPER);
3852    InitReg(MISCREG_PMCCFILTR_EL0)
3853      .allPrivileges();
3854    InitReg(MISCREG_PMXEVCNTR_EL0)
3855      .allPrivileges()
3856      .mapsTo(MISCREG_PMXEVCNTR);
3857    InitReg(MISCREG_PMUSERENR_EL0)
3858      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3859      .mapsTo(MISCREG_PMUSERENR);
3860    InitReg(MISCREG_PMOVSSET_EL0)
3861      .allPrivileges()
3862      .mapsTo(MISCREG_PMOVSSET);
3863    InitReg(MISCREG_MAIR_EL1)
3864      .allPrivileges().exceptUserMode()
3865      .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3866    InitReg(MISCREG_AMAIR_EL1)
3867      .allPrivileges().exceptUserMode()
3868      .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3869    InitReg(MISCREG_MAIR_EL2)
3870      .hyp().mon()
3871      .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3872    InitReg(MISCREG_AMAIR_EL2)
3873      .hyp().mon()
3874      .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3875    InitReg(MISCREG_MAIR_EL3)
3876      .mon();
3877    InitReg(MISCREG_AMAIR_EL3)
3878      .mon();
3879    InitReg(MISCREG_L2CTLR_EL1)
3880      .allPrivileges().exceptUserMode();
3881    InitReg(MISCREG_L2ECTLR_EL1)
3882      .allPrivileges().exceptUserMode();
3883    InitReg(MISCREG_VBAR_EL1)
3884      .allPrivileges().exceptUserMode()
3885      .mapsTo(MISCREG_VBAR_NS);
3886    InitReg(MISCREG_RVBAR_EL1)
3887      .allPrivileges().exceptUserMode().writes(0);
3888    InitReg(MISCREG_ISR_EL1)
3889      .allPrivileges().exceptUserMode().writes(0);
3890    InitReg(MISCREG_VBAR_EL2)
3891      .hyp().mon()
3892      .mapsTo(MISCREG_HVBAR);
3893    InitReg(MISCREG_RVBAR_EL2)
3894      .mon().hyp().writes(0);
3895    InitReg(MISCREG_VBAR_EL3)
3896      .mon();
3897    InitReg(MISCREG_RVBAR_EL3)
3898      .mon().writes(0);
3899    InitReg(MISCREG_RMR_EL3)
3900      .mon();
3901    InitReg(MISCREG_CONTEXTIDR_EL1)
3902      .allPrivileges().exceptUserMode()
3903      .mapsTo(MISCREG_CONTEXTIDR_NS);
3904    InitReg(MISCREG_TPIDR_EL1)
3905      .allPrivileges().exceptUserMode()
3906      .mapsTo(MISCREG_TPIDRPRW_NS);
3907    InitReg(MISCREG_TPIDR_EL0)
3908      .allPrivileges()
3909      .mapsTo(MISCREG_TPIDRURW_NS);
3910    InitReg(MISCREG_TPIDRRO_EL0)
3911      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3912      .mapsTo(MISCREG_TPIDRURO_NS);
3913    InitReg(MISCREG_TPIDR_EL2)
3914      .hyp().mon()
3915      .mapsTo(MISCREG_HTPIDR);
3916    InitReg(MISCREG_TPIDR_EL3)
3917      .mon();
3918    InitReg(MISCREG_CNTKCTL_EL1)
3919      .allPrivileges().exceptUserMode()
3920      .mapsTo(MISCREG_CNTKCTL);
3921    InitReg(MISCREG_CNTFRQ_EL0)
3922      .reads(1).mon()
3923      .mapsTo(MISCREG_CNTFRQ);
3924    InitReg(MISCREG_CNTPCT_EL0)
3925      .reads(1)
3926      .mapsTo(MISCREG_CNTPCT); /* 64b */
3927    InitReg(MISCREG_CNTVCT_EL0)
3928      .unverifiable()
3929      .reads(1)
3930      .mapsTo(MISCREG_CNTVCT); /* 64b */
3931    InitReg(MISCREG_CNTP_TVAL_EL0)
3932      .allPrivileges()
3933      .mapsTo(MISCREG_CNTP_TVAL_NS);
3934    InitReg(MISCREG_CNTP_CTL_EL0)
3935      .allPrivileges()
3936      .mapsTo(MISCREG_CNTP_CTL_NS);
3937    InitReg(MISCREG_CNTP_CVAL_EL0)
3938      .allPrivileges()
3939      .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
3940    InitReg(MISCREG_CNTV_TVAL_EL0)
3941      .allPrivileges()
3942      .mapsTo(MISCREG_CNTV_TVAL);
3943    InitReg(MISCREG_CNTV_CTL_EL0)
3944      .allPrivileges()
3945      .mapsTo(MISCREG_CNTV_CTL);
3946    InitReg(MISCREG_CNTV_CVAL_EL0)
3947      .allPrivileges()
3948      .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
3949    InitReg(MISCREG_PMEVCNTR0_EL0)
3950      .allPrivileges();
3951//    .mapsTo(MISCREG_PMEVCNTR0);
3952    InitReg(MISCREG_PMEVCNTR1_EL0)
3953      .allPrivileges();
3954//    .mapsTo(MISCREG_PMEVCNTR1);
3955    InitReg(MISCREG_PMEVCNTR2_EL0)
3956      .allPrivileges();
3957//    .mapsTo(MISCREG_PMEVCNTR2);
3958    InitReg(MISCREG_PMEVCNTR3_EL0)
3959      .allPrivileges();
3960//    .mapsTo(MISCREG_PMEVCNTR3);
3961    InitReg(MISCREG_PMEVCNTR4_EL0)
3962      .allPrivileges();
3963//    .mapsTo(MISCREG_PMEVCNTR4);
3964    InitReg(MISCREG_PMEVCNTR5_EL0)
3965      .allPrivileges();
3966//    .mapsTo(MISCREG_PMEVCNTR5);
3967    InitReg(MISCREG_PMEVTYPER0_EL0)
3968      .allPrivileges();
3969//    .mapsTo(MISCREG_PMEVTYPER0);
3970    InitReg(MISCREG_PMEVTYPER1_EL0)
3971      .allPrivileges();
3972//    .mapsTo(MISCREG_PMEVTYPER1);
3973    InitReg(MISCREG_PMEVTYPER2_EL0)
3974      .allPrivileges();
3975//    .mapsTo(MISCREG_PMEVTYPER2);
3976    InitReg(MISCREG_PMEVTYPER3_EL0)
3977      .allPrivileges();
3978//    .mapsTo(MISCREG_PMEVTYPER3);
3979    InitReg(MISCREG_PMEVTYPER4_EL0)
3980      .allPrivileges();
3981//    .mapsTo(MISCREG_PMEVTYPER4);
3982    InitReg(MISCREG_PMEVTYPER5_EL0)
3983      .allPrivileges();
3984//    .mapsTo(MISCREG_PMEVTYPER5);
3985    InitReg(MISCREG_CNTVOFF_EL2)
3986      .hyp().mon()
3987      .mapsTo(MISCREG_CNTVOFF); /* 64b */
3988    InitReg(MISCREG_CNTHCTL_EL2)
3989      .mon().hyp()
3990      .mapsTo(MISCREG_CNTHCTL);
3991    InitReg(MISCREG_CNTHP_TVAL_EL2)
3992      .mon().hyp()
3993      .mapsTo(MISCREG_CNTHP_TVAL);
3994    InitReg(MISCREG_CNTHP_CTL_EL2)
3995      .mon().hyp()
3996      .mapsTo(MISCREG_CNTHP_CTL);
3997    InitReg(MISCREG_CNTHP_CVAL_EL2)
3998      .mon().hyp()
3999      .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4000    InitReg(MISCREG_CNTPS_TVAL_EL1)
4001      .mon().privSecure();
4002    InitReg(MISCREG_CNTPS_CTL_EL1)
4003      .mon().privSecure();
4004    InitReg(MISCREG_CNTPS_CVAL_EL1)
4005      .mon().privSecure();
4006    InitReg(MISCREG_IL1DATA0_EL1)
4007      .allPrivileges().exceptUserMode();
4008    InitReg(MISCREG_IL1DATA1_EL1)
4009      .allPrivileges().exceptUserMode();
4010    InitReg(MISCREG_IL1DATA2_EL1)
4011      .allPrivileges().exceptUserMode();
4012    InitReg(MISCREG_IL1DATA3_EL1)
4013      .allPrivileges().exceptUserMode();
4014    InitReg(MISCREG_DL1DATA0_EL1)
4015      .allPrivileges().exceptUserMode();
4016    InitReg(MISCREG_DL1DATA1_EL1)
4017      .allPrivileges().exceptUserMode();
4018    InitReg(MISCREG_DL1DATA2_EL1)
4019      .allPrivileges().exceptUserMode();
4020    InitReg(MISCREG_DL1DATA3_EL1)
4021      .allPrivileges().exceptUserMode();
4022    InitReg(MISCREG_DL1DATA4_EL1)
4023      .allPrivileges().exceptUserMode();
4024    InitReg(MISCREG_L2ACTLR_EL1)
4025      .allPrivileges().exceptUserMode();
4026    InitReg(MISCREG_CPUACTLR_EL1)
4027      .allPrivileges().exceptUserMode();
4028    InitReg(MISCREG_CPUECTLR_EL1)
4029      .allPrivileges().exceptUserMode();
4030    InitReg(MISCREG_CPUMERRSR_EL1)
4031      .allPrivileges().exceptUserMode();
4032    InitReg(MISCREG_L2MERRSR_EL1)
4033      .unimplemented()
4034      .warnNotFail()
4035      .allPrivileges().exceptUserMode();
4036    InitReg(MISCREG_CBAR_EL1)
4037      .allPrivileges().exceptUserMode().writes(0);
4038    InitReg(MISCREG_CONTEXTIDR_EL2)
4039      .mon().hyp();
4040    InitReg(MISCREG_CNTHV_CTL_EL2)
4041      .mon().hyp();
4042    InitReg(MISCREG_CNTHV_CVAL_EL2)
4043      .mon().hyp();
4044    InitReg(MISCREG_CNTHV_TVAL_EL2)
4045      .mon().hyp();
4046
4047    // Dummy registers
4048    InitReg(MISCREG_NOP)
4049      .allPrivileges();
4050    InitReg(MISCREG_RAZ)
4051      .allPrivileges().exceptUserMode().writes(0);
4052    InitReg(MISCREG_CP14_UNIMPL)
4053      .unimplemented()
4054      .warnNotFail();
4055    InitReg(MISCREG_CP15_UNIMPL)
4056      .unimplemented()
4057      .warnNotFail();
4058    InitReg(MISCREG_UNKNOWN);
4059    InitReg(MISCREG_IMPDEF_UNIMPL)
4060      .unimplemented()
4061      .warnNotFail(impdefAsNop);
4062
4063    // RAS extension (unimplemented)
4064    InitReg(MISCREG_ERRIDR_EL1)
4065      .unimplemented()
4066      .warnNotFail();
4067    InitReg(MISCREG_ERRSELR_EL1)
4068      .unimplemented()
4069      .warnNotFail();
4070    InitReg(MISCREG_ERXFR_EL1)
4071      .unimplemented()
4072      .warnNotFail();
4073    InitReg(MISCREG_ERXCTLR_EL1)
4074      .unimplemented()
4075      .warnNotFail();
4076    InitReg(MISCREG_ERXSTATUS_EL1)
4077      .unimplemented()
4078      .warnNotFail();
4079    InitReg(MISCREG_ERXADDR_EL1)
4080      .unimplemented()
4081      .warnNotFail();
4082    InitReg(MISCREG_ERXMISC0_EL1)
4083      .unimplemented()
4084      .warnNotFail();
4085    InitReg(MISCREG_ERXMISC1_EL1)
4086      .unimplemented()
4087      .warnNotFail();
4088    InitReg(MISCREG_DISR_EL1)
4089      .unimplemented()
4090      .warnNotFail();
4091    InitReg(MISCREG_VSESR_EL2)
4092      .unimplemented()
4093      .warnNotFail();
4094    InitReg(MISCREG_VDISR_EL2)
4095      .unimplemented()
4096      .warnNotFail();
4097
4098    // Register mappings for some unimplemented registers:
4099    // ESR_EL1 -> DFSR
4100    // RMR_EL1 -> RMR
4101    // RMR_EL2 -> HRMR
4102    // DBGDTR_EL0 -> DBGDTR{R or T}Xint
4103    // DBGDTRRX_EL0 -> DBGDTRRXint
4104    // DBGDTRTX_EL0 -> DBGDTRRXint
4105    // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
4106
4107    completed = true;
4108}
4109
4110} // namespace ArmISA
4111