miscregs.cc revision 12499:b81688796004 
1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 *          Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57    switch(crn) {
58      case 0:
59        switch (opc1) {
60          case 0:
61            switch (opc2) {
62              case 0:
63                switch (crm) {
64                  case 0:
65                    return MISCREG_DBGDIDR;
66                  case 1:
67                    return MISCREG_DBGDSCRint;
68                }
69                break;
70            }
71            break;
72          case 7:
73            switch (opc2) {
74              case 0:
75                switch (crm) {
76                  case 0:
77                    return MISCREG_JIDR;
78                }
79              break;
80            }
81            break;
82        }
83        break;
84      case 1:
85        switch (opc1) {
86          case 6:
87            switch (crm) {
88              case 0:
89                switch (opc2) {
90                  case 0:
91                    return MISCREG_TEEHBR;
92                }
93                break;
94            }
95            break;
96          case 7:
97            switch (crm) {
98              case 0:
99                switch (opc2) {
100                  case 0:
101                    return MISCREG_JOSCR;
102                }
103                break;
104            }
105            break;
106        }
107        break;
108      case 2:
109        switch (opc1) {
110          case 7:
111            switch (crm) {
112              case 0:
113                switch (opc2) {
114                  case 0:
115                    return MISCREG_JMCR;
116                }
117                break;
118            }
119            break;
120        }
121        break;
122    }
123    // If we get here then it must be a register that we haven't implemented
124    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125         crn, opc1, crm, opc2);
126    return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134    switch (crn) {
135      case 0:
136        switch (opc1) {
137          case 0:
138            switch (crm) {
139              case 0:
140                switch (opc2) {
141                  case 1:
142                    return MISCREG_CTR;
143                  case 2:
144                    return MISCREG_TCMTR;
145                  case 3:
146                    return MISCREG_TLBTR;
147                  case 5:
148                    return MISCREG_MPIDR;
149                  case 6:
150                    return MISCREG_REVIDR;
151                  default:
152                    return MISCREG_MIDR;
153                }
154                break;
155              case 1:
156                switch (opc2) {
157                  case 0:
158                    return MISCREG_ID_PFR0;
159                  case 1:
160                    return MISCREG_ID_PFR1;
161                  case 2:
162                    return MISCREG_ID_DFR0;
163                  case 3:
164                    return MISCREG_ID_AFR0;
165                  case 4:
166                    return MISCREG_ID_MMFR0;
167                  case 5:
168                    return MISCREG_ID_MMFR1;
169                  case 6:
170                    return MISCREG_ID_MMFR2;
171                  case 7:
172                    return MISCREG_ID_MMFR3;
173                }
174                break;
175              case 2:
176                switch (opc2) {
177                  case 0:
178                    return MISCREG_ID_ISAR0;
179                  case 1:
180                    return MISCREG_ID_ISAR1;
181                  case 2:
182                    return MISCREG_ID_ISAR2;
183                  case 3:
184                    return MISCREG_ID_ISAR3;
185                  case 4:
186                    return MISCREG_ID_ISAR4;
187                  case 5:
188                    return MISCREG_ID_ISAR5;
189                  case 6:
190                  case 7:
191                    return MISCREG_RAZ; // read as zero
192                }
193                break;
194              default:
195                return MISCREG_RAZ; // read as zero
196            }
197            break;
198          case 1:
199            if (crm == 0) {
200                switch (opc2) {
201                  case 0:
202                    return MISCREG_CCSIDR;
203                  case 1:
204                    return MISCREG_CLIDR;
205                  case 7:
206                    return MISCREG_AIDR;
207                }
208            }
209            break;
210          case 2:
211            if (crm == 0 && opc2 == 0) {
212                return MISCREG_CSSELR;
213            }
214            break;
215          case 4:
216            if (crm == 0) {
217                if (opc2 == 0)
218                    return MISCREG_VPIDR;
219                else if (opc2 == 5)
220                    return MISCREG_VMPIDR;
221            }
222            break;
223        }
224        break;
225      case 1:
226        if (opc1 == 0) {
227            if (crm == 0) {
228                switch (opc2) {
229                  case 0:
230                    return MISCREG_SCTLR;
231                  case 1:
232                    return MISCREG_ACTLR;
233                  case 0x2:
234                    return MISCREG_CPACR;
235                }
236            } else if (crm == 1) {
237                switch (opc2) {
238                  case 0:
239                    return MISCREG_SCR;
240                  case 1:
241                    return MISCREG_SDER;
242                  case 2:
243                    return MISCREG_NSACR;
244                }
245            }
246        } else if (opc1 == 4) {
247            if (crm == 0) {
248                if (opc2 == 0)
249                    return MISCREG_HSCTLR;
250                else if (opc2 == 1)
251                    return MISCREG_HACTLR;
252            } else if (crm == 1) {
253                switch (opc2) {
254                  case 0:
255                    return MISCREG_HCR;
256                  case 1:
257                    return MISCREG_HDCR;
258                  case 2:
259                    return MISCREG_HCPTR;
260                  case 3:
261                    return MISCREG_HSTR;
262                  case 7:
263                    return MISCREG_HACR;
264                }
265            }
266        }
267        break;
268      case 2:
269        if (opc1 == 0 && crm == 0) {
270            switch (opc2) {
271              case 0:
272                return MISCREG_TTBR0;
273              case 1:
274                return MISCREG_TTBR1;
275              case 2:
276                return MISCREG_TTBCR;
277            }
278        } else if (opc1 == 4) {
279            if (crm == 0 && opc2 == 2)
280                return MISCREG_HTCR;
281            else if (crm == 1 && opc2 == 2)
282                return MISCREG_VTCR;
283        }
284        break;
285      case 3:
286        if (opc1 == 0 && crm == 0 && opc2 == 0) {
287            return MISCREG_DACR;
288        }
289        break;
290      case 5:
291        if (opc1 == 0) {
292            if (crm == 0) {
293                if (opc2 == 0) {
294                    return MISCREG_DFSR;
295                } else if (opc2 == 1) {
296                    return MISCREG_IFSR;
297                }
298            } else if (crm == 1) {
299                if (opc2 == 0) {
300                    return MISCREG_ADFSR;
301                } else if (opc2 == 1) {
302                    return MISCREG_AIFSR;
303                }
304            }
305        } else if (opc1 == 4) {
306            if (crm == 1) {
307                if (opc2 == 0)
308                    return MISCREG_HADFSR;
309                else if (opc2 == 1)
310                    return MISCREG_HAIFSR;
311            } else if (crm == 2 && opc2 == 0) {
312                return MISCREG_HSR;
313            }
314        }
315        break;
316      case 6:
317        if (opc1 == 0 && crm == 0) {
318            switch (opc2) {
319              case 0:
320                return MISCREG_DFAR;
321              case 2:
322                return MISCREG_IFAR;
323            }
324        } else if (opc1 == 4 && crm == 0) {
325            switch (opc2) {
326              case 0:
327                return MISCREG_HDFAR;
328              case 2:
329                return MISCREG_HIFAR;
330              case 4:
331                return MISCREG_HPFAR;
332            }
333        }
334        break;
335      case 7:
336        if (opc1 == 0) {
337            switch (crm) {
338              case 0:
339                if (opc2 == 4) {
340                    return MISCREG_NOP;
341                }
342                break;
343              case 1:
344                switch (opc2) {
345                  case 0:
346                    return MISCREG_ICIALLUIS;
347                  case 6:
348                    return MISCREG_BPIALLIS;
349                }
350                break;
351              case 4:
352                if (opc2 == 0) {
353                    return MISCREG_PAR;
354                }
355                break;
356              case 5:
357                switch (opc2) {
358                  case 0:
359                    return MISCREG_ICIALLU;
360                  case 1:
361                    return MISCREG_ICIMVAU;
362                  case 4:
363                    return MISCREG_CP15ISB;
364                  case 6:
365                    return MISCREG_BPIALL;
366                  case 7:
367                    return MISCREG_BPIMVA;
368                }
369                break;
370              case 6:
371                if (opc2 == 1) {
372                    return MISCREG_DCIMVAC;
373                } else if (opc2 == 2) {
374                    return MISCREG_DCISW;
375                }
376                break;
377              case 8:
378                switch (opc2) {
379                  case 0:
380                    return MISCREG_ATS1CPR;
381                  case 1:
382                    return MISCREG_ATS1CPW;
383                  case 2:
384                    return MISCREG_ATS1CUR;
385                  case 3:
386                    return MISCREG_ATS1CUW;
387                  case 4:
388                    return MISCREG_ATS12NSOPR;
389                  case 5:
390                    return MISCREG_ATS12NSOPW;
391                  case 6:
392                    return MISCREG_ATS12NSOUR;
393                  case 7:
394                    return MISCREG_ATS12NSOUW;
395                }
396                break;
397              case 10:
398                switch (opc2) {
399                  case 1:
400                    return MISCREG_DCCMVAC;
401                  case 2:
402                    return MISCREG_DCCSW;
403                  case 4:
404                    return MISCREG_CP15DSB;
405                  case 5:
406                    return MISCREG_CP15DMB;
407                }
408                break;
409              case 11:
410                if (opc2 == 1) {
411                    return MISCREG_DCCMVAU;
412                }
413                break;
414              case 13:
415                if (opc2 == 1) {
416                    return MISCREG_NOP;
417                }
418                break;
419              case 14:
420                if (opc2 == 1) {
421                    return MISCREG_DCCIMVAC;
422                } else if (opc2 == 2) {
423                    return MISCREG_DCCISW;
424                }
425                break;
426            }
427        } else if (opc1 == 4 && crm == 8) {
428            if (opc2 == 0)
429                return MISCREG_ATS1HR;
430            else if (opc2 == 1)
431                return MISCREG_ATS1HW;
432        }
433        break;
434      case 8:
435        if (opc1 == 0) {
436            switch (crm) {
437              case 3:
438                switch (opc2) {
439                  case 0:
440                    return MISCREG_TLBIALLIS;
441                  case 1:
442                    return MISCREG_TLBIMVAIS;
443                  case 2:
444                    return MISCREG_TLBIASIDIS;
445                  case 3:
446                    return MISCREG_TLBIMVAAIS;
447                }
448                break;
449              case 5:
450                switch (opc2) {
451                  case 0:
452                    return MISCREG_ITLBIALL;
453                  case 1:
454                    return MISCREG_ITLBIMVA;
455                  case 2:
456                    return MISCREG_ITLBIASID;
457                }
458                break;
459              case 6:
460                switch (opc2) {
461                  case 0:
462                    return MISCREG_DTLBIALL;
463                  case 1:
464                    return MISCREG_DTLBIMVA;
465                  case 2:
466                    return MISCREG_DTLBIASID;
467                }
468                break;
469              case 7:
470                switch (opc2) {
471                  case 0:
472                    return MISCREG_TLBIALL;
473                  case 1:
474                    return MISCREG_TLBIMVA;
475                  case 2:
476                    return MISCREG_TLBIASID;
477                  case 3:
478                    return MISCREG_TLBIMVAA;
479                }
480                break;
481            }
482        } else if (opc1 == 4) {
483            if (crm == 3) {
484                switch (opc2) {
485                  case 0:
486                    return MISCREG_TLBIALLHIS;
487                  case 1:
488                    return MISCREG_TLBIMVAHIS;
489                  case 4:
490                    return MISCREG_TLBIALLNSNHIS;
491                }
492            } else if (crm == 7) {
493                switch (opc2) {
494                  case 0:
495                    return MISCREG_TLBIALLH;
496                  case 1:
497                    return MISCREG_TLBIMVAH;
498                  case 4:
499                    return MISCREG_TLBIALLNSNH;
500                }
501            }
502        }
503        break;
504      case 9:
505        if (opc1 == 0) {
506            switch (crm) {
507              case 12:
508                switch (opc2) {
509                  case 0:
510                    return MISCREG_PMCR;
511                  case 1:
512                    return MISCREG_PMCNTENSET;
513                  case 2:
514                    return MISCREG_PMCNTENCLR;
515                  case 3:
516                    return MISCREG_PMOVSR;
517                  case 4:
518                    return MISCREG_PMSWINC;
519                  case 5:
520                    return MISCREG_PMSELR;
521                  case 6:
522                    return MISCREG_PMCEID0;
523                  case 7:
524                    return MISCREG_PMCEID1;
525                }
526                break;
527              case 13:
528                switch (opc2) {
529                  case 0:
530                    return MISCREG_PMCCNTR;
531                  case 1:
532                    // Selector is PMSELR.SEL
533                    return MISCREG_PMXEVTYPER_PMCCFILTR;
534                  case 2:
535                    return MISCREG_PMXEVCNTR;
536                }
537                break;
538              case 14:
539                switch (opc2) {
540                  case 0:
541                    return MISCREG_PMUSERENR;
542                  case 1:
543                    return MISCREG_PMINTENSET;
544                  case 2:
545                    return MISCREG_PMINTENCLR;
546                  case 3:
547                    return MISCREG_PMOVSSET;
548                }
549                break;
550            }
551        } else if (opc1 == 1) {
552            switch (crm) {
553              case 0:
554                switch (opc2) {
555                  case 2: // L2CTLR, L2 Control Register
556                    return MISCREG_L2CTLR;
557                  case 3:
558                    return MISCREG_L2ECTLR;
559                }
560                break;
561                break;
562            }
563        }
564        break;
565      case 10:
566        if (opc1 == 0) {
567            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
568            if (crm == 2) { // TEX Remap Registers
569                if (opc2 == 0) {
570                    // Selector is TTBCR.EAE
571                    return MISCREG_PRRR_MAIR0;
572                } else if (opc2 == 1) {
573                    // Selector is TTBCR.EAE
574                    return MISCREG_NMRR_MAIR1;
575                }
576            } else if (crm == 3) {
577                if (opc2 == 0) {
578                    return MISCREG_AMAIR0;
579                } else if (opc2 == 1) {
580                    return MISCREG_AMAIR1;
581                }
582            }
583        } else if (opc1 == 4) {
584            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
585            if (crm == 2) {
586                if (opc2 == 0)
587                    return MISCREG_HMAIR0;
588                else if (opc2 == 1)
589                    return MISCREG_HMAIR1;
590            } else if (crm == 3) {
591                if (opc2 == 0)
592                    return MISCREG_HAMAIR0;
593                else if (opc2 == 1)
594                    return MISCREG_HAMAIR1;
595            }
596        }
597        break;
598      case 11:
599        if (opc1 <=7) {
600            switch (crm) {
601              case 0:
602              case 1:
603              case 2:
604              case 3:
605              case 4:
606              case 5:
607              case 6:
608              case 7:
609              case 8:
610              case 15:
611                // Reserved for DMA operations for TCM access
612                break;
613            }
614        }
615        break;
616      case 12:
617        if (opc1 == 0) {
618            if (crm == 0) {
619                if (opc2 == 0) {
620                    return MISCREG_VBAR;
621                } else if (opc2 == 1) {
622                    return MISCREG_MVBAR;
623                }
624            } else if (crm == 1) {
625                if (opc2 == 0) {
626                    return MISCREG_ISR;
627                }
628            }
629        } else if (opc1 == 4) {
630            if (crm == 0 && opc2 == 0)
631                return MISCREG_HVBAR;
632        }
633        break;
634      case 13:
635        if (opc1 == 0) {
636            if (crm == 0) {
637                switch (opc2) {
638                  case 0:
639                    return MISCREG_FCSEIDR;
640                  case 1:
641                    return MISCREG_CONTEXTIDR;
642                  case 2:
643                    return MISCREG_TPIDRURW;
644                  case 3:
645                    return MISCREG_TPIDRURO;
646                  case 4:
647                    return MISCREG_TPIDRPRW;
648                }
649            }
650        } else if (opc1 == 4) {
651            if (crm == 0 && opc2 == 2)
652                return MISCREG_HTPIDR;
653        }
654        break;
655      case 14:
656        if (opc1 == 0) {
657            switch (crm) {
658              case 0:
659                if (opc2 == 0)
660                    return MISCREG_CNTFRQ;
661                break;
662              case 1:
663                if (opc2 == 0)
664                    return MISCREG_CNTKCTL;
665                break;
666              case 2:
667                if (opc2 == 0)
668                    return MISCREG_CNTP_TVAL;
669                else if (opc2 == 1)
670                    return MISCREG_CNTP_CTL;
671                break;
672              case 3:
673                if (opc2 == 0)
674                    return MISCREG_CNTV_TVAL;
675                else if (opc2 == 1)
676                    return MISCREG_CNTV_CTL;
677                break;
678            }
679        } else if (opc1 == 4) {
680            if (crm == 1 && opc2 == 0) {
681                return MISCREG_CNTHCTL;
682            } else if (crm == 2) {
683                if (opc2 == 0)
684                    return MISCREG_CNTHP_TVAL;
685                else if (opc2 == 1)
686                    return MISCREG_CNTHP_CTL;
687            }
688        }
689        break;
690      case 15:
691        // Implementation defined
692        return MISCREG_CP15_UNIMPL;
693    }
694    // Unrecognized register
695    return MISCREG_CP15_UNIMPL;
696}
697
698MiscRegIndex
699decodeCP15Reg64(unsigned crm, unsigned opc1)
700{
701    switch (crm) {
702      case 2:
703        switch (opc1) {
704          case 0:
705            return MISCREG_TTBR0;
706          case 1:
707            return MISCREG_TTBR1;
708          case 4:
709            return MISCREG_HTTBR;
710          case 6:
711            return MISCREG_VTTBR;
712        }
713        break;
714      case 7:
715        if (opc1 == 0)
716            return MISCREG_PAR;
717        break;
718      case 14:
719        switch (opc1) {
720          case 0:
721            return MISCREG_CNTPCT;
722          case 1:
723            return MISCREG_CNTVCT;
724          case 2:
725            return MISCREG_CNTP_CVAL;
726          case 3:
727            return MISCREG_CNTV_CVAL;
728          case 4:
729            return MISCREG_CNTVOFF;
730          case 6:
731            return MISCREG_CNTHP_CVAL;
732        }
733        break;
734      case 15:
735        if (opc1 == 0)
736            return MISCREG_CPUMERRSR;
737        else if (opc1 == 1)
738            return MISCREG_L2MERRSR;
739        break;
740    }
741    // Unrecognized register
742    return MISCREG_CP15_UNIMPL;
743}
744
745std::tuple<bool, bool>
746canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
747{
748    bool secure = !scr.ns;
749    bool canRead = false;
750    bool undefined = false;
751
752    switch (cpsr.mode) {
753      case MODE_USER:
754        canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
755                           miscRegInfo[reg][MISCREG_USR_NS_RD];
756        break;
757      case MODE_FIQ:
758      case MODE_IRQ:
759      case MODE_SVC:
760      case MODE_ABORT:
761      case MODE_UNDEFINED:
762      case MODE_SYSTEM:
763        canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
764                           miscRegInfo[reg][MISCREG_PRI_NS_RD];
765        break;
766      case MODE_MON:
767        canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
768                           miscRegInfo[reg][MISCREG_MON_NS1_RD];
769        break;
770      case MODE_HYP:
771        canRead = miscRegInfo[reg][MISCREG_HYP_RD];
772        break;
773      default:
774        undefined = true;
775    }
776    // can't do permissions checkes on the root of a banked pair of regs
777    assert(!miscRegInfo[reg][MISCREG_BANKED]);
778    return std::make_tuple(canRead, undefined);
779}
780
781std::tuple<bool, bool>
782canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
783{
784    bool secure = !scr.ns;
785    bool canWrite = false;
786    bool undefined = false;
787
788    switch (cpsr.mode) {
789      case MODE_USER:
790        canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
791                            miscRegInfo[reg][MISCREG_USR_NS_WR];
792        break;
793      case MODE_FIQ:
794      case MODE_IRQ:
795      case MODE_SVC:
796      case MODE_ABORT:
797      case MODE_UNDEFINED:
798      case MODE_SYSTEM:
799        canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
800                            miscRegInfo[reg][MISCREG_PRI_NS_WR];
801        break;
802      case MODE_MON:
803        canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
804                            miscRegInfo[reg][MISCREG_MON_NS1_WR];
805        break;
806      case MODE_HYP:
807        canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
808        break;
809      default:
810        undefined = true;
811    }
812    // can't do permissions checkes on the root of a banked pair of regs
813    assert(!miscRegInfo[reg][MISCREG_BANKED]);
814    return std::make_tuple(canWrite, undefined);
815}
816
817int
818snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
819{
820    SCR scr = tc->readMiscReg(MISCREG_SCR);
821    return snsBankedIndex(reg, tc, scr.ns);
822}
823
824int
825snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
826{
827    int reg_as_int = static_cast<int>(reg);
828    if (miscRegInfo[reg][MISCREG_BANKED]) {
829        reg_as_int += (ArmSystem::haveSecurity(tc) &&
830                      !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
831    }
832    return reg_as_int;
833}
834
835
836/**
837 * If the reg is a child reg of a banked set, then the parent is the last
838 * banked one in the list. This is messy, and the wish is to eventually have
839 * the bitmap replaced with a better data structure. the preUnflatten function
840 * initializes a lookup table to speed up the search for these banked
841 * registers.
842 */
843
844int unflattenResultMiscReg[NUM_MISCREGS];
845
846void
847preUnflattenMiscReg()
848{
849    int reg = -1;
850    for (int i = 0 ; i < NUM_MISCREGS; i++){
851        if (miscRegInfo[i][MISCREG_BANKED])
852            reg = i;
853        if (miscRegInfo[i][MISCREG_BANKED_CHILD])
854            unflattenResultMiscReg[i] = reg;
855        else
856            unflattenResultMiscReg[i] = i;
857        // if this assert fails, no parent was found, and something is broken
858        assert(unflattenResultMiscReg[i] > -1);
859    }
860}
861
862int
863unflattenMiscReg(int reg)
864{
865    return unflattenResultMiscReg[reg];
866}
867
868bool
869canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
870{
871    // Check for SP_EL0 access while SPSEL == 0
872    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
873        return false;
874
875    // Check for RVBAR access
876    if (reg == MISCREG_RVBAR_EL1) {
877        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
878        if (highest_el == EL2 || highest_el == EL3)
879            return false;
880    }
881    if (reg == MISCREG_RVBAR_EL2) {
882        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
883        if (highest_el == EL3)
884            return false;
885    }
886
887    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
888
889    switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
890      case EL0:
891        return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
892            miscRegInfo[reg][MISCREG_USR_NS_RD];
893      case EL1:
894        return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
895            miscRegInfo[reg][MISCREG_PRI_NS_RD];
896      case EL2:
897        return miscRegInfo[reg][MISCREG_HYP_RD];
898      case EL3:
899        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
900            miscRegInfo[reg][MISCREG_MON_NS1_RD];
901      default:
902        panic("Invalid exception level");
903    }
904}
905
906bool
907canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
908{
909    // Check for SP_EL0 access while SPSEL == 0
910    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
911        return false;
912    ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
913    if (reg == MISCREG_DAIF) {
914        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
915        if (el == EL0 && !sctlr.uma)
916            return false;
917    }
918    if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
919        // In syscall-emulation mode, this test is skipped and DCZVA is always
920        // allowed at EL0
921        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
922        if (el == EL0 && !sctlr.dze)
923            return false;
924    }
925    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt ||
926        reg == MISCREG_DC_IVAC_Xt) {
927        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
928        if (el == EL0 && !sctlr.uci)
929            return false;
930    }
931
932    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
933
934    switch (el) {
935      case EL0:
936        return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
937            miscRegInfo[reg][MISCREG_USR_NS_WR];
938      case EL1:
939        return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
940            miscRegInfo[reg][MISCREG_PRI_NS_WR];
941      case EL2:
942        return miscRegInfo[reg][MISCREG_HYP_WR];
943      case EL3:
944        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
945            miscRegInfo[reg][MISCREG_MON_NS1_WR];
946      default:
947        panic("Invalid exception level");
948    }
949}
950
951MiscRegIndex
952decodeAArch64SysReg(unsigned op0, unsigned op1,
953                    unsigned crn, unsigned crm,
954                    unsigned op2)
955{
956    switch (op0) {
957      case 1:
958        switch (crn) {
959          case 7:
960            switch (op1) {
961              case 0:
962                switch (crm) {
963                  case 1:
964                    switch (op2) {
965                      case 0:
966                        return MISCREG_IC_IALLUIS;
967                    }
968                    break;
969                  case 5:
970                    switch (op2) {
971                      case 0:
972                        return MISCREG_IC_IALLU;
973                    }
974                    break;
975                  case 6:
976                    switch (op2) {
977                      case 1:
978                        return MISCREG_DC_IVAC_Xt;
979                      case 2:
980                        return MISCREG_DC_ISW_Xt;
981                    }
982                    break;
983                  case 8:
984                    switch (op2) {
985                      case 0:
986                        return MISCREG_AT_S1E1R_Xt;
987                      case 1:
988                        return MISCREG_AT_S1E1W_Xt;
989                      case 2:
990                        return MISCREG_AT_S1E0R_Xt;
991                      case 3:
992                        return MISCREG_AT_S1E0W_Xt;
993                    }
994                    break;
995                  case 10:
996                    switch (op2) {
997                      case 2:
998                        return MISCREG_DC_CSW_Xt;
999                    }
1000                    break;
1001                  case 14:
1002                    switch (op2) {
1003                      case 2:
1004                        return MISCREG_DC_CISW_Xt;
1005                    }
1006                    break;
1007                }
1008                break;
1009              case 3:
1010                switch (crm) {
1011                  case 4:
1012                    switch (op2) {
1013                      case 1:
1014                        return MISCREG_DC_ZVA_Xt;
1015                    }
1016                    break;
1017                  case 5:
1018                    switch (op2) {
1019                      case 1:
1020                        return MISCREG_IC_IVAU_Xt;
1021                    }
1022                    break;
1023                  case 10:
1024                    switch (op2) {
1025                      case 1:
1026                        return MISCREG_DC_CVAC_Xt;
1027                    }
1028                    break;
1029                  case 11:
1030                    switch (op2) {
1031                      case 1:
1032                        return MISCREG_DC_CVAU_Xt;
1033                    }
1034                    break;
1035                  case 14:
1036                    switch (op2) {
1037                      case 1:
1038                        return MISCREG_DC_CIVAC_Xt;
1039                    }
1040                    break;
1041                }
1042                break;
1043              case 4:
1044                switch (crm) {
1045                  case 8:
1046                    switch (op2) {
1047                      case 0:
1048                        return MISCREG_AT_S1E2R_Xt;
1049                      case 1:
1050                        return MISCREG_AT_S1E2W_Xt;
1051                      case 4:
1052                        return MISCREG_AT_S12E1R_Xt;
1053                      case 5:
1054                        return MISCREG_AT_S12E1W_Xt;
1055                      case 6:
1056                        return MISCREG_AT_S12E0R_Xt;
1057                      case 7:
1058                        return MISCREG_AT_S12E0W_Xt;
1059                    }
1060                    break;
1061                }
1062                break;
1063              case 6:
1064                switch (crm) {
1065                  case 8:
1066                    switch (op2) {
1067                      case 0:
1068                        return MISCREG_AT_S1E3R_Xt;
1069                      case 1:
1070                        return MISCREG_AT_S1E3W_Xt;
1071                    }
1072                    break;
1073                }
1074                break;
1075            }
1076            break;
1077          case 8:
1078            switch (op1) {
1079              case 0:
1080                switch (crm) {
1081                  case 3:
1082                    switch (op2) {
1083                      case 0:
1084                        return MISCREG_TLBI_VMALLE1IS;
1085                      case 1:
1086                        return MISCREG_TLBI_VAE1IS_Xt;
1087                      case 2:
1088                        return MISCREG_TLBI_ASIDE1IS_Xt;
1089                      case 3:
1090                        return MISCREG_TLBI_VAAE1IS_Xt;
1091                      case 5:
1092                        return MISCREG_TLBI_VALE1IS_Xt;
1093                      case 7:
1094                        return MISCREG_TLBI_VAALE1IS_Xt;
1095                    }
1096                    break;
1097                  case 7:
1098                    switch (op2) {
1099                      case 0:
1100                        return MISCREG_TLBI_VMALLE1;
1101                      case 1:
1102                        return MISCREG_TLBI_VAE1_Xt;
1103                      case 2:
1104                        return MISCREG_TLBI_ASIDE1_Xt;
1105                      case 3:
1106                        return MISCREG_TLBI_VAAE1_Xt;
1107                      case 5:
1108                        return MISCREG_TLBI_VALE1_Xt;
1109                      case 7:
1110                        return MISCREG_TLBI_VAALE1_Xt;
1111                    }
1112                    break;
1113                }
1114                break;
1115              case 4:
1116                switch (crm) {
1117                  case 0:
1118                    switch (op2) {
1119                      case 1:
1120                        return MISCREG_TLBI_IPAS2E1IS_Xt;
1121                      case 5:
1122                        return MISCREG_TLBI_IPAS2LE1IS_Xt;
1123                    }
1124                    break;
1125                  case 3:
1126                    switch (op2) {
1127                      case 0:
1128                        return MISCREG_TLBI_ALLE2IS;
1129                      case 1:
1130                        return MISCREG_TLBI_VAE2IS_Xt;
1131                      case 4:
1132                        return MISCREG_TLBI_ALLE1IS;
1133                      case 5:
1134                        return MISCREG_TLBI_VALE2IS_Xt;
1135                      case 6:
1136                        return MISCREG_TLBI_VMALLS12E1IS;
1137                    }
1138                    break;
1139                  case 4:
1140                    switch (op2) {
1141                      case 1:
1142                        return MISCREG_TLBI_IPAS2E1_Xt;
1143                      case 5:
1144                        return MISCREG_TLBI_IPAS2LE1_Xt;
1145                    }
1146                    break;
1147                  case 7:
1148                    switch (op2) {
1149                      case 0:
1150                        return MISCREG_TLBI_ALLE2;
1151                      case 1:
1152                        return MISCREG_TLBI_VAE2_Xt;
1153                      case 4:
1154                        return MISCREG_TLBI_ALLE1;
1155                      case 5:
1156                        return MISCREG_TLBI_VALE2_Xt;
1157                      case 6:
1158                        return MISCREG_TLBI_VMALLS12E1;
1159                    }
1160                    break;
1161                }
1162                break;
1163              case 6:
1164                switch (crm) {
1165                  case 3:
1166                    switch (op2) {
1167                      case 0:
1168                        return MISCREG_TLBI_ALLE3IS;
1169                      case 1:
1170                        return MISCREG_TLBI_VAE3IS_Xt;
1171                      case 5:
1172                        return MISCREG_TLBI_VALE3IS_Xt;
1173                    }
1174                    break;
1175                  case 7:
1176                    switch (op2) {
1177                      case 0:
1178                        return MISCREG_TLBI_ALLE3;
1179                      case 1:
1180                        return MISCREG_TLBI_VAE3_Xt;
1181                      case 5:
1182                        return MISCREG_TLBI_VALE3_Xt;
1183                    }
1184                    break;
1185                }
1186                break;
1187            }
1188            break;
1189        }
1190        break;
1191      case 2:
1192        switch (crn) {
1193          case 0:
1194            switch (op1) {
1195              case 0:
1196                switch (crm) {
1197                  case 0:
1198                    switch (op2) {
1199                      case 2:
1200                        return MISCREG_OSDTRRX_EL1;
1201                      case 4:
1202                        return MISCREG_DBGBVR0_EL1;
1203                      case 5:
1204                        return MISCREG_DBGBCR0_EL1;
1205                      case 6:
1206                        return MISCREG_DBGWVR0_EL1;
1207                      case 7:
1208                        return MISCREG_DBGWCR0_EL1;
1209                    }
1210                    break;
1211                  case 1:
1212                    switch (op2) {
1213                      case 4:
1214                        return MISCREG_DBGBVR1_EL1;
1215                      case 5:
1216                        return MISCREG_DBGBCR1_EL1;
1217                      case 6:
1218                        return MISCREG_DBGWVR1_EL1;
1219                      case 7:
1220                        return MISCREG_DBGWCR1_EL1;
1221                    }
1222                    break;
1223                  case 2:
1224                    switch (op2) {
1225                      case 0:
1226                        return MISCREG_MDCCINT_EL1;
1227                      case 2:
1228                        return MISCREG_MDSCR_EL1;
1229                      case 4:
1230                        return MISCREG_DBGBVR2_EL1;
1231                      case 5:
1232                        return MISCREG_DBGBCR2_EL1;
1233                      case 6:
1234                        return MISCREG_DBGWVR2_EL1;
1235                      case 7:
1236                        return MISCREG_DBGWCR2_EL1;
1237                    }
1238                    break;
1239                  case 3:
1240                    switch (op2) {
1241                      case 2:
1242                        return MISCREG_OSDTRTX_EL1;
1243                      case 4:
1244                        return MISCREG_DBGBVR3_EL1;
1245                      case 5:
1246                        return MISCREG_DBGBCR3_EL1;
1247                      case 6:
1248                        return MISCREG_DBGWVR3_EL1;
1249                      case 7:
1250                        return MISCREG_DBGWCR3_EL1;
1251                    }
1252                    break;
1253                  case 4:
1254                    switch (op2) {
1255                      case 4:
1256                        return MISCREG_DBGBVR4_EL1;
1257                      case 5:
1258                        return MISCREG_DBGBCR4_EL1;
1259                    }
1260                    break;
1261                  case 5:
1262                    switch (op2) {
1263                      case 4:
1264                        return MISCREG_DBGBVR5_EL1;
1265                      case 5:
1266                        return MISCREG_DBGBCR5_EL1;
1267                    }
1268                    break;
1269                  case 6:
1270                    switch (op2) {
1271                      case 2:
1272                        return MISCREG_OSECCR_EL1;
1273                    }
1274                    break;
1275                }
1276                break;
1277              case 2:
1278                switch (crm) {
1279                  case 0:
1280                    switch (op2) {
1281                      case 0:
1282                        return MISCREG_TEECR32_EL1;
1283                    }
1284                    break;
1285                }
1286                break;
1287              case 3:
1288                switch (crm) {
1289                  case 1:
1290                    switch (op2) {
1291                      case 0:
1292                        return MISCREG_MDCCSR_EL0;
1293                    }
1294                    break;
1295                  case 4:
1296                    switch (op2) {
1297                      case 0:
1298                        return MISCREG_MDDTR_EL0;
1299                    }
1300                    break;
1301                  case 5:
1302                    switch (op2) {
1303                      case 0:
1304                        return MISCREG_MDDTRRX_EL0;
1305                    }
1306                    break;
1307                }
1308                break;
1309              case 4:
1310                switch (crm) {
1311                  case 7:
1312                    switch (op2) {
1313                      case 0:
1314                        return MISCREG_DBGVCR32_EL2;
1315                    }
1316                    break;
1317                }
1318                break;
1319            }
1320            break;
1321          case 1:
1322            switch (op1) {
1323              case 0:
1324                switch (crm) {
1325                  case 0:
1326                    switch (op2) {
1327                      case 0:
1328                        return MISCREG_MDRAR_EL1;
1329                      case 4:
1330                        return MISCREG_OSLAR_EL1;
1331                    }
1332                    break;
1333                  case 1:
1334                    switch (op2) {
1335                      case 4:
1336                        return MISCREG_OSLSR_EL1;
1337                    }
1338                    break;
1339                  case 3:
1340                    switch (op2) {
1341                      case 4:
1342                        return MISCREG_OSDLR_EL1;
1343                    }
1344                    break;
1345                  case 4:
1346                    switch (op2) {
1347                      case 4:
1348                        return MISCREG_DBGPRCR_EL1;
1349                    }
1350                    break;
1351                }
1352                break;
1353              case 2:
1354                switch (crm) {
1355                  case 0:
1356                    switch (op2) {
1357                      case 0:
1358                        return MISCREG_TEEHBR32_EL1;
1359                    }
1360                    break;
1361                }
1362                break;
1363            }
1364            break;
1365          case 7:
1366            switch (op1) {
1367              case 0:
1368                switch (crm) {
1369                  case 8:
1370                    switch (op2) {
1371                      case 6:
1372                        return MISCREG_DBGCLAIMSET_EL1;
1373                    }
1374                    break;
1375                  case 9:
1376                    switch (op2) {
1377                      case 6:
1378                        return MISCREG_DBGCLAIMCLR_EL1;
1379                    }
1380                    break;
1381                  case 14:
1382                    switch (op2) {
1383                      case 6:
1384                        return MISCREG_DBGAUTHSTATUS_EL1;
1385                    }
1386                    break;
1387                }
1388                break;
1389            }
1390            break;
1391        }
1392        break;
1393      case 3:
1394        switch (crn) {
1395          case 0:
1396            switch (op1) {
1397              case 0:
1398                switch (crm) {
1399                  case 0:
1400                    switch (op2) {
1401                      case 0:
1402                        return MISCREG_MIDR_EL1;
1403                      case 5:
1404                        return MISCREG_MPIDR_EL1;
1405                      case 6:
1406                        return MISCREG_REVIDR_EL1;
1407                    }
1408                    break;
1409                  case 1:
1410                    switch (op2) {
1411                      case 0:
1412                        return MISCREG_ID_PFR0_EL1;
1413                      case 1:
1414                        return MISCREG_ID_PFR1_EL1;
1415                      case 2:
1416                        return MISCREG_ID_DFR0_EL1;
1417                      case 3:
1418                        return MISCREG_ID_AFR0_EL1;
1419                      case 4:
1420                        return MISCREG_ID_MMFR0_EL1;
1421                      case 5:
1422                        return MISCREG_ID_MMFR1_EL1;
1423                      case 6:
1424                        return MISCREG_ID_MMFR2_EL1;
1425                      case 7:
1426                        return MISCREG_ID_MMFR3_EL1;
1427                    }
1428                    break;
1429                  case 2:
1430                    switch (op2) {
1431                      case 0:
1432                        return MISCREG_ID_ISAR0_EL1;
1433                      case 1:
1434                        return MISCREG_ID_ISAR1_EL1;
1435                      case 2:
1436                        return MISCREG_ID_ISAR2_EL1;
1437                      case 3:
1438                        return MISCREG_ID_ISAR3_EL1;
1439                      case 4:
1440                        return MISCREG_ID_ISAR4_EL1;
1441                      case 5:
1442                        return MISCREG_ID_ISAR5_EL1;
1443                    }
1444                    break;
1445                  case 3:
1446                    switch (op2) {
1447                      case 0:
1448                        return MISCREG_MVFR0_EL1;
1449                      case 1:
1450                        return MISCREG_MVFR1_EL1;
1451                      case 2:
1452                        return MISCREG_MVFR2_EL1;
1453                      case 3 ... 7:
1454                        return MISCREG_RAZ;
1455                    }
1456                    break;
1457                  case 4:
1458                    switch (op2) {
1459                      case 0:
1460                        return MISCREG_ID_AA64PFR0_EL1;
1461                      case 1:
1462                        return MISCREG_ID_AA64PFR1_EL1;
1463                      case 2 ... 7:
1464                        return MISCREG_RAZ;
1465                    }
1466                    break;
1467                  case 5:
1468                    switch (op2) {
1469                      case 0:
1470                        return MISCREG_ID_AA64DFR0_EL1;
1471                      case 1:
1472                        return MISCREG_ID_AA64DFR1_EL1;
1473                      case 4:
1474                        return MISCREG_ID_AA64AFR0_EL1;
1475                      case 5:
1476                        return MISCREG_ID_AA64AFR1_EL1;
1477                      case 2:
1478                      case 3:
1479                      case 6:
1480                      case 7:
1481                        return MISCREG_RAZ;
1482                    }
1483                    break;
1484                  case 6:
1485                    switch (op2) {
1486                      case 0:
1487                        return MISCREG_ID_AA64ISAR0_EL1;
1488                      case 1:
1489                        return MISCREG_ID_AA64ISAR1_EL1;
1490                      case 2 ... 7:
1491                        return MISCREG_RAZ;
1492                    }
1493                    break;
1494                  case 7:
1495                    switch (op2) {
1496                      case 0:
1497                        return MISCREG_ID_AA64MMFR0_EL1;
1498                      case 1:
1499                        return MISCREG_ID_AA64MMFR1_EL1;
1500                      case 2 ... 7:
1501                        return MISCREG_RAZ;
1502                    }
1503                    break;
1504                }
1505                break;
1506              case 1:
1507                switch (crm) {
1508                  case 0:
1509                    switch (op2) {
1510                      case 0:
1511                        return MISCREG_CCSIDR_EL1;
1512                      case 1:
1513                        return MISCREG_CLIDR_EL1;
1514                      case 7:
1515                        return MISCREG_AIDR_EL1;
1516                    }
1517                    break;
1518                }
1519                break;
1520              case 2:
1521                switch (crm) {
1522                  case 0:
1523                    switch (op2) {
1524                      case 0:
1525                        return MISCREG_CSSELR_EL1;
1526                    }
1527                    break;
1528                }
1529                break;
1530              case 3:
1531                switch (crm) {
1532                  case 0:
1533                    switch (op2) {
1534                      case 1:
1535                        return MISCREG_CTR_EL0;
1536                      case 7:
1537                        return MISCREG_DCZID_EL0;
1538                    }
1539                    break;
1540                }
1541                break;
1542              case 4:
1543                switch (crm) {
1544                  case 0:
1545                    switch (op2) {
1546                      case 0:
1547                        return MISCREG_VPIDR_EL2;
1548                      case 5:
1549                        return MISCREG_VMPIDR_EL2;
1550                    }
1551                    break;
1552                }
1553                break;
1554            }
1555            break;
1556          case 1:
1557            switch (op1) {
1558              case 0:
1559                switch (crm) {
1560                  case 0:
1561                    switch (op2) {
1562                      case 0:
1563                        return MISCREG_SCTLR_EL1;
1564                      case 1:
1565                        return MISCREG_ACTLR_EL1;
1566                      case 2:
1567                        return MISCREG_CPACR_EL1;
1568                    }
1569                    break;
1570                }
1571                break;
1572              case 4:
1573                switch (crm) {
1574                  case 0:
1575                    switch (op2) {
1576                      case 0:
1577                        return MISCREG_SCTLR_EL2;
1578                      case 1:
1579                        return MISCREG_ACTLR_EL2;
1580                    }
1581                    break;
1582                  case 1:
1583                    switch (op2) {
1584                      case 0:
1585                        return MISCREG_HCR_EL2;
1586                      case 1:
1587                        return MISCREG_MDCR_EL2;
1588                      case 2:
1589                        return MISCREG_CPTR_EL2;
1590                      case 3:
1591                        return MISCREG_HSTR_EL2;
1592                      case 7:
1593                        return MISCREG_HACR_EL2;
1594                    }
1595                    break;
1596                }
1597                break;
1598              case 6:
1599                switch (crm) {
1600                  case 0:
1601                    switch (op2) {
1602                      case 0:
1603                        return MISCREG_SCTLR_EL3;
1604                      case 1:
1605                        return MISCREG_ACTLR_EL3;
1606                    }
1607                    break;
1608                  case 1:
1609                    switch (op2) {
1610                      case 0:
1611                        return MISCREG_SCR_EL3;
1612                      case 1:
1613                        return MISCREG_SDER32_EL3;
1614                      case 2:
1615                        return MISCREG_CPTR_EL3;
1616                    }
1617                    break;
1618                  case 3:
1619                    switch (op2) {
1620                      case 1:
1621                        return MISCREG_MDCR_EL3;
1622                    }
1623                    break;
1624                }
1625                break;
1626            }
1627            break;
1628          case 2:
1629            switch (op1) {
1630              case 0:
1631                switch (crm) {
1632                  case 0:
1633                    switch (op2) {
1634                      case 0:
1635                        return MISCREG_TTBR0_EL1;
1636                      case 1:
1637                        return MISCREG_TTBR1_EL1;
1638                      case 2:
1639                        return MISCREG_TCR_EL1;
1640                    }
1641                    break;
1642                }
1643                break;
1644              case 4:
1645                switch (crm) {
1646                  case 0:
1647                    switch (op2) {
1648                      case 0:
1649                        return MISCREG_TTBR0_EL2;
1650                      case 2:
1651                        return MISCREG_TCR_EL2;
1652                    }
1653                    break;
1654                  case 1:
1655                    switch (op2) {
1656                      case 0:
1657                        return MISCREG_VTTBR_EL2;
1658                      case 2:
1659                        return MISCREG_VTCR_EL2;
1660                    }
1661                    break;
1662                }
1663                break;
1664              case 6:
1665                switch (crm) {
1666                  case 0:
1667                    switch (op2) {
1668                      case 0:
1669                        return MISCREG_TTBR0_EL3;
1670                      case 2:
1671                        return MISCREG_TCR_EL3;
1672                    }
1673                    break;
1674                }
1675                break;
1676            }
1677            break;
1678          case 3:
1679            switch (op1) {
1680              case 4:
1681                switch (crm) {
1682                  case 0:
1683                    switch (op2) {
1684                      case 0:
1685                        return MISCREG_DACR32_EL2;
1686                    }
1687                    break;
1688                }
1689                break;
1690            }
1691            break;
1692          case 4:
1693            switch (op1) {
1694              case 0:
1695                switch (crm) {
1696                  case 0:
1697                    switch (op2) {
1698                      case 0:
1699                        return MISCREG_SPSR_EL1;
1700                      case 1:
1701                        return MISCREG_ELR_EL1;
1702                    }
1703                    break;
1704                  case 1:
1705                    switch (op2) {
1706                      case 0:
1707                        return MISCREG_SP_EL0;
1708                    }
1709                    break;
1710                  case 2:
1711                    switch (op2) {
1712                      case 0:
1713                        return MISCREG_SPSEL;
1714                      case 2:
1715                        return MISCREG_CURRENTEL;
1716                    }
1717                    break;
1718                }
1719                break;
1720              case 3:
1721                switch (crm) {
1722                  case 2:
1723                    switch (op2) {
1724                      case 0:
1725                        return MISCREG_NZCV;
1726                      case 1:
1727                        return MISCREG_DAIF;
1728                    }
1729                    break;
1730                  case 4:
1731                    switch (op2) {
1732                      case 0:
1733                        return MISCREG_FPCR;
1734                      case 1:
1735                        return MISCREG_FPSR;
1736                    }
1737                    break;
1738                  case 5:
1739                    switch (op2) {
1740                      case 0:
1741                        return MISCREG_DSPSR_EL0;
1742                      case 1:
1743                        return MISCREG_DLR_EL0;
1744                    }
1745                    break;
1746                }
1747                break;
1748              case 4:
1749                switch (crm) {
1750                  case 0:
1751                    switch (op2) {
1752                      case 0:
1753                        return MISCREG_SPSR_EL2;
1754                      case 1:
1755                        return MISCREG_ELR_EL2;
1756                    }
1757                    break;
1758                  case 1:
1759                    switch (op2) {
1760                      case 0:
1761                        return MISCREG_SP_EL1;
1762                    }
1763                    break;
1764                  case 3:
1765                    switch (op2) {
1766                      case 0:
1767                        return MISCREG_SPSR_IRQ_AA64;
1768                      case 1:
1769                        return MISCREG_SPSR_ABT_AA64;
1770                      case 2:
1771                        return MISCREG_SPSR_UND_AA64;
1772                      case 3:
1773                        return MISCREG_SPSR_FIQ_AA64;
1774                    }
1775                    break;
1776                }
1777                break;
1778              case 6:
1779                switch (crm) {
1780                  case 0:
1781                    switch (op2) {
1782                      case 0:
1783                        return MISCREG_SPSR_EL3;
1784                      case 1:
1785                        return MISCREG_ELR_EL3;
1786                    }
1787                    break;
1788                  case 1:
1789                    switch (op2) {
1790                      case 0:
1791                        return MISCREG_SP_EL2;
1792                    }
1793                    break;
1794                }
1795                break;
1796            }
1797            break;
1798          case 5:
1799            switch (op1) {
1800              case 0:
1801                switch (crm) {
1802                  case 1:
1803                    switch (op2) {
1804                      case 0:
1805                        return MISCREG_AFSR0_EL1;
1806                      case 1:
1807                        return MISCREG_AFSR1_EL1;
1808                    }
1809                    break;
1810                  case 2:
1811                    switch (op2) {
1812                      case 0:
1813                        return MISCREG_ESR_EL1;
1814                    }
1815                    break;
1816                }
1817                break;
1818              case 4:
1819                switch (crm) {
1820                  case 0:
1821                    switch (op2) {
1822                      case 1:
1823                        return MISCREG_IFSR32_EL2;
1824                    }
1825                    break;
1826                  case 1:
1827                    switch (op2) {
1828                      case 0:
1829                        return MISCREG_AFSR0_EL2;
1830                      case 1:
1831                        return MISCREG_AFSR1_EL2;
1832                    }
1833                    break;
1834                  case 2:
1835                    switch (op2) {
1836                      case 0:
1837                        return MISCREG_ESR_EL2;
1838                    }
1839                    break;
1840                  case 3:
1841                    switch (op2) {
1842                      case 0:
1843                        return MISCREG_FPEXC32_EL2;
1844                    }
1845                    break;
1846                }
1847                break;
1848              case 6:
1849                switch (crm) {
1850                  case 1:
1851                    switch (op2) {
1852                      case 0:
1853                        return MISCREG_AFSR0_EL3;
1854                      case 1:
1855                        return MISCREG_AFSR1_EL3;
1856                    }
1857                    break;
1858                  case 2:
1859                    switch (op2) {
1860                      case 0:
1861                        return MISCREG_ESR_EL3;
1862                    }
1863                    break;
1864                }
1865                break;
1866            }
1867            break;
1868          case 6:
1869            switch (op1) {
1870              case 0:
1871                switch (crm) {
1872                  case 0:
1873                    switch (op2) {
1874                      case 0:
1875                        return MISCREG_FAR_EL1;
1876                    }
1877                    break;
1878                }
1879                break;
1880              case 4:
1881                switch (crm) {
1882                  case 0:
1883                    switch (op2) {
1884                      case 0:
1885                        return MISCREG_FAR_EL2;
1886                      case 4:
1887                        return MISCREG_HPFAR_EL2;
1888                    }
1889                    break;
1890                }
1891                break;
1892              case 6:
1893                switch (crm) {
1894                  case 0:
1895                    switch (op2) {
1896                      case 0:
1897                        return MISCREG_FAR_EL3;
1898                    }
1899                    break;
1900                }
1901                break;
1902            }
1903            break;
1904          case 7:
1905            switch (op1) {
1906              case 0:
1907                switch (crm) {
1908                  case 4:
1909                    switch (op2) {
1910                      case 0:
1911                        return MISCREG_PAR_EL1;
1912                    }
1913                    break;
1914                }
1915                break;
1916            }
1917            break;
1918          case 9:
1919            switch (op1) {
1920              case 0:
1921                switch (crm) {
1922                  case 14:
1923                    switch (op2) {
1924                      case 1:
1925                        return MISCREG_PMINTENSET_EL1;
1926                      case 2:
1927                        return MISCREG_PMINTENCLR_EL1;
1928                    }
1929                    break;
1930                }
1931                break;
1932              case 3:
1933                switch (crm) {
1934                  case 12:
1935                    switch (op2) {
1936                      case 0:
1937                        return MISCREG_PMCR_EL0;
1938                      case 1:
1939                        return MISCREG_PMCNTENSET_EL0;
1940                      case 2:
1941                        return MISCREG_PMCNTENCLR_EL0;
1942                      case 3:
1943                        return MISCREG_PMOVSCLR_EL0;
1944                      case 4:
1945                        return MISCREG_PMSWINC_EL0;
1946                      case 5:
1947                        return MISCREG_PMSELR_EL0;
1948                      case 6:
1949                        return MISCREG_PMCEID0_EL0;
1950                      case 7:
1951                        return MISCREG_PMCEID1_EL0;
1952                    }
1953                    break;
1954                  case 13:
1955                    switch (op2) {
1956                      case 0:
1957                        return MISCREG_PMCCNTR_EL0;
1958                      case 1:
1959                        return MISCREG_PMXEVTYPER_EL0;
1960                      case 2:
1961                        return MISCREG_PMXEVCNTR_EL0;
1962                    }
1963                    break;
1964                  case 14:
1965                    switch (op2) {
1966                      case 0:
1967                        return MISCREG_PMUSERENR_EL0;
1968                      case 3:
1969                        return MISCREG_PMOVSSET_EL0;
1970                    }
1971                    break;
1972                }
1973                break;
1974            }
1975            break;
1976          case 10:
1977            switch (op1) {
1978              case 0:
1979                switch (crm) {
1980                  case 2:
1981                    switch (op2) {
1982                      case 0:
1983                        return MISCREG_MAIR_EL1;
1984                    }
1985                    break;
1986                  case 3:
1987                    switch (op2) {
1988                      case 0:
1989                        return MISCREG_AMAIR_EL1;
1990                    }
1991                    break;
1992                }
1993                break;
1994              case 4:
1995                switch (crm) {
1996                  case 2:
1997                    switch (op2) {
1998                      case 0:
1999                        return MISCREG_MAIR_EL2;
2000                    }
2001                    break;
2002                  case 3:
2003                    switch (op2) {
2004                      case 0:
2005                        return MISCREG_AMAIR_EL2;
2006                    }
2007                    break;
2008                }
2009                break;
2010              case 6:
2011                switch (crm) {
2012                  case 2:
2013                    switch (op2) {
2014                      case 0:
2015                        return MISCREG_MAIR_EL3;
2016                    }
2017                    break;
2018                  case 3:
2019                    switch (op2) {
2020                      case 0:
2021                        return MISCREG_AMAIR_EL3;
2022                    }
2023                    break;
2024                }
2025                break;
2026            }
2027            break;
2028          case 11:
2029            switch (op1) {
2030              case 1:
2031                switch (crm) {
2032                  case 0:
2033                    switch (op2) {
2034                      case 2:
2035                        return MISCREG_L2CTLR_EL1;
2036                      case 3:
2037                        return MISCREG_L2ECTLR_EL1;
2038                    }
2039                    break;
2040                }
2041                break;
2042            }
2043            break;
2044          case 12:
2045            switch (op1) {
2046              case 0:
2047                switch (crm) {
2048                  case 0:
2049                    switch (op2) {
2050                      case 0:
2051                        return MISCREG_VBAR_EL1;
2052                      case 1:
2053                        return MISCREG_RVBAR_EL1;
2054                    }
2055                    break;
2056                  case 1:
2057                    switch (op2) {
2058                      case 0:
2059                        return MISCREG_ISR_EL1;
2060                    }
2061                    break;
2062                }
2063                break;
2064              case 4:
2065                switch (crm) {
2066                  case 0:
2067                    switch (op2) {
2068                      case 0:
2069                        return MISCREG_VBAR_EL2;
2070                      case 1:
2071                        return MISCREG_RVBAR_EL2;
2072                    }
2073                    break;
2074                }
2075                break;
2076              case 6:
2077                switch (crm) {
2078                  case 0:
2079                    switch (op2) {
2080                      case 0:
2081                        return MISCREG_VBAR_EL3;
2082                      case 1:
2083                        return MISCREG_RVBAR_EL3;
2084                      case 2:
2085                        return MISCREG_RMR_EL3;
2086                    }
2087                    break;
2088                }
2089                break;
2090            }
2091            break;
2092          case 13:
2093            switch (op1) {
2094              case 0:
2095                switch (crm) {
2096                  case 0:
2097                    switch (op2) {
2098                      case 1:
2099                        return MISCREG_CONTEXTIDR_EL1;
2100                      case 4:
2101                        return MISCREG_TPIDR_EL1;
2102                    }
2103                    break;
2104                }
2105                break;
2106              case 3:
2107                switch (crm) {
2108                  case 0:
2109                    switch (op2) {
2110                      case 2:
2111                        return MISCREG_TPIDR_EL0;
2112                      case 3:
2113                        return MISCREG_TPIDRRO_EL0;
2114                    }
2115                    break;
2116                }
2117                break;
2118              case 4:
2119                switch (crm) {
2120                  case 0:
2121                    switch (op2) {
2122                      case 1:
2123                        return MISCREG_CONTEXTIDR_EL2;
2124                      case 2:
2125                        return MISCREG_TPIDR_EL2;
2126                    }
2127                    break;
2128                }
2129                break;
2130              case 6:
2131                switch (crm) {
2132                  case 0:
2133                    switch (op2) {
2134                      case 2:
2135                        return MISCREG_TPIDR_EL3;
2136                    }
2137                    break;
2138                }
2139                break;
2140            }
2141            break;
2142          case 14:
2143            switch (op1) {
2144              case 0:
2145                switch (crm) {
2146                  case 1:
2147                    switch (op2) {
2148                      case 0:
2149                        return MISCREG_CNTKCTL_EL1;
2150                    }
2151                    break;
2152                }
2153                break;
2154              case 3:
2155                switch (crm) {
2156                  case 0:
2157                    switch (op2) {
2158                      case 0:
2159                        return MISCREG_CNTFRQ_EL0;
2160                      case 1:
2161                        return MISCREG_CNTPCT_EL0;
2162                      case 2:
2163                        return MISCREG_CNTVCT_EL0;
2164                    }
2165                    break;
2166                  case 2:
2167                    switch (op2) {
2168                      case 0:
2169                        return MISCREG_CNTP_TVAL_EL0;
2170                      case 1:
2171                        return MISCREG_CNTP_CTL_EL0;
2172                      case 2:
2173                        return MISCREG_CNTP_CVAL_EL0;
2174                    }
2175                    break;
2176                  case 3:
2177                    switch (op2) {
2178                      case 0:
2179                        return MISCREG_CNTV_TVAL_EL0;
2180                      case 1:
2181                        return MISCREG_CNTV_CTL_EL0;
2182                      case 2:
2183                        return MISCREG_CNTV_CVAL_EL0;
2184                    }
2185                    break;
2186                  case 8:
2187                    switch (op2) {
2188                      case 0:
2189                        return MISCREG_PMEVCNTR0_EL0;
2190                      case 1:
2191                        return MISCREG_PMEVCNTR1_EL0;
2192                      case 2:
2193                        return MISCREG_PMEVCNTR2_EL0;
2194                      case 3:
2195                        return MISCREG_PMEVCNTR3_EL0;
2196                      case 4:
2197                        return MISCREG_PMEVCNTR4_EL0;
2198                      case 5:
2199                        return MISCREG_PMEVCNTR5_EL0;
2200                    }
2201                    break;
2202                  case 12:
2203                    switch (op2) {
2204                      case 0:
2205                        return MISCREG_PMEVTYPER0_EL0;
2206                      case 1:
2207                        return MISCREG_PMEVTYPER1_EL0;
2208                      case 2:
2209                        return MISCREG_PMEVTYPER2_EL0;
2210                      case 3:
2211                        return MISCREG_PMEVTYPER3_EL0;
2212                      case 4:
2213                        return MISCREG_PMEVTYPER4_EL0;
2214                      case 5:
2215                        return MISCREG_PMEVTYPER5_EL0;
2216                    }
2217                    break;
2218                  case 15:
2219                    switch (op2) {
2220                      case 7:
2221                        return MISCREG_PMCCFILTR_EL0;
2222                    }
2223                }
2224                break;
2225              case 4:
2226                switch (crm) {
2227                  case 0:
2228                    switch (op2) {
2229                      case 3:
2230                        return MISCREG_CNTVOFF_EL2;
2231                    }
2232                    break;
2233                  case 1:
2234                    switch (op2) {
2235                      case 0:
2236                        return MISCREG_CNTHCTL_EL2;
2237                    }
2238                    break;
2239                  case 2:
2240                    switch (op2) {
2241                      case 0:
2242                        return MISCREG_CNTHP_TVAL_EL2;
2243                      case 1:
2244                        return MISCREG_CNTHP_CTL_EL2;
2245                      case 2:
2246                        return MISCREG_CNTHP_CVAL_EL2;
2247                    }
2248                    break;
2249                }
2250                break;
2251              case 7:
2252                switch (crm) {
2253                  case 2:
2254                    switch (op2) {
2255                      case 0:
2256                        return MISCREG_CNTPS_TVAL_EL1;
2257                      case 1:
2258                        return MISCREG_CNTPS_CTL_EL1;
2259                      case 2:
2260                        return MISCREG_CNTPS_CVAL_EL1;
2261                    }
2262                    break;
2263                }
2264                break;
2265            }
2266            break;
2267          case 15:
2268            switch (op1) {
2269              case 0:
2270                switch (crm) {
2271                  case 0:
2272                    switch (op2) {
2273                      case 0:
2274                        return MISCREG_IL1DATA0_EL1;
2275                      case 1:
2276                        return MISCREG_IL1DATA1_EL1;
2277                      case 2:
2278                        return MISCREG_IL1DATA2_EL1;
2279                      case 3:
2280                        return MISCREG_IL1DATA3_EL1;
2281                    }
2282                    break;
2283                  case 1:
2284                    switch (op2) {
2285                      case 0:
2286                        return MISCREG_DL1DATA0_EL1;
2287                      case 1:
2288                        return MISCREG_DL1DATA1_EL1;
2289                      case 2:
2290                        return MISCREG_DL1DATA2_EL1;
2291                      case 3:
2292                        return MISCREG_DL1DATA3_EL1;
2293                      case 4:
2294                        return MISCREG_DL1DATA4_EL1;
2295                    }
2296                    break;
2297                }
2298                break;
2299              case 1:
2300                switch (crm) {
2301                  case 0:
2302                    switch (op2) {
2303                      case 0:
2304                        return MISCREG_L2ACTLR_EL1;
2305                    }
2306                    break;
2307                  case 2:
2308                    switch (op2) {
2309                      case 0:
2310                        return MISCREG_CPUACTLR_EL1;
2311                      case 1:
2312                        return MISCREG_CPUECTLR_EL1;
2313                      case 2:
2314                        return MISCREG_CPUMERRSR_EL1;
2315                      case 3:
2316                        return MISCREG_L2MERRSR_EL1;
2317                    }
2318                    break;
2319                  case 3:
2320                    switch (op2) {
2321                      case 0:
2322                        return MISCREG_CBAR_EL1;
2323
2324                    }
2325                    break;
2326                }
2327                break;
2328            }
2329            break;
2330        }
2331        break;
2332    }
2333
2334    return MISCREG_UNKNOWN;
2335}
2336
2337bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2338
2339void
2340ISA::initializeMiscRegMetadata()
2341{
2342    // the MiscReg metadata tables are shared across all instances of the
2343    // ISA object, so there's no need to initialize them multiple times.
2344    static bool completed = false;
2345    if (completed)
2346        return;
2347
2348    /**
2349     * Some registers alias with others, and therefore need to be translated.
2350     * When two mapping registers are given, they are the 32b lower and
2351     * upper halves, respectively, of the 64b register being mapped.
2352     * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2353     *
2354     * NAM = "not architecturally mandated",
2355     * from ARM DDI 0487A.i, template text
2356     * "AArch64 System register ___ can be mapped to
2357     *  AArch32 System register ___, but this is not
2358     *  architecturally mandated."
2359     */
2360
2361    InitReg(MISCREG_CPSR)
2362      .allPrivileges();
2363    InitReg(MISCREG_SPSR)
2364      .allPrivileges();
2365    InitReg(MISCREG_SPSR_FIQ)
2366      .allPrivileges();
2367    InitReg(MISCREG_SPSR_IRQ)
2368      .allPrivileges();
2369    InitReg(MISCREG_SPSR_SVC)
2370      .allPrivileges();
2371    InitReg(MISCREG_SPSR_MON)
2372      .allPrivileges();
2373    InitReg(MISCREG_SPSR_ABT)
2374      .allPrivileges();
2375    InitReg(MISCREG_SPSR_HYP)
2376      .allPrivileges();
2377    InitReg(MISCREG_SPSR_UND)
2378      .allPrivileges();
2379    InitReg(MISCREG_ELR_HYP)
2380      .allPrivileges();
2381    InitReg(MISCREG_FPSID)
2382      .allPrivileges();
2383    InitReg(MISCREG_FPSCR)
2384      .allPrivileges();
2385    InitReg(MISCREG_MVFR1)
2386      .allPrivileges();
2387    InitReg(MISCREG_MVFR0)
2388      .allPrivileges();
2389    InitReg(MISCREG_FPEXC)
2390      .allPrivileges();
2391
2392    // Helper registers
2393    InitReg(MISCREG_CPSR_MODE)
2394      .allPrivileges();
2395    InitReg(MISCREG_CPSR_Q)
2396      .allPrivileges();
2397    InitReg(MISCREG_FPSCR_EXC)
2398      .allPrivileges();
2399    InitReg(MISCREG_FPSCR_QC)
2400      .allPrivileges();
2401    InitReg(MISCREG_LOCKADDR)
2402      .allPrivileges();
2403    InitReg(MISCREG_LOCKFLAG)
2404      .allPrivileges();
2405    InitReg(MISCREG_PRRR_MAIR0)
2406      .mutex()
2407      .banked();
2408    InitReg(MISCREG_PRRR_MAIR0_NS)
2409      .mutex()
2410      .bankedChild();
2411    InitReg(MISCREG_PRRR_MAIR0_S)
2412      .mutex()
2413      .bankedChild();
2414    InitReg(MISCREG_NMRR_MAIR1)
2415      .mutex()
2416      .banked();
2417    InitReg(MISCREG_NMRR_MAIR1_NS)
2418      .mutex()
2419      .bankedChild();
2420    InitReg(MISCREG_NMRR_MAIR1_S)
2421      .mutex()
2422      .bankedChild();
2423    InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2424      .mutex();
2425    InitReg(MISCREG_SCTLR_RST)
2426      .allPrivileges();
2427    InitReg(MISCREG_SEV_MAILBOX)
2428      .allPrivileges();
2429
2430    // AArch32 CP14 registers
2431    InitReg(MISCREG_DBGDIDR)
2432      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2433    InitReg(MISCREG_DBGDSCRint)
2434      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2435    InitReg(MISCREG_DBGDCCINT)
2436      .unimplemented()
2437      .allPrivileges();
2438    InitReg(MISCREG_DBGDTRTXint)
2439      .unimplemented()
2440      .allPrivileges();
2441    InitReg(MISCREG_DBGDTRRXint)
2442      .unimplemented()
2443      .allPrivileges();
2444    InitReg(MISCREG_DBGWFAR)
2445      .unimplemented()
2446      .allPrivileges();
2447    InitReg(MISCREG_DBGVCR)
2448      .unimplemented()
2449      .allPrivileges();
2450    InitReg(MISCREG_DBGDTRRXext)
2451      .unimplemented()
2452      .allPrivileges();
2453    InitReg(MISCREG_DBGDSCRext)
2454      .unimplemented()
2455      .warnNotFail()
2456      .allPrivileges();
2457    InitReg(MISCREG_DBGDTRTXext)
2458      .unimplemented()
2459      .allPrivileges();
2460    InitReg(MISCREG_DBGOSECCR)
2461      .unimplemented()
2462      .allPrivileges();
2463    InitReg(MISCREG_DBGBVR0)
2464      .unimplemented()
2465      .allPrivileges();
2466    InitReg(MISCREG_DBGBVR1)
2467      .unimplemented()
2468      .allPrivileges();
2469    InitReg(MISCREG_DBGBVR2)
2470      .unimplemented()
2471      .allPrivileges();
2472    InitReg(MISCREG_DBGBVR3)
2473      .unimplemented()
2474      .allPrivileges();
2475    InitReg(MISCREG_DBGBVR4)
2476      .unimplemented()
2477      .allPrivileges();
2478    InitReg(MISCREG_DBGBVR5)
2479      .unimplemented()
2480      .allPrivileges();
2481    InitReg(MISCREG_DBGBCR0)
2482      .unimplemented()
2483      .allPrivileges();
2484    InitReg(MISCREG_DBGBCR1)
2485      .unimplemented()
2486      .allPrivileges();
2487    InitReg(MISCREG_DBGBCR2)
2488      .unimplemented()
2489      .allPrivileges();
2490    InitReg(MISCREG_DBGBCR3)
2491      .unimplemented()
2492      .allPrivileges();
2493    InitReg(MISCREG_DBGBCR4)
2494      .unimplemented()
2495      .allPrivileges();
2496    InitReg(MISCREG_DBGBCR5)
2497      .unimplemented()
2498      .allPrivileges();
2499    InitReg(MISCREG_DBGWVR0)
2500      .unimplemented()
2501      .allPrivileges();
2502    InitReg(MISCREG_DBGWVR1)
2503      .unimplemented()
2504      .allPrivileges();
2505    InitReg(MISCREG_DBGWVR2)
2506      .unimplemented()
2507      .allPrivileges();
2508    InitReg(MISCREG_DBGWVR3)
2509      .unimplemented()
2510      .allPrivileges();
2511    InitReg(MISCREG_DBGWCR0)
2512      .unimplemented()
2513      .allPrivileges();
2514    InitReg(MISCREG_DBGWCR1)
2515      .unimplemented()
2516      .allPrivileges();
2517    InitReg(MISCREG_DBGWCR2)
2518      .unimplemented()
2519      .allPrivileges();
2520    InitReg(MISCREG_DBGWCR3)
2521      .unimplemented()
2522      .allPrivileges();
2523    InitReg(MISCREG_DBGDRAR)
2524      .unimplemented()
2525      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2526    InitReg(MISCREG_DBGBXVR4)
2527      .unimplemented()
2528      .allPrivileges();
2529    InitReg(MISCREG_DBGBXVR5)
2530      .unimplemented()
2531      .allPrivileges();
2532    InitReg(MISCREG_DBGOSLAR)
2533      .unimplemented()
2534      .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2535    InitReg(MISCREG_DBGOSLSR)
2536      .unimplemented()
2537      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2538    InitReg(MISCREG_DBGOSDLR)
2539      .unimplemented()
2540      .allPrivileges();
2541    InitReg(MISCREG_DBGPRCR)
2542      .unimplemented()
2543      .allPrivileges();
2544    InitReg(MISCREG_DBGDSAR)
2545      .unimplemented()
2546      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2547    InitReg(MISCREG_DBGCLAIMSET)
2548      .unimplemented()
2549      .allPrivileges();
2550    InitReg(MISCREG_DBGCLAIMCLR)
2551      .unimplemented()
2552      .allPrivileges();
2553    InitReg(MISCREG_DBGAUTHSTATUS)
2554      .unimplemented()
2555      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2556    InitReg(MISCREG_DBGDEVID2)
2557      .unimplemented()
2558      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2559    InitReg(MISCREG_DBGDEVID1)
2560      .unimplemented()
2561      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2562    InitReg(MISCREG_DBGDEVID0)
2563      .unimplemented()
2564      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2565    InitReg(MISCREG_TEECR)
2566      .unimplemented()
2567      .allPrivileges();
2568    InitReg(MISCREG_JIDR)
2569      .allPrivileges();
2570    InitReg(MISCREG_TEEHBR)
2571      .allPrivileges();
2572    InitReg(MISCREG_JOSCR)
2573      .allPrivileges();
2574    InitReg(MISCREG_JMCR)
2575      .allPrivileges();
2576
2577    // AArch32 CP15 registers
2578    InitReg(MISCREG_MIDR)
2579      .allPrivileges().exceptUserMode().writes(0);
2580    InitReg(MISCREG_CTR)
2581      .allPrivileges().exceptUserMode().writes(0);
2582    InitReg(MISCREG_TCMTR)
2583      .allPrivileges().exceptUserMode().writes(0);
2584    InitReg(MISCREG_TLBTR)
2585      .allPrivileges().exceptUserMode().writes(0);
2586    InitReg(MISCREG_MPIDR)
2587      .allPrivileges().exceptUserMode().writes(0);
2588    InitReg(MISCREG_REVIDR)
2589      .unimplemented()
2590      .warnNotFail()
2591      .allPrivileges().exceptUserMode().writes(0);
2592    InitReg(MISCREG_ID_PFR0)
2593      .allPrivileges().exceptUserMode().writes(0);
2594    InitReg(MISCREG_ID_PFR1)
2595      .allPrivileges().exceptUserMode().writes(0);
2596    InitReg(MISCREG_ID_DFR0)
2597      .allPrivileges().exceptUserMode().writes(0);
2598    InitReg(MISCREG_ID_AFR0)
2599      .allPrivileges().exceptUserMode().writes(0);
2600    InitReg(MISCREG_ID_MMFR0)
2601      .allPrivileges().exceptUserMode().writes(0);
2602    InitReg(MISCREG_ID_MMFR1)
2603      .allPrivileges().exceptUserMode().writes(0);
2604    InitReg(MISCREG_ID_MMFR2)
2605      .allPrivileges().exceptUserMode().writes(0);
2606    InitReg(MISCREG_ID_MMFR3)
2607      .allPrivileges().exceptUserMode().writes(0);
2608    InitReg(MISCREG_ID_ISAR0)
2609      .allPrivileges().exceptUserMode().writes(0);
2610    InitReg(MISCREG_ID_ISAR1)
2611      .allPrivileges().exceptUserMode().writes(0);
2612    InitReg(MISCREG_ID_ISAR2)
2613      .allPrivileges().exceptUserMode().writes(0);
2614    InitReg(MISCREG_ID_ISAR3)
2615      .allPrivileges().exceptUserMode().writes(0);
2616    InitReg(MISCREG_ID_ISAR4)
2617      .allPrivileges().exceptUserMode().writes(0);
2618    InitReg(MISCREG_ID_ISAR5)
2619      .allPrivileges().exceptUserMode().writes(0);
2620    InitReg(MISCREG_CCSIDR)
2621      .allPrivileges().exceptUserMode().writes(0);
2622    InitReg(MISCREG_CLIDR)
2623      .allPrivileges().exceptUserMode().writes(0);
2624    InitReg(MISCREG_AIDR)
2625      .allPrivileges().exceptUserMode().writes(0);
2626    InitReg(MISCREG_CSSELR)
2627      .banked();
2628    InitReg(MISCREG_CSSELR_NS)
2629      .bankedChild()
2630      .nonSecure().exceptUserMode();
2631    InitReg(MISCREG_CSSELR_S)
2632      .bankedChild()
2633      .secure().exceptUserMode();
2634    InitReg(MISCREG_VPIDR)
2635      .hyp().monNonSecure();
2636    InitReg(MISCREG_VMPIDR)
2637      .hyp().monNonSecure();
2638    InitReg(MISCREG_SCTLR)
2639      .banked();
2640    InitReg(MISCREG_SCTLR_NS)
2641      .bankedChild()
2642      .nonSecure().exceptUserMode();
2643    InitReg(MISCREG_SCTLR_S)
2644      .bankedChild()
2645      .secure().exceptUserMode();
2646    InitReg(MISCREG_ACTLR)
2647      .banked();
2648    InitReg(MISCREG_ACTLR_NS)
2649      .bankedChild()
2650      .nonSecure().exceptUserMode();
2651    InitReg(MISCREG_ACTLR_S)
2652      .bankedChild()
2653      .secure().exceptUserMode();
2654    InitReg(MISCREG_CPACR)
2655      .allPrivileges().exceptUserMode();
2656    InitReg(MISCREG_SCR)
2657      .mon().secure().exceptUserMode()
2658      .res0(0xff40)  // [31:16], [6]
2659      .res1(0x0030); // [5:4]
2660    InitReg(MISCREG_SDER)
2661      .mon();
2662    InitReg(MISCREG_NSACR)
2663      .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2664    InitReg(MISCREG_HSCTLR)
2665      .hyp().monNonSecure();
2666    InitReg(MISCREG_HACTLR)
2667      .hyp().monNonSecure();
2668    InitReg(MISCREG_HCR)
2669      .hyp().monNonSecure();
2670    InitReg(MISCREG_HDCR)
2671      .hyp().monNonSecure();
2672    InitReg(MISCREG_HCPTR)
2673      .hyp().monNonSecure();
2674    InitReg(MISCREG_HSTR)
2675      .hyp().monNonSecure();
2676    InitReg(MISCREG_HACR)
2677      .unimplemented()
2678      .warnNotFail()
2679      .hyp().monNonSecure();
2680    InitReg(MISCREG_TTBR0)
2681      .banked();
2682    InitReg(MISCREG_TTBR0_NS)
2683      .bankedChild()
2684      .nonSecure().exceptUserMode();
2685    InitReg(MISCREG_TTBR0_S)
2686      .bankedChild()
2687      .secure().exceptUserMode();
2688    InitReg(MISCREG_TTBR1)
2689      .banked();
2690    InitReg(MISCREG_TTBR1_NS)
2691      .bankedChild()
2692      .nonSecure().exceptUserMode();
2693    InitReg(MISCREG_TTBR1_S)
2694      .bankedChild()
2695      .secure().exceptUserMode();
2696    InitReg(MISCREG_TTBCR)
2697      .banked();
2698    InitReg(MISCREG_TTBCR_NS)
2699      .bankedChild()
2700      .nonSecure().exceptUserMode();
2701    InitReg(MISCREG_TTBCR_S)
2702      .bankedChild()
2703      .secure().exceptUserMode();
2704    InitReg(MISCREG_HTCR)
2705      .hyp().monNonSecure();
2706    InitReg(MISCREG_VTCR)
2707      .hyp().monNonSecure();
2708    InitReg(MISCREG_DACR)
2709      .banked();
2710    InitReg(MISCREG_DACR_NS)
2711      .bankedChild()
2712      .nonSecure().exceptUserMode();
2713    InitReg(MISCREG_DACR_S)
2714      .bankedChild()
2715      .secure().exceptUserMode();
2716    InitReg(MISCREG_DFSR)
2717      .banked();
2718    InitReg(MISCREG_DFSR_NS)
2719      .bankedChild()
2720      .nonSecure().exceptUserMode();
2721    InitReg(MISCREG_DFSR_S)
2722      .bankedChild()
2723      .secure().exceptUserMode();
2724    InitReg(MISCREG_IFSR)
2725      .banked();
2726    InitReg(MISCREG_IFSR_NS)
2727      .bankedChild()
2728      .nonSecure().exceptUserMode();
2729    InitReg(MISCREG_IFSR_S)
2730      .bankedChild()
2731      .secure().exceptUserMode();
2732    InitReg(MISCREG_ADFSR)
2733      .unimplemented()
2734      .warnNotFail()
2735      .banked();
2736    InitReg(MISCREG_ADFSR_NS)
2737      .unimplemented()
2738      .warnNotFail()
2739      .bankedChild()
2740      .nonSecure().exceptUserMode();
2741    InitReg(MISCREG_ADFSR_S)
2742      .unimplemented()
2743      .warnNotFail()
2744      .bankedChild()
2745      .secure().exceptUserMode();
2746    InitReg(MISCREG_AIFSR)
2747      .unimplemented()
2748      .warnNotFail()
2749      .banked();
2750    InitReg(MISCREG_AIFSR_NS)
2751      .unimplemented()
2752      .warnNotFail()
2753      .bankedChild()
2754      .nonSecure().exceptUserMode();
2755    InitReg(MISCREG_AIFSR_S)
2756      .unimplemented()
2757      .warnNotFail()
2758      .bankedChild()
2759      .secure().exceptUserMode();
2760    InitReg(MISCREG_HADFSR)
2761      .hyp().monNonSecure();
2762    InitReg(MISCREG_HAIFSR)
2763      .hyp().monNonSecure();
2764    InitReg(MISCREG_HSR)
2765      .hyp().monNonSecure();
2766    InitReg(MISCREG_DFAR)
2767      .banked();
2768    InitReg(MISCREG_DFAR_NS)
2769      .bankedChild()
2770      .nonSecure().exceptUserMode();
2771    InitReg(MISCREG_DFAR_S)
2772      .bankedChild()
2773      .secure().exceptUserMode();
2774    InitReg(MISCREG_IFAR)
2775      .banked();
2776    InitReg(MISCREG_IFAR_NS)
2777      .bankedChild()
2778      .nonSecure().exceptUserMode();
2779    InitReg(MISCREG_IFAR_S)
2780      .bankedChild()
2781      .secure().exceptUserMode();
2782    InitReg(MISCREG_HDFAR)
2783      .hyp().monNonSecure();
2784    InitReg(MISCREG_HIFAR)
2785      .hyp().monNonSecure();
2786    InitReg(MISCREG_HPFAR)
2787      .hyp().monNonSecure();
2788    InitReg(MISCREG_ICIALLUIS)
2789      .unimplemented()
2790      .warnNotFail()
2791      .writes(1).exceptUserMode();
2792    InitReg(MISCREG_BPIALLIS)
2793      .unimplemented()
2794      .warnNotFail()
2795      .writes(1).exceptUserMode();
2796    InitReg(MISCREG_PAR)
2797      .banked();
2798    InitReg(MISCREG_PAR_NS)
2799      .bankedChild()
2800      .nonSecure().exceptUserMode();
2801    InitReg(MISCREG_PAR_S)
2802      .bankedChild()
2803      .secure().exceptUserMode();
2804    InitReg(MISCREG_ICIALLU)
2805      .writes(1).exceptUserMode();
2806    InitReg(MISCREG_ICIMVAU)
2807      .unimplemented()
2808      .warnNotFail()
2809      .writes(1).exceptUserMode();
2810    InitReg(MISCREG_CP15ISB)
2811      .writes(1);
2812    InitReg(MISCREG_BPIALL)
2813      .unimplemented()
2814      .warnNotFail()
2815      .writes(1).exceptUserMode();
2816    InitReg(MISCREG_BPIMVA)
2817      .unimplemented()
2818      .warnNotFail()
2819      .writes(1).exceptUserMode();
2820    InitReg(MISCREG_DCIMVAC)
2821      .unimplemented()
2822      .warnNotFail()
2823      .writes(1).exceptUserMode();
2824    InitReg(MISCREG_DCISW)
2825      .unimplemented()
2826      .warnNotFail()
2827      .writes(1).exceptUserMode();
2828    InitReg(MISCREG_ATS1CPR)
2829      .writes(1).exceptUserMode();
2830    InitReg(MISCREG_ATS1CPW)
2831      .writes(1).exceptUserMode();
2832    InitReg(MISCREG_ATS1CUR)
2833      .writes(1).exceptUserMode();
2834    InitReg(MISCREG_ATS1CUW)
2835      .writes(1).exceptUserMode();
2836    InitReg(MISCREG_ATS12NSOPR)
2837      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2838    InitReg(MISCREG_ATS12NSOPW)
2839      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2840    InitReg(MISCREG_ATS12NSOUR)
2841      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2842    InitReg(MISCREG_ATS12NSOUW)
2843      .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2844    InitReg(MISCREG_DCCMVAC)
2845      .writes(1).exceptUserMode();
2846    InitReg(MISCREG_DCCSW)
2847      .unimplemented()
2848      .warnNotFail()
2849      .writes(1).exceptUserMode();
2850    InitReg(MISCREG_CP15DSB)
2851      .writes(1);
2852    InitReg(MISCREG_CP15DMB)
2853      .writes(1);
2854    InitReg(MISCREG_DCCMVAU)
2855      .unimplemented()
2856      .warnNotFail()
2857      .writes(1).exceptUserMode();
2858    InitReg(MISCREG_DCCIMVAC)
2859      .unimplemented()
2860      .warnNotFail()
2861      .writes(1).exceptUserMode();
2862    InitReg(MISCREG_DCCISW)
2863      .unimplemented()
2864      .warnNotFail()
2865      .writes(1).exceptUserMode();
2866    InitReg(MISCREG_ATS1HR)
2867      .monNonSecureWrite().hypWrite();
2868    InitReg(MISCREG_ATS1HW)
2869      .monNonSecureWrite().hypWrite();
2870    InitReg(MISCREG_TLBIALLIS)
2871      .writes(1).exceptUserMode();
2872    InitReg(MISCREG_TLBIMVAIS)
2873      .writes(1).exceptUserMode();
2874    InitReg(MISCREG_TLBIASIDIS)
2875      .writes(1).exceptUserMode();
2876    InitReg(MISCREG_TLBIMVAAIS)
2877      .writes(1).exceptUserMode();
2878    InitReg(MISCREG_TLBIMVALIS)
2879      .unimplemented()
2880      .writes(1).exceptUserMode();
2881    InitReg(MISCREG_TLBIMVAALIS)
2882      .unimplemented()
2883      .writes(1).exceptUserMode();
2884    InitReg(MISCREG_ITLBIALL)
2885      .writes(1).exceptUserMode();
2886    InitReg(MISCREG_ITLBIMVA)
2887      .writes(1).exceptUserMode();
2888    InitReg(MISCREG_ITLBIASID)
2889      .writes(1).exceptUserMode();
2890    InitReg(MISCREG_DTLBIALL)
2891      .writes(1).exceptUserMode();
2892    InitReg(MISCREG_DTLBIMVA)
2893      .writes(1).exceptUserMode();
2894    InitReg(MISCREG_DTLBIASID)
2895      .writes(1).exceptUserMode();
2896    InitReg(MISCREG_TLBIALL)
2897      .writes(1).exceptUserMode();
2898    InitReg(MISCREG_TLBIMVA)
2899      .writes(1).exceptUserMode();
2900    InitReg(MISCREG_TLBIASID)
2901      .writes(1).exceptUserMode();
2902    InitReg(MISCREG_TLBIMVAA)
2903      .writes(1).exceptUserMode();
2904    InitReg(MISCREG_TLBIMVAL)
2905      .unimplemented()
2906      .writes(1).exceptUserMode();
2907    InitReg(MISCREG_TLBIMVAAL)
2908      .unimplemented()
2909      .writes(1).exceptUserMode();
2910    InitReg(MISCREG_TLBIIPAS2IS)
2911      .unimplemented()
2912      .monNonSecureWrite().hypWrite();
2913    InitReg(MISCREG_TLBIIPAS2LIS)
2914      .unimplemented()
2915      .monNonSecureWrite().hypWrite();
2916    InitReg(MISCREG_TLBIALLHIS)
2917      .monNonSecureWrite().hypWrite();
2918    InitReg(MISCREG_TLBIMVAHIS)
2919      .monNonSecureWrite().hypWrite();
2920    InitReg(MISCREG_TLBIALLNSNHIS)
2921      .monNonSecureWrite().hypWrite();
2922    InitReg(MISCREG_TLBIMVALHIS)
2923      .unimplemented()
2924      .monNonSecureWrite().hypWrite();
2925    InitReg(MISCREG_TLBIIPAS2)
2926      .unimplemented()
2927      .monNonSecureWrite().hypWrite();
2928    InitReg(MISCREG_TLBIIPAS2L)
2929      .unimplemented()
2930      .monNonSecureWrite().hypWrite();
2931    InitReg(MISCREG_TLBIALLH)
2932      .monNonSecureWrite().hypWrite();
2933    InitReg(MISCREG_TLBIMVAH)
2934      .monNonSecureWrite().hypWrite();
2935    InitReg(MISCREG_TLBIALLNSNH)
2936      .monNonSecureWrite().hypWrite();
2937    InitReg(MISCREG_TLBIMVALH)
2938      .unimplemented()
2939      .monNonSecureWrite().hypWrite();
2940    InitReg(MISCREG_PMCR)
2941      .allPrivileges();
2942    InitReg(MISCREG_PMCNTENSET)
2943      .allPrivileges();
2944    InitReg(MISCREG_PMCNTENCLR)
2945      .allPrivileges();
2946    InitReg(MISCREG_PMOVSR)
2947      .allPrivileges();
2948    InitReg(MISCREG_PMSWINC)
2949      .allPrivileges();
2950    InitReg(MISCREG_PMSELR)
2951      .allPrivileges();
2952    InitReg(MISCREG_PMCEID0)
2953      .allPrivileges();
2954    InitReg(MISCREG_PMCEID1)
2955      .allPrivileges();
2956    InitReg(MISCREG_PMCCNTR)
2957      .allPrivileges();
2958    InitReg(MISCREG_PMXEVTYPER)
2959      .allPrivileges();
2960    InitReg(MISCREG_PMCCFILTR)
2961      .allPrivileges();
2962    InitReg(MISCREG_PMXEVCNTR)
2963      .allPrivileges();
2964    InitReg(MISCREG_PMUSERENR)
2965      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
2966    InitReg(MISCREG_PMINTENSET)
2967      .allPrivileges().exceptUserMode();
2968    InitReg(MISCREG_PMINTENCLR)
2969      .allPrivileges().exceptUserMode();
2970    InitReg(MISCREG_PMOVSSET)
2971      .unimplemented()
2972      .allPrivileges();
2973    InitReg(MISCREG_L2CTLR)
2974      .allPrivileges().exceptUserMode();
2975    InitReg(MISCREG_L2ECTLR)
2976      .unimplemented()
2977      .allPrivileges().exceptUserMode();
2978    InitReg(MISCREG_PRRR)
2979      .banked();
2980    InitReg(MISCREG_PRRR_NS)
2981      .bankedChild()
2982      .nonSecure().exceptUserMode();
2983    InitReg(MISCREG_PRRR_S)
2984      .bankedChild()
2985      .secure().exceptUserMode();
2986    InitReg(MISCREG_MAIR0)
2987      .banked();
2988    InitReg(MISCREG_MAIR0_NS)
2989      .bankedChild()
2990      .nonSecure().exceptUserMode();
2991    InitReg(MISCREG_MAIR0_S)
2992      .bankedChild()
2993      .secure().exceptUserMode();
2994    InitReg(MISCREG_NMRR)
2995      .banked();
2996    InitReg(MISCREG_NMRR_NS)
2997      .bankedChild()
2998      .nonSecure().exceptUserMode();
2999    InitReg(MISCREG_NMRR_S)
3000      .bankedChild()
3001      .secure().exceptUserMode();
3002    InitReg(MISCREG_MAIR1)
3003      .banked();
3004    InitReg(MISCREG_MAIR1_NS)
3005      .bankedChild()
3006      .nonSecure().exceptUserMode();
3007    InitReg(MISCREG_MAIR1_S)
3008      .bankedChild()
3009      .secure().exceptUserMode();
3010    InitReg(MISCREG_AMAIR0)
3011      .banked();
3012    InitReg(MISCREG_AMAIR0_NS)
3013      .bankedChild()
3014      .nonSecure().exceptUserMode();
3015    InitReg(MISCREG_AMAIR0_S)
3016      .bankedChild()
3017      .secure().exceptUserMode();
3018    InitReg(MISCREG_AMAIR1)
3019      .banked();
3020    InitReg(MISCREG_AMAIR1_NS)
3021      .bankedChild()
3022      .nonSecure().exceptUserMode();
3023    InitReg(MISCREG_AMAIR1_S)
3024      .bankedChild()
3025      .secure().exceptUserMode();
3026    InitReg(MISCREG_HMAIR0)
3027      .hyp().monNonSecure();
3028    InitReg(MISCREG_HMAIR1)
3029      .hyp().monNonSecure();
3030    InitReg(MISCREG_HAMAIR0)
3031      .unimplemented()
3032      .warnNotFail()
3033      .hyp().monNonSecure();
3034    InitReg(MISCREG_HAMAIR1)
3035      .unimplemented()
3036      .warnNotFail()
3037      .hyp().monNonSecure();
3038    InitReg(MISCREG_VBAR)
3039      .banked();
3040    InitReg(MISCREG_VBAR_NS)
3041      .bankedChild()
3042      .nonSecure().exceptUserMode();
3043    InitReg(MISCREG_VBAR_S)
3044      .bankedChild()
3045      .secure().exceptUserMode();
3046    InitReg(MISCREG_MVBAR)
3047      .mon().secure().exceptUserMode();
3048    InitReg(MISCREG_RMR)
3049      .unimplemented()
3050      .mon().secure().exceptUserMode();
3051    InitReg(MISCREG_ISR)
3052      .allPrivileges().exceptUserMode().writes(0);
3053    InitReg(MISCREG_HVBAR)
3054      .hyp().monNonSecure();
3055    InitReg(MISCREG_FCSEIDR)
3056      .unimplemented()
3057      .warnNotFail()
3058      .allPrivileges().exceptUserMode();
3059    InitReg(MISCREG_CONTEXTIDR)
3060      .banked();
3061    InitReg(MISCREG_CONTEXTIDR_NS)
3062      .bankedChild()
3063      .nonSecure().exceptUserMode();
3064    InitReg(MISCREG_CONTEXTIDR_S)
3065      .bankedChild()
3066      .secure().exceptUserMode();
3067    InitReg(MISCREG_TPIDRURW)
3068      .banked();
3069    InitReg(MISCREG_TPIDRURW_NS)
3070      .bankedChild()
3071      .allPrivileges().monSecure(0).privSecure(0);
3072    InitReg(MISCREG_TPIDRURW_S)
3073      .bankedChild()
3074      .secure();
3075    InitReg(MISCREG_TPIDRURO)
3076      .banked();
3077    InitReg(MISCREG_TPIDRURO_NS)
3078      .bankedChild()
3079      .allPrivileges().secure(0).userNonSecureWrite(0).userSecureRead(1);
3080    InitReg(MISCREG_TPIDRURO_S)
3081      .bankedChild()
3082      .secure().userSecureWrite(0);
3083    InitReg(MISCREG_TPIDRPRW)
3084      .banked();
3085    InitReg(MISCREG_TPIDRPRW_NS)
3086      .bankedChild()
3087      .nonSecure().exceptUserMode();
3088    InitReg(MISCREG_TPIDRPRW_S)
3089      .bankedChild()
3090      .secure().exceptUserMode();
3091    InitReg(MISCREG_HTPIDR)
3092      .hyp().monNonSecure();
3093    InitReg(MISCREG_CNTFRQ)
3094      .unverifiable()
3095      .reads(1).mon();
3096    InitReg(MISCREG_CNTKCTL)
3097      .allPrivileges().exceptUserMode();
3098    InitReg(MISCREG_CNTP_TVAL)
3099      .banked();
3100    InitReg(MISCREG_CNTP_TVAL_NS)
3101      .bankedChild()
3102      .allPrivileges().monSecure(0).privSecure(0);
3103    InitReg(MISCREG_CNTP_TVAL_S)
3104      .unimplemented()
3105      .bankedChild()
3106      .secure().user(1);
3107    InitReg(MISCREG_CNTP_CTL)
3108      .banked();
3109    InitReg(MISCREG_CNTP_CTL_NS)
3110      .bankedChild()
3111      .allPrivileges().monSecure(0).privSecure(0);
3112    InitReg(MISCREG_CNTP_CTL_S)
3113      .unimplemented()
3114      .bankedChild()
3115      .secure().user(1);
3116    InitReg(MISCREG_CNTV_TVAL)
3117      .allPrivileges();
3118    InitReg(MISCREG_CNTV_CTL)
3119      .allPrivileges();
3120    InitReg(MISCREG_CNTHCTL)
3121      .unimplemented()
3122      .hypWrite().monNonSecureRead();
3123    InitReg(MISCREG_CNTHP_TVAL)
3124      .unimplemented()
3125      .hypWrite().monNonSecureRead();
3126    InitReg(MISCREG_CNTHP_CTL)
3127      .unimplemented()
3128      .hypWrite().monNonSecureRead();
3129    InitReg(MISCREG_IL1DATA0)
3130      .unimplemented()
3131      .allPrivileges().exceptUserMode();
3132    InitReg(MISCREG_IL1DATA1)
3133      .unimplemented()
3134      .allPrivileges().exceptUserMode();
3135    InitReg(MISCREG_IL1DATA2)
3136      .unimplemented()
3137      .allPrivileges().exceptUserMode();
3138    InitReg(MISCREG_IL1DATA3)
3139      .unimplemented()
3140      .allPrivileges().exceptUserMode();
3141    InitReg(MISCREG_DL1DATA0)
3142      .unimplemented()
3143      .allPrivileges().exceptUserMode();
3144    InitReg(MISCREG_DL1DATA1)
3145      .unimplemented()
3146      .allPrivileges().exceptUserMode();
3147    InitReg(MISCREG_DL1DATA2)
3148      .unimplemented()
3149      .allPrivileges().exceptUserMode();
3150    InitReg(MISCREG_DL1DATA3)
3151      .unimplemented()
3152      .allPrivileges().exceptUserMode();
3153    InitReg(MISCREG_DL1DATA4)
3154      .unimplemented()
3155      .allPrivileges().exceptUserMode();
3156    InitReg(MISCREG_RAMINDEX)
3157      .unimplemented()
3158      .writes(1).exceptUserMode();
3159    InitReg(MISCREG_L2ACTLR)
3160      .unimplemented()
3161      .allPrivileges().exceptUserMode();
3162    InitReg(MISCREG_CBAR)
3163      .unimplemented()
3164      .allPrivileges().exceptUserMode().writes(0);
3165    InitReg(MISCREG_HTTBR)
3166      .hyp().monNonSecure();
3167    InitReg(MISCREG_VTTBR)
3168      .hyp().monNonSecure();
3169    InitReg(MISCREG_CNTPCT)
3170      .reads(1);
3171    InitReg(MISCREG_CNTVCT)
3172      .unverifiable()
3173      .reads(1);
3174    InitReg(MISCREG_CNTP_CVAL)
3175      .banked();
3176    InitReg(MISCREG_CNTP_CVAL_NS)
3177      .bankedChild()
3178      .allPrivileges().monSecure(0).privSecure(0);
3179    InitReg(MISCREG_CNTP_CVAL_S)
3180      .unimplemented()
3181      .bankedChild()
3182      .secure().user(1);
3183    InitReg(MISCREG_CNTV_CVAL)
3184      .allPrivileges();
3185    InitReg(MISCREG_CNTVOFF)
3186      .hyp().monNonSecure();
3187    InitReg(MISCREG_CNTHP_CVAL)
3188      .unimplemented()
3189      .hypWrite().monNonSecureRead();
3190    InitReg(MISCREG_CPUMERRSR)
3191      .unimplemented()
3192      .allPrivileges().exceptUserMode();
3193    InitReg(MISCREG_L2MERRSR)
3194      .unimplemented()
3195      .warnNotFail()
3196      .allPrivileges().exceptUserMode();
3197
3198    // AArch64 registers (Op0=2);
3199    InitReg(MISCREG_MDCCINT_EL1)
3200      .allPrivileges();
3201    InitReg(MISCREG_OSDTRRX_EL1)
3202      .allPrivileges()
3203      .mapsTo(MISCREG_DBGDTRRXext);
3204    InitReg(MISCREG_MDSCR_EL1)
3205      .allPrivileges()
3206      .mapsTo(MISCREG_DBGDSCRext);
3207    InitReg(MISCREG_OSDTRTX_EL1)
3208      .allPrivileges()
3209      .mapsTo(MISCREG_DBGDTRTXext);
3210    InitReg(MISCREG_OSECCR_EL1)
3211      .allPrivileges()
3212      .mapsTo(MISCREG_DBGOSECCR);
3213    InitReg(MISCREG_DBGBVR0_EL1)
3214      .allPrivileges()
3215      .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3216    InitReg(MISCREG_DBGBVR1_EL1)
3217      .allPrivileges()
3218      .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3219    InitReg(MISCREG_DBGBVR2_EL1)
3220      .allPrivileges()
3221      .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3222    InitReg(MISCREG_DBGBVR3_EL1)
3223      .allPrivileges()
3224      .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3225    InitReg(MISCREG_DBGBVR4_EL1)
3226      .allPrivileges()
3227      .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3228    InitReg(MISCREG_DBGBVR5_EL1)
3229      .allPrivileges()
3230      .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3231    InitReg(MISCREG_DBGBCR0_EL1)
3232      .allPrivileges()
3233      .mapsTo(MISCREG_DBGBCR0);
3234    InitReg(MISCREG_DBGBCR1_EL1)
3235      .allPrivileges()
3236      .mapsTo(MISCREG_DBGBCR1);
3237    InitReg(MISCREG_DBGBCR2_EL1)
3238      .allPrivileges()
3239      .mapsTo(MISCREG_DBGBCR2);
3240    InitReg(MISCREG_DBGBCR3_EL1)
3241      .allPrivileges()
3242      .mapsTo(MISCREG_DBGBCR3);
3243    InitReg(MISCREG_DBGBCR4_EL1)
3244      .allPrivileges()
3245      .mapsTo(MISCREG_DBGBCR4);
3246    InitReg(MISCREG_DBGBCR5_EL1)
3247      .allPrivileges()
3248      .mapsTo(MISCREG_DBGBCR5);
3249    InitReg(MISCREG_DBGWVR0_EL1)
3250      .allPrivileges()
3251      .mapsTo(MISCREG_DBGWVR0);
3252    InitReg(MISCREG_DBGWVR1_EL1)
3253      .allPrivileges()
3254      .mapsTo(MISCREG_DBGWVR1);
3255    InitReg(MISCREG_DBGWVR2_EL1)
3256      .allPrivileges()
3257      .mapsTo(MISCREG_DBGWVR2);
3258    InitReg(MISCREG_DBGWVR3_EL1)
3259      .allPrivileges()
3260      .mapsTo(MISCREG_DBGWVR3);
3261    InitReg(MISCREG_DBGWCR0_EL1)
3262      .allPrivileges()
3263      .mapsTo(MISCREG_DBGWCR0);
3264    InitReg(MISCREG_DBGWCR1_EL1)
3265      .allPrivileges()
3266      .mapsTo(MISCREG_DBGWCR1);
3267    InitReg(MISCREG_DBGWCR2_EL1)
3268      .allPrivileges()
3269      .mapsTo(MISCREG_DBGWCR2);
3270    InitReg(MISCREG_DBGWCR3_EL1)
3271      .allPrivileges()
3272      .mapsTo(MISCREG_DBGWCR3);
3273    InitReg(MISCREG_MDCCSR_EL0)
3274      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3275      .mapsTo(MISCREG_DBGDSCRint);
3276    InitReg(MISCREG_MDDTR_EL0)
3277      .allPrivileges();
3278    InitReg(MISCREG_MDDTRTX_EL0)
3279      .allPrivileges();
3280    InitReg(MISCREG_MDDTRRX_EL0)
3281      .allPrivileges();
3282    InitReg(MISCREG_DBGVCR32_EL2)
3283      .allPrivileges()
3284      .mapsTo(MISCREG_DBGVCR);
3285    InitReg(MISCREG_MDRAR_EL1)
3286      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3287      .mapsTo(MISCREG_DBGDRAR);
3288    InitReg(MISCREG_OSLAR_EL1)
3289      .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3290      .mapsTo(MISCREG_DBGOSLAR);
3291    InitReg(MISCREG_OSLSR_EL1)
3292      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3293      .mapsTo(MISCREG_DBGOSLSR);
3294    InitReg(MISCREG_OSDLR_EL1)
3295      .allPrivileges()
3296      .mapsTo(MISCREG_DBGOSDLR);
3297    InitReg(MISCREG_DBGPRCR_EL1)
3298      .allPrivileges()
3299      .mapsTo(MISCREG_DBGPRCR);
3300    InitReg(MISCREG_DBGCLAIMSET_EL1)
3301      .allPrivileges()
3302      .mapsTo(MISCREG_DBGCLAIMSET);
3303    InitReg(MISCREG_DBGCLAIMCLR_EL1)
3304      .allPrivileges()
3305      .mapsTo(MISCREG_DBGCLAIMCLR);
3306    InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3307      .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3308      .mapsTo(MISCREG_DBGAUTHSTATUS);
3309    InitReg(MISCREG_TEECR32_EL1);
3310    InitReg(MISCREG_TEEHBR32_EL1);
3311
3312    // AArch64 registers (Op0=1,3);
3313    InitReg(MISCREG_MIDR_EL1)
3314      .allPrivileges().exceptUserMode().writes(0);
3315    InitReg(MISCREG_MPIDR_EL1)
3316      .allPrivileges().exceptUserMode().writes(0);
3317    InitReg(MISCREG_REVIDR_EL1)
3318      .allPrivileges().exceptUserMode().writes(0);
3319    InitReg(MISCREG_ID_PFR0_EL1)
3320      .allPrivileges().exceptUserMode().writes(0);
3321    InitReg(MISCREG_ID_PFR1_EL1)
3322      .allPrivileges().exceptUserMode().writes(0);
3323    InitReg(MISCREG_ID_DFR0_EL1)
3324      .allPrivileges().exceptUserMode().writes(0)
3325      .mapsTo(MISCREG_ID_DFR0);
3326    InitReg(MISCREG_ID_AFR0_EL1)
3327      .allPrivileges().exceptUserMode().writes(0);
3328    InitReg(MISCREG_ID_MMFR0_EL1)
3329      .allPrivileges().exceptUserMode().writes(0);
3330    InitReg(MISCREG_ID_MMFR1_EL1)
3331      .allPrivileges().exceptUserMode().writes(0);
3332    InitReg(MISCREG_ID_MMFR2_EL1)
3333      .allPrivileges().exceptUserMode().writes(0);
3334    InitReg(MISCREG_ID_MMFR3_EL1)
3335      .allPrivileges().exceptUserMode().writes(0);
3336    InitReg(MISCREG_ID_ISAR0_EL1)
3337      .allPrivileges().exceptUserMode().writes(0);
3338    InitReg(MISCREG_ID_ISAR1_EL1)
3339      .allPrivileges().exceptUserMode().writes(0);
3340    InitReg(MISCREG_ID_ISAR2_EL1)
3341      .allPrivileges().exceptUserMode().writes(0);
3342    InitReg(MISCREG_ID_ISAR3_EL1)
3343      .allPrivileges().exceptUserMode().writes(0);
3344    InitReg(MISCREG_ID_ISAR4_EL1)
3345      .allPrivileges().exceptUserMode().writes(0);
3346    InitReg(MISCREG_ID_ISAR5_EL1)
3347      .allPrivileges().exceptUserMode().writes(0);
3348    InitReg(MISCREG_MVFR0_EL1)
3349      .allPrivileges().exceptUserMode().writes(0);
3350    InitReg(MISCREG_MVFR1_EL1)
3351      .allPrivileges().exceptUserMode().writes(0);
3352    InitReg(MISCREG_MVFR2_EL1)
3353      .allPrivileges().exceptUserMode().writes(0);
3354    InitReg(MISCREG_ID_AA64PFR0_EL1)
3355      .allPrivileges().exceptUserMode().writes(0);
3356    InitReg(MISCREG_ID_AA64PFR1_EL1)
3357      .allPrivileges().exceptUserMode().writes(0);
3358    InitReg(MISCREG_ID_AA64DFR0_EL1)
3359      .allPrivileges().exceptUserMode().writes(0);
3360    InitReg(MISCREG_ID_AA64DFR1_EL1)
3361      .allPrivileges().exceptUserMode().writes(0);
3362    InitReg(MISCREG_ID_AA64AFR0_EL1)
3363      .allPrivileges().exceptUserMode().writes(0);
3364    InitReg(MISCREG_ID_AA64AFR1_EL1)
3365      .allPrivileges().exceptUserMode().writes(0);
3366    InitReg(MISCREG_ID_AA64ISAR0_EL1)
3367      .allPrivileges().exceptUserMode().writes(0);
3368    InitReg(MISCREG_ID_AA64ISAR1_EL1)
3369      .allPrivileges().exceptUserMode().writes(0);
3370    InitReg(MISCREG_ID_AA64MMFR0_EL1)
3371      .allPrivileges().exceptUserMode().writes(0);
3372    InitReg(MISCREG_ID_AA64MMFR1_EL1)
3373      .allPrivileges().exceptUserMode().writes(0);
3374    InitReg(MISCREG_CCSIDR_EL1)
3375      .allPrivileges().exceptUserMode().writes(0);
3376    InitReg(MISCREG_CLIDR_EL1)
3377      .allPrivileges().exceptUserMode().writes(0);
3378    InitReg(MISCREG_AIDR_EL1)
3379      .allPrivileges().exceptUserMode().writes(0);
3380    InitReg(MISCREG_CSSELR_EL1)
3381      .allPrivileges().exceptUserMode()
3382      .mapsTo(MISCREG_CSSELR_NS);
3383    InitReg(MISCREG_CTR_EL0)
3384      .reads(1);
3385    InitReg(MISCREG_DCZID_EL0)
3386      .reads(1);
3387    InitReg(MISCREG_VPIDR_EL2)
3388      .hyp().mon()
3389      .mapsTo(MISCREG_VPIDR);
3390    InitReg(MISCREG_VMPIDR_EL2)
3391      .hyp().mon()
3392      .mapsTo(MISCREG_VMPIDR);
3393    InitReg(MISCREG_SCTLR_EL1)
3394      .allPrivileges().exceptUserMode()
3395      .mapsTo(MISCREG_SCTLR_NS);
3396    InitReg(MISCREG_ACTLR_EL1)
3397      .allPrivileges().exceptUserMode()
3398      .mapsTo(MISCREG_ACTLR_NS);
3399    InitReg(MISCREG_CPACR_EL1)
3400      .allPrivileges().exceptUserMode()
3401      .mapsTo(MISCREG_CPACR);
3402    InitReg(MISCREG_SCTLR_EL2)
3403      .hyp().mon()
3404      .mapsTo(MISCREG_HSCTLR);
3405    InitReg(MISCREG_ACTLR_EL2)
3406      .hyp().mon()
3407      .mapsTo(MISCREG_HACTLR);
3408    InitReg(MISCREG_HCR_EL2)
3409      .hyp().mon()
3410      .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3411    InitReg(MISCREG_MDCR_EL2)
3412      .hyp().mon()
3413      .mapsTo(MISCREG_HDCR);
3414    InitReg(MISCREG_CPTR_EL2)
3415      .hyp().mon()
3416      .mapsTo(MISCREG_HCPTR);
3417    InitReg(MISCREG_HSTR_EL2)
3418      .hyp().mon()
3419      .mapsTo(MISCREG_HSTR);
3420    InitReg(MISCREG_HACR_EL2)
3421      .hyp().mon()
3422      .mapsTo(MISCREG_HACR);
3423    InitReg(MISCREG_SCTLR_EL3)
3424      .mon();
3425    InitReg(MISCREG_ACTLR_EL3)
3426      .mon();
3427    InitReg(MISCREG_SCR_EL3)
3428      .mon()
3429      .mapsTo(MISCREG_SCR); // NAM D7-2005
3430    InitReg(MISCREG_SDER32_EL3)
3431      .mon()
3432      .mapsTo(MISCREG_SDER);
3433    InitReg(MISCREG_CPTR_EL3)
3434      .mon();
3435    InitReg(MISCREG_MDCR_EL3)
3436      .mon();
3437    InitReg(MISCREG_TTBR0_EL1)
3438      .allPrivileges().exceptUserMode()
3439      .mapsTo(MISCREG_TTBR0_NS);
3440    InitReg(MISCREG_TTBR1_EL1)
3441      .allPrivileges().exceptUserMode()
3442      .mapsTo(MISCREG_TTBR1_NS);
3443    InitReg(MISCREG_TCR_EL1)
3444      .allPrivileges().exceptUserMode()
3445      .mapsTo(MISCREG_TTBCR_NS);
3446    InitReg(MISCREG_TTBR0_EL2)
3447      .hyp().mon()
3448      .mapsTo(MISCREG_HTTBR);
3449    InitReg(MISCREG_TCR_EL2)
3450      .hyp().mon()
3451      .mapsTo(MISCREG_HTCR);
3452    InitReg(MISCREG_VTTBR_EL2)
3453      .hyp().mon()
3454      .mapsTo(MISCREG_VTTBR);
3455    InitReg(MISCREG_VTCR_EL2)
3456      .hyp().mon()
3457      .mapsTo(MISCREG_VTCR);
3458    InitReg(MISCREG_TTBR0_EL3)
3459      .mon();
3460    InitReg(MISCREG_TCR_EL3)
3461      .mon();
3462    InitReg(MISCREG_DACR32_EL2)
3463      .hyp().mon()
3464      .mapsTo(MISCREG_DACR_NS);
3465    InitReg(MISCREG_SPSR_EL1)
3466      .allPrivileges().exceptUserMode()
3467      .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3468    InitReg(MISCREG_ELR_EL1)
3469      .allPrivileges().exceptUserMode();
3470    InitReg(MISCREG_SP_EL0)
3471      .allPrivileges().exceptUserMode();
3472    InitReg(MISCREG_SPSEL)
3473      .allPrivileges().exceptUserMode();
3474    InitReg(MISCREG_CURRENTEL)
3475      .allPrivileges().exceptUserMode().writes(0);
3476    InitReg(MISCREG_NZCV)
3477      .allPrivileges();
3478    InitReg(MISCREG_DAIF)
3479      .allPrivileges();
3480    InitReg(MISCREG_FPCR)
3481      .allPrivileges();
3482    InitReg(MISCREG_FPSR)
3483      .allPrivileges();
3484    InitReg(MISCREG_DSPSR_EL0)
3485      .allPrivileges();
3486    InitReg(MISCREG_DLR_EL0)
3487      .allPrivileges();
3488    InitReg(MISCREG_SPSR_EL2)
3489      .hyp().mon()
3490      .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3491    InitReg(MISCREG_ELR_EL2)
3492      .hyp().mon();
3493    InitReg(MISCREG_SP_EL1)
3494      .hyp().mon();
3495    InitReg(MISCREG_SPSR_IRQ_AA64)
3496      .hyp().mon();
3497    InitReg(MISCREG_SPSR_ABT_AA64)
3498      .hyp().mon();
3499    InitReg(MISCREG_SPSR_UND_AA64)
3500      .hyp().mon();
3501    InitReg(MISCREG_SPSR_FIQ_AA64)
3502      .hyp().mon();
3503    InitReg(MISCREG_SPSR_EL3)
3504      .mon()
3505      .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3506    InitReg(MISCREG_ELR_EL3)
3507      .mon();
3508    InitReg(MISCREG_SP_EL2)
3509      .mon();
3510    InitReg(MISCREG_AFSR0_EL1)
3511      .allPrivileges().exceptUserMode()
3512      .mapsTo(MISCREG_ADFSR_NS);
3513    InitReg(MISCREG_AFSR1_EL1)
3514      .allPrivileges().exceptUserMode()
3515      .mapsTo(MISCREG_AIFSR_NS);
3516    InitReg(MISCREG_ESR_EL1)
3517      .allPrivileges().exceptUserMode();
3518    InitReg(MISCREG_IFSR32_EL2)
3519      .hyp().mon()
3520      .mapsTo(MISCREG_IFSR_NS);
3521    InitReg(MISCREG_AFSR0_EL2)
3522      .hyp().mon()
3523      .mapsTo(MISCREG_HADFSR);
3524    InitReg(MISCREG_AFSR1_EL2)
3525      .hyp().mon()
3526      .mapsTo(MISCREG_HAIFSR);
3527    InitReg(MISCREG_ESR_EL2)
3528      .hyp().mon()
3529      .mapsTo(MISCREG_HSR);
3530    InitReg(MISCREG_FPEXC32_EL2)
3531      .hyp().mon();
3532    InitReg(MISCREG_AFSR0_EL3)
3533      .mon();
3534    InitReg(MISCREG_AFSR1_EL3)
3535      .mon();
3536    InitReg(MISCREG_ESR_EL3)
3537      .mon();
3538    InitReg(MISCREG_FAR_EL1)
3539      .allPrivileges().exceptUserMode()
3540      .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3541    InitReg(MISCREG_FAR_EL2)
3542      .hyp().mon()
3543      .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3544    InitReg(MISCREG_HPFAR_EL2)
3545      .hyp().mon()
3546      .mapsTo(MISCREG_HPFAR);
3547    InitReg(MISCREG_FAR_EL3)
3548      .mon();
3549    InitReg(MISCREG_IC_IALLUIS)
3550      .warnNotFail()
3551      .writes(1).exceptUserMode();
3552    InitReg(MISCREG_PAR_EL1)
3553      .allPrivileges().exceptUserMode()
3554      .mapsTo(MISCREG_PAR_NS);
3555    InitReg(MISCREG_IC_IALLU)
3556      .warnNotFail()
3557      .writes(1).exceptUserMode();
3558    InitReg(MISCREG_DC_IVAC_Xt)
3559      .warnNotFail()
3560      .writes(1);
3561    InitReg(MISCREG_DC_ISW_Xt)
3562      .warnNotFail()
3563      .writes(1).exceptUserMode();
3564    InitReg(MISCREG_AT_S1E1R_Xt)
3565      .writes(1).exceptUserMode();
3566    InitReg(MISCREG_AT_S1E1W_Xt)
3567      .writes(1).exceptUserMode();
3568    InitReg(MISCREG_AT_S1E0R_Xt)
3569      .writes(1).exceptUserMode();
3570    InitReg(MISCREG_AT_S1E0W_Xt)
3571      .writes(1).exceptUserMode();
3572    InitReg(MISCREG_DC_CSW_Xt)
3573      .warnNotFail()
3574      .writes(1).exceptUserMode();
3575    InitReg(MISCREG_DC_CISW_Xt)
3576      .warnNotFail()
3577      .writes(1).exceptUserMode();
3578    InitReg(MISCREG_DC_ZVA_Xt)
3579      .warnNotFail()
3580      .writes(1).userSecureWrite(0);
3581    InitReg(MISCREG_IC_IVAU_Xt)
3582      .writes(1);
3583    InitReg(MISCREG_DC_CVAC_Xt)
3584      .warnNotFail()
3585      .writes(1);
3586    InitReg(MISCREG_DC_CVAU_Xt)
3587      .warnNotFail()
3588      .writes(1);
3589    InitReg(MISCREG_DC_CIVAC_Xt)
3590      .warnNotFail()
3591      .writes(1);
3592    InitReg(MISCREG_AT_S1E2R_Xt)
3593      .monNonSecureWrite().hypWrite();
3594    InitReg(MISCREG_AT_S1E2W_Xt)
3595      .monNonSecureWrite().hypWrite();
3596    InitReg(MISCREG_AT_S12E1R_Xt)
3597      .hypWrite().monSecureWrite().monNonSecureWrite();
3598    InitReg(MISCREG_AT_S12E1W_Xt)
3599      .hypWrite().monSecureWrite().monNonSecureWrite();
3600    InitReg(MISCREG_AT_S12E0R_Xt)
3601      .hypWrite().monSecureWrite().monNonSecureWrite();
3602    InitReg(MISCREG_AT_S12E0W_Xt)
3603      .hypWrite().monSecureWrite().monNonSecureWrite();
3604    InitReg(MISCREG_AT_S1E3R_Xt)
3605      .monSecureWrite().monNonSecureWrite();
3606    InitReg(MISCREG_AT_S1E3W_Xt)
3607      .monSecureWrite().monNonSecureWrite();
3608    InitReg(MISCREG_TLBI_VMALLE1IS)
3609      .writes(1).exceptUserMode();
3610    InitReg(MISCREG_TLBI_VAE1IS_Xt)
3611      .writes(1).exceptUserMode();
3612    InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3613      .writes(1).exceptUserMode();
3614    InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3615      .writes(1).exceptUserMode();
3616    InitReg(MISCREG_TLBI_VALE1IS_Xt)
3617      .writes(1).exceptUserMode();
3618    InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3619      .writes(1).exceptUserMode();
3620    InitReg(MISCREG_TLBI_VMALLE1)
3621      .writes(1).exceptUserMode();
3622    InitReg(MISCREG_TLBI_VAE1_Xt)
3623      .writes(1).exceptUserMode();
3624    InitReg(MISCREG_TLBI_ASIDE1_Xt)
3625      .writes(1).exceptUserMode();
3626    InitReg(MISCREG_TLBI_VAAE1_Xt)
3627      .writes(1).exceptUserMode();
3628    InitReg(MISCREG_TLBI_VALE1_Xt)
3629      .writes(1).exceptUserMode();
3630    InitReg(MISCREG_TLBI_VAALE1_Xt)
3631      .writes(1).exceptUserMode();
3632    InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3633      .hypWrite().monSecureWrite().monNonSecureWrite();
3634    InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3635      .hypWrite().monSecureWrite().monNonSecureWrite();
3636    InitReg(MISCREG_TLBI_ALLE2IS)
3637      .monNonSecureWrite().hypWrite();
3638    InitReg(MISCREG_TLBI_VAE2IS_Xt)
3639      .monNonSecureWrite().hypWrite();
3640    InitReg(MISCREG_TLBI_ALLE1IS)
3641      .hypWrite().monSecureWrite().monNonSecureWrite();
3642    InitReg(MISCREG_TLBI_VALE2IS_Xt)
3643      .monNonSecureWrite().hypWrite();
3644    InitReg(MISCREG_TLBI_VMALLS12E1IS)
3645      .hypWrite().monSecureWrite().monNonSecureWrite();
3646    InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3647      .hypWrite().monSecureWrite().monNonSecureWrite();
3648    InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3649      .hypWrite().monSecureWrite().monNonSecureWrite();
3650    InitReg(MISCREG_TLBI_ALLE2)
3651      .monNonSecureWrite().hypWrite();
3652    InitReg(MISCREG_TLBI_VAE2_Xt)
3653      .monNonSecureWrite().hypWrite();
3654    InitReg(MISCREG_TLBI_ALLE1)
3655      .hypWrite().monSecureWrite().monNonSecureWrite();
3656    InitReg(MISCREG_TLBI_VALE2_Xt)
3657      .monNonSecureWrite().hypWrite();
3658    InitReg(MISCREG_TLBI_VMALLS12E1)
3659      .hypWrite().monSecureWrite().monNonSecureWrite();
3660    InitReg(MISCREG_TLBI_ALLE3IS)
3661      .monSecureWrite().monNonSecureWrite();
3662    InitReg(MISCREG_TLBI_VAE3IS_Xt)
3663      .monSecureWrite().monNonSecureWrite();
3664    InitReg(MISCREG_TLBI_VALE3IS_Xt)
3665      .monSecureWrite().monNonSecureWrite();
3666    InitReg(MISCREG_TLBI_ALLE3)
3667      .monSecureWrite().monNonSecureWrite();
3668    InitReg(MISCREG_TLBI_VAE3_Xt)
3669      .monSecureWrite().monNonSecureWrite();
3670    InitReg(MISCREG_TLBI_VALE3_Xt)
3671      .monSecureWrite().monNonSecureWrite();
3672    InitReg(MISCREG_PMINTENSET_EL1)
3673      .allPrivileges().exceptUserMode()
3674      .mapsTo(MISCREG_PMINTENSET);
3675    InitReg(MISCREG_PMINTENCLR_EL1)
3676      .allPrivileges().exceptUserMode()
3677      .mapsTo(MISCREG_PMINTENCLR);
3678    InitReg(MISCREG_PMCR_EL0)
3679      .allPrivileges()
3680      .mapsTo(MISCREG_PMCR);
3681    InitReg(MISCREG_PMCNTENSET_EL0)
3682      .allPrivileges()
3683      .mapsTo(MISCREG_PMCNTENSET);
3684    InitReg(MISCREG_PMCNTENCLR_EL0)
3685      .allPrivileges()
3686      .mapsTo(MISCREG_PMCNTENCLR);
3687    InitReg(MISCREG_PMOVSCLR_EL0)
3688      .allPrivileges();
3689//    .mapsTo(MISCREG_PMOVSCLR);
3690    InitReg(MISCREG_PMSWINC_EL0)
3691      .writes(1).user()
3692      .mapsTo(MISCREG_PMSWINC);
3693    InitReg(MISCREG_PMSELR_EL0)
3694      .allPrivileges()
3695      .mapsTo(MISCREG_PMSELR);
3696    InitReg(MISCREG_PMCEID0_EL0)
3697      .reads(1).user()
3698      .mapsTo(MISCREG_PMCEID0);
3699    InitReg(MISCREG_PMCEID1_EL0)
3700      .reads(1).user()
3701      .mapsTo(MISCREG_PMCEID1);
3702    InitReg(MISCREG_PMCCNTR_EL0)
3703      .allPrivileges()
3704      .mapsTo(MISCREG_PMCCNTR);
3705    InitReg(MISCREG_PMXEVTYPER_EL0)
3706      .allPrivileges()
3707      .mapsTo(MISCREG_PMXEVTYPER);
3708    InitReg(MISCREG_PMCCFILTR_EL0)
3709      .allPrivileges();
3710    InitReg(MISCREG_PMXEVCNTR_EL0)
3711      .allPrivileges()
3712      .mapsTo(MISCREG_PMXEVCNTR);
3713    InitReg(MISCREG_PMUSERENR_EL0)
3714      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3715      .mapsTo(MISCREG_PMUSERENR);
3716    InitReg(MISCREG_PMOVSSET_EL0)
3717      .allPrivileges()
3718      .mapsTo(MISCREG_PMOVSSET);
3719    InitReg(MISCREG_MAIR_EL1)
3720      .allPrivileges().exceptUserMode()
3721      .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3722    InitReg(MISCREG_AMAIR_EL1)
3723      .allPrivileges().exceptUserMode()
3724      .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3725    InitReg(MISCREG_MAIR_EL2)
3726      .hyp().mon()
3727      .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3728    InitReg(MISCREG_AMAIR_EL2)
3729      .hyp().mon()
3730      .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3731    InitReg(MISCREG_MAIR_EL3)
3732      .mon();
3733    InitReg(MISCREG_AMAIR_EL3)
3734      .mon();
3735    InitReg(MISCREG_L2CTLR_EL1)
3736      .allPrivileges().exceptUserMode();
3737    InitReg(MISCREG_L2ECTLR_EL1)
3738      .allPrivileges().exceptUserMode();
3739    InitReg(MISCREG_VBAR_EL1)
3740      .allPrivileges().exceptUserMode()
3741      .mapsTo(MISCREG_VBAR_NS);
3742    InitReg(MISCREG_RVBAR_EL1)
3743      .allPrivileges().exceptUserMode().writes(0);
3744    InitReg(MISCREG_ISR_EL1)
3745      .allPrivileges().exceptUserMode().writes(0);
3746    InitReg(MISCREG_VBAR_EL2)
3747      .hyp().mon()
3748      .mapsTo(MISCREG_HVBAR);
3749    InitReg(MISCREG_RVBAR_EL2)
3750      .mon().hyp().writes(0);
3751    InitReg(MISCREG_VBAR_EL3)
3752      .mon();
3753    InitReg(MISCREG_RVBAR_EL3)
3754      .mon().writes(0);
3755    InitReg(MISCREG_RMR_EL3)
3756      .mon();
3757    InitReg(MISCREG_CONTEXTIDR_EL1)
3758      .allPrivileges().exceptUserMode()
3759      .mapsTo(MISCREG_CONTEXTIDR_NS);
3760    InitReg(MISCREG_TPIDR_EL1)
3761      .allPrivileges().exceptUserMode()
3762      .mapsTo(MISCREG_TPIDRPRW_NS);
3763    InitReg(MISCREG_TPIDR_EL0)
3764      .allPrivileges()
3765      .mapsTo(MISCREG_TPIDRURW_NS);
3766    InitReg(MISCREG_TPIDRRO_EL0)
3767      .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3768      .mapsTo(MISCREG_TPIDRURO_NS);
3769    InitReg(MISCREG_TPIDR_EL2)
3770      .hyp().mon()
3771      .mapsTo(MISCREG_HTPIDR);
3772    InitReg(MISCREG_TPIDR_EL3)
3773      .mon();
3774    InitReg(MISCREG_CNTKCTL_EL1)
3775      .allPrivileges().exceptUserMode()
3776      .mapsTo(MISCREG_CNTKCTL);
3777    InitReg(MISCREG_CNTFRQ_EL0)
3778      .reads(1).mon()
3779      .mapsTo(MISCREG_CNTFRQ);
3780    InitReg(MISCREG_CNTPCT_EL0)
3781      .reads(1)
3782      .mapsTo(MISCREG_CNTPCT); /* 64b */
3783    InitReg(MISCREG_CNTVCT_EL0)
3784      .unverifiable()
3785      .reads(1)
3786      .mapsTo(MISCREG_CNTVCT); /* 64b */
3787    InitReg(MISCREG_CNTP_TVAL_EL0)
3788      .allPrivileges()
3789      .mapsTo(MISCREG_CNTP_TVAL_NS);
3790    InitReg(MISCREG_CNTP_CTL_EL0)
3791      .allPrivileges()
3792      .mapsTo(MISCREG_CNTP_CTL_NS);
3793    InitReg(MISCREG_CNTP_CVAL_EL0)
3794      .allPrivileges()
3795      .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
3796    InitReg(MISCREG_CNTV_TVAL_EL0)
3797      .allPrivileges()
3798      .mapsTo(MISCREG_CNTV_TVAL);
3799    InitReg(MISCREG_CNTV_CTL_EL0)
3800      .allPrivileges()
3801      .mapsTo(MISCREG_CNTV_CTL);
3802    InitReg(MISCREG_CNTV_CVAL_EL0)
3803      .allPrivileges()
3804      .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
3805    InitReg(MISCREG_PMEVCNTR0_EL0)
3806      .allPrivileges();
3807//    .mapsTo(MISCREG_PMEVCNTR0);
3808    InitReg(MISCREG_PMEVCNTR1_EL0)
3809      .allPrivileges();
3810//    .mapsTo(MISCREG_PMEVCNTR1);
3811    InitReg(MISCREG_PMEVCNTR2_EL0)
3812      .allPrivileges();
3813//    .mapsTo(MISCREG_PMEVCNTR2);
3814    InitReg(MISCREG_PMEVCNTR3_EL0)
3815      .allPrivileges();
3816//    .mapsTo(MISCREG_PMEVCNTR3);
3817    InitReg(MISCREG_PMEVCNTR4_EL0)
3818      .allPrivileges();
3819//    .mapsTo(MISCREG_PMEVCNTR4);
3820    InitReg(MISCREG_PMEVCNTR5_EL0)
3821      .allPrivileges();
3822//    .mapsTo(MISCREG_PMEVCNTR5);
3823    InitReg(MISCREG_PMEVTYPER0_EL0)
3824      .allPrivileges();
3825//    .mapsTo(MISCREG_PMEVTYPER0);
3826    InitReg(MISCREG_PMEVTYPER1_EL0)
3827      .allPrivileges();
3828//    .mapsTo(MISCREG_PMEVTYPER1);
3829    InitReg(MISCREG_PMEVTYPER2_EL0)
3830      .allPrivileges();
3831//    .mapsTo(MISCREG_PMEVTYPER2);
3832    InitReg(MISCREG_PMEVTYPER3_EL0)
3833      .allPrivileges();
3834//    .mapsTo(MISCREG_PMEVTYPER3);
3835    InitReg(MISCREG_PMEVTYPER4_EL0)
3836      .allPrivileges();
3837//    .mapsTo(MISCREG_PMEVTYPER4);
3838    InitReg(MISCREG_PMEVTYPER5_EL0)
3839      .allPrivileges();
3840//    .mapsTo(MISCREG_PMEVTYPER5);
3841    InitReg(MISCREG_CNTVOFF_EL2)
3842      .hyp().mon()
3843      .mapsTo(MISCREG_CNTVOFF); /* 64b */
3844    InitReg(MISCREG_CNTHCTL_EL2)
3845      .unimplemented()
3846      .warnNotFail()
3847      .mon().monNonSecureWrite(0).hypWrite()
3848      .mapsTo(MISCREG_CNTHCTL);
3849    InitReg(MISCREG_CNTHP_TVAL_EL2)
3850      .unimplemented()
3851      .mon().monNonSecureWrite(0).hypWrite()
3852      .mapsTo(MISCREG_CNTHP_TVAL);
3853    InitReg(MISCREG_CNTHP_CTL_EL2)
3854      .unimplemented()
3855      .mon().monNonSecureWrite(0).hypWrite()
3856      .mapsTo(MISCREG_CNTHP_CTL);
3857    InitReg(MISCREG_CNTHP_CVAL_EL2)
3858      .unimplemented()
3859      .mon().monNonSecureWrite(0).hypWrite()
3860      .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
3861    InitReg(MISCREG_CNTPS_TVAL_EL1)
3862      .unimplemented()
3863      .mon().monNonSecureWrite(0).hypWrite();
3864    InitReg(MISCREG_CNTPS_CTL_EL1)
3865      .unimplemented()
3866      .mon().monNonSecureWrite(0).hypWrite();
3867    InitReg(MISCREG_CNTPS_CVAL_EL1)
3868      .unimplemented()
3869      .mon().monNonSecureWrite(0).hypWrite();
3870    InitReg(MISCREG_IL1DATA0_EL1)
3871      .allPrivileges().exceptUserMode();
3872    InitReg(MISCREG_IL1DATA1_EL1)
3873      .allPrivileges().exceptUserMode();
3874    InitReg(MISCREG_IL1DATA2_EL1)
3875      .allPrivileges().exceptUserMode();
3876    InitReg(MISCREG_IL1DATA3_EL1)
3877      .allPrivileges().exceptUserMode();
3878    InitReg(MISCREG_DL1DATA0_EL1)
3879      .allPrivileges().exceptUserMode();
3880    InitReg(MISCREG_DL1DATA1_EL1)
3881      .allPrivileges().exceptUserMode();
3882    InitReg(MISCREG_DL1DATA2_EL1)
3883      .allPrivileges().exceptUserMode();
3884    InitReg(MISCREG_DL1DATA3_EL1)
3885      .allPrivileges().exceptUserMode();
3886    InitReg(MISCREG_DL1DATA4_EL1)
3887      .allPrivileges().exceptUserMode();
3888    InitReg(MISCREG_L2ACTLR_EL1)
3889      .allPrivileges().exceptUserMode();
3890    InitReg(MISCREG_CPUACTLR_EL1)
3891      .allPrivileges().exceptUserMode();
3892    InitReg(MISCREG_CPUECTLR_EL1)
3893      .allPrivileges().exceptUserMode();
3894    InitReg(MISCREG_CPUMERRSR_EL1)
3895      .allPrivileges().exceptUserMode();
3896    InitReg(MISCREG_L2MERRSR_EL1)
3897      .unimplemented()
3898      .warnNotFail()
3899      .allPrivileges().exceptUserMode();
3900    InitReg(MISCREG_CBAR_EL1)
3901      .allPrivileges().exceptUserMode().writes(0);
3902    InitReg(MISCREG_CONTEXTIDR_EL2)
3903      .mon().hyp();
3904
3905    // Dummy registers
3906    InitReg(MISCREG_NOP)
3907      .allPrivileges();
3908    InitReg(MISCREG_RAZ)
3909      .allPrivileges().exceptUserMode().writes(0);
3910    InitReg(MISCREG_CP14_UNIMPL)
3911      .unimplemented()
3912      .warnNotFail();
3913    InitReg(MISCREG_CP15_UNIMPL)
3914      .unimplemented()
3915      .warnNotFail();
3916    InitReg(MISCREG_A64_UNIMPL)
3917      .unimplemented()
3918      .warnNotFail();
3919    InitReg(MISCREG_UNKNOWN);
3920
3921    // Register mappings for some unimplemented registers:
3922    // ESR_EL1 -> DFSR
3923    // RMR_EL1 -> RMR
3924    // RMR_EL2 -> HRMR
3925    // DBGDTR_EL0 -> DBGDTR{R or T}Xint
3926    // DBGDTRRX_EL0 -> DBGDTRRXint
3927    // DBGDTRTX_EL0 -> DBGDTRRXint
3928    // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
3929
3930    completed = true;
3931}
3932
3933} // namespace ArmISA
3934