miscregs.cc revision 11587:b7c4aa85db2a
1/*
2 * Copyright (c) 2010-2013, 2015-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 *          Giacomo Gabrielli
40 */
41
42#include "arch/arm/isa.hh"
43#include "arch/arm/miscregs.hh"
44#include "base/misc.hh"
45#include "cpu/thread_context.hh"
46#include "sim/full_system.hh"
47
48namespace ArmISA
49{
50
51MiscRegIndex
52decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
53{
54    switch(crn) {
55      case 0:
56        switch (opc1) {
57          case 0:
58            switch (opc2) {
59              case 0:
60                switch (crm) {
61                  case 0:
62                    return MISCREG_DBGDIDR;
63                  case 1:
64                    return MISCREG_DBGDSCRint;
65                }
66                break;
67            }
68            break;
69          case 7:
70            switch (opc2) {
71              case 0:
72                switch (crm) {
73                  case 0:
74                    return MISCREG_JIDR;
75                }
76              break;
77            }
78            break;
79        }
80        break;
81      case 1:
82        switch (opc1) {
83          case 6:
84            switch (crm) {
85              case 0:
86                switch (opc2) {
87                  case 0:
88                    return MISCREG_TEEHBR;
89                }
90                break;
91            }
92            break;
93          case 7:
94            switch (crm) {
95              case 0:
96                switch (opc2) {
97                  case 0:
98                    return MISCREG_JOSCR;
99                }
100                break;
101            }
102            break;
103        }
104        break;
105      case 2:
106        switch (opc1) {
107          case 7:
108            switch (crm) {
109              case 0:
110                switch (opc2) {
111                  case 0:
112                    return MISCREG_JMCR;
113                }
114                break;
115            }
116            break;
117        }
118        break;
119    }
120    // If we get here then it must be a register that we haven't implemented
121    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
122         crn, opc1, crm, opc2);
123    return MISCREG_CP14_UNIMPL;
124}
125
126using namespace std;
127
128bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
129    // MISCREG_CPSR
130    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
131    // MISCREG_SPSR
132    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
133    // MISCREG_SPSR_FIQ
134    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
135    // MISCREG_SPSR_IRQ
136    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
137    // MISCREG_SPSR_SVC
138    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
139    // MISCREG_SPSR_MON
140    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
141    // MISCREG_SPSR_ABT
142    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
143    // MISCREG_SPSR_HYP
144    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
145    // MISCREG_SPSR_UND
146    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
147    // MISCREG_ELR_HYP
148    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
149    // MISCREG_FPSID
150    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
151    // MISCREG_FPSCR
152    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
153    // MISCREG_MVFR1
154    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
155    // MISCREG_MVFR0
156    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
157    // MISCREG_FPEXC
158    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
159
160    // Helper registers
161    // MISCREG_CPSR_MODE
162    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
163    // MISCREG_CPSR_Q
164    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
165    // MISCREG_FPSCR_Q
166    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
167    // MISCREG_FPSCR_EXC
168    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
169    // MISCREG_LOCKADDR
170    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
171    // MISCREG_LOCKFLAG
172    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
173    // MISCREG_PRRR_MAIR0
174    bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")),
175    // MISCREG_PRRR_MAIR0_NS
176    bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
177    // MISCREG_PRRR_MAIR0_S
178    bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
179    // MISCREG_NMRR_MAIR1
180    bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")),
181    // MISCREG_NMRR_MAIR1_NS
182    bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
183    // MISCREG_NMRR_MAIR1_S
184    bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
185    // MISCREG_PMXEVTYPER_PMCCFILTR
186    bitset<NUM_MISCREG_INFOS>(string("00000000000000001001")),
187    // MISCREG_SCTLR_RST
188    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
189    // MISCREG_SEV_MAILBOX
190    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
191
192    // AArch32 CP14 registers
193    // MISCREG_DBGDIDR
194    bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
195    // MISCREG_DBGDSCRint
196    bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
197    // MISCREG_DBGDCCINT
198    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
199    // MISCREG_DBGDTRTXint
200    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
201    // MISCREG_DBGDTRRXint
202    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
203    // MISCREG_DBGWFAR
204    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
205    // MISCREG_DBGVCR
206    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
207    // MISCREG_DBGDTRRXext
208    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
209    // MISCREG_DBGDSCRext
210    bitset<NUM_MISCREG_INFOS>(string("11111111111111000100")),
211    // MISCREG_DBGDTRTXext
212    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
213    // MISCREG_DBGOSECCR
214    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
215    // MISCREG_DBGBVR0
216    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
217    // MISCREG_DBGBVR1
218    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
219    // MISCREG_DBGBVR2
220    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
221    // MISCREG_DBGBVR3
222    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
223    // MISCREG_DBGBVR4
224    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
225    // MISCREG_DBGBVR5
226    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
227    // MISCREG_DBGBCR0
228    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
229    // MISCREG_DBGBCR1
230    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
231    // MISCREG_DBGBCR2
232    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
233    // MISCREG_DBGBCR3
234    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
235    // MISCREG_DBGBCR4
236    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
237    // MISCREG_DBGBCR5
238    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
239    // MISCREG_DBGWVR0
240    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
241    // MISCREG_DBGWVR1
242    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
243    // MISCREG_DBGWVR2
244    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
245    // MISCREG_DBGWVR3
246    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
247    // MISCREG_DBGWCR0
248    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
249    // MISCREG_DBGWCR1
250    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
251    // MISCREG_DBGWCR2
252    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
253    // MISCREG_DBGWCR3
254    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
255    // MISCREG_DBGDRAR
256    bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
257    // MISCREG_DBGBXVR4
258    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
259    // MISCREG_DBGBXVR5
260    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
261    // MISCREG_DBGOSLAR
262    bitset<NUM_MISCREG_INFOS>(string("10101111111111000000")),
263    // MISCREG_DBGOSLSR
264    bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
265    // MISCREG_DBGOSDLR
266    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
267    // MISCREG_DBGPRCR
268    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
269    // MISCREG_DBGDSAR
270    bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
271    // MISCREG_DBGCLAIMSET
272    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
273    // MISCREG_DBGCLAIMCLR
274    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
275    // MISCREG_DBGAUTHSTATUS
276    bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
277    // MISCREG_DBGDEVID2
278    bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
279    // MISCREG_DBGDEVID1
280    bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
281    // MISCREG_DBGDEVID0
282    bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
283    // MISCREG_TEECR
284    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
285    // MISCREG_JIDR
286    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
287    // MISCREG_TEEHBR
288    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
289    // MISCREG_JOSCR
290    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
291    // MISCREG_JMCR
292    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
293
294    // AArch32 CP15 registers
295    // MISCREG_MIDR
296    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
297    // MISCREG_CTR
298    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
299    // MISCREG_TCMTR
300    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
301    // MISCREG_TLBTR
302    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
303    // MISCREG_MPIDR
304    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
305    // MISCREG_REVIDR
306    bitset<NUM_MISCREG_INFOS>(string("01010101010000000100")),
307    // MISCREG_ID_PFR0
308    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
309    // MISCREG_ID_PFR1
310    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
311    // MISCREG_ID_DFR0
312    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
313    // MISCREG_ID_AFR0
314    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
315    // MISCREG_ID_MMFR0
316    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
317    // MISCREG_ID_MMFR1
318    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
319    // MISCREG_ID_MMFR2
320    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
321    // MISCREG_ID_MMFR3
322    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
323    // MISCREG_ID_ISAR0
324    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
325    // MISCREG_ID_ISAR1
326    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
327    // MISCREG_ID_ISAR2
328    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
329    // MISCREG_ID_ISAR3
330    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
331    // MISCREG_ID_ISAR4
332    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
333    // MISCREG_ID_ISAR5
334    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
335    // MISCREG_CCSIDR
336    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
337    // MISCREG_CLIDR
338    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
339    // MISCREG_AIDR
340    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
341    // MISCREG_CSSELR
342    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
343    // MISCREG_CSSELR_NS
344    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
345    // MISCREG_CSSELR_S
346    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
347    // MISCREG_VPIDR
348    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
349    // MISCREG_VMPIDR
350    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
351    // MISCREG_SCTLR
352    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
353    // MISCREG_SCTLR_NS
354    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
355    // MISCREG_SCTLR_S
356    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
357    // MISCREG_ACTLR
358    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
359    // MISCREG_ACTLR_NS
360    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
361    // MISCREG_ACTLR_S
362    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
363    // MISCREG_CPACR
364    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
365    // MISCREG_SCR
366    bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")),
367    // MISCREG_SDER
368    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
369    // MISCREG_NSACR
370    bitset<NUM_MISCREG_INFOS>(string("11110111010000000001")),
371    // MISCREG_HSCTLR
372    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
373    // MISCREG_HACTLR
374    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
375    // MISCREG_HCR
376    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
377    // MISCREG_HDCR
378    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
379    // MISCREG_HCPTR
380    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
381    // MISCREG_HSTR
382    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
383    // MISCREG_HACR
384    bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
385    // MISCREG_TTBR0
386    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
387    // MISCREG_TTBR0_NS
388    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
389    // MISCREG_TTBR0_S
390    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
391    // MISCREG_TTBR1
392    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
393    // MISCREG_TTBR1_NS
394    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
395    // MISCREG_TTBR1_S
396    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
397    // MISCREG_TTBCR
398    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
399    // MISCREG_TTBCR_NS
400    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
401    // MISCREG_TTBCR_S
402    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
403    // MISCREG_HTCR
404    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
405    // MISCREG_VTCR
406    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
407    // MISCREG_DACR
408    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
409    // MISCREG_DACR_NS
410    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
411    // MISCREG_DACR_S
412    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
413    // MISCREG_DFSR
414    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
415    // MISCREG_DFSR_NS
416    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
417    // MISCREG_DFSR_S
418    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
419    // MISCREG_IFSR
420    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
421    // MISCREG_IFSR_NS
422    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
423    // MISCREG_IFSR_S
424    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
425    // MISCREG_ADFSR
426    bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")),
427    // MISCREG_ADFSR_NS
428    bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")),
429    // MISCREG_ADFSR_S
430    bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")),
431    // MISCREG_AIFSR
432    bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")),
433    // MISCREG_AIFSR_NS
434    bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")),
435    // MISCREG_AIFSR_S
436    bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")),
437    // MISCREG_HADFSR
438    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
439    // MISCREG_HAIFSR
440    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
441    // MISCREG_HSR
442    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
443    // MISCREG_DFAR
444    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
445    // MISCREG_DFAR_NS
446    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
447    // MISCREG_DFAR_S
448    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
449    // MISCREG_IFAR
450    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
451    // MISCREG_IFAR_NS
452    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
453    // MISCREG_IFAR_S
454    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
455    // MISCREG_HDFAR
456    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
457    // MISCREG_HIFAR
458    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
459    // MISCREG_HPFAR
460    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
461    // MISCREG_ICIALLUIS
462    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
463    // MISCREG_BPIALLIS
464    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
465    // MISCREG_PAR
466    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
467    // MISCREG_PAR_NS
468    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
469    // MISCREG_PAR_S
470    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
471    // MISCREG_ICIALLU
472    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
473    // MISCREG_ICIMVAU
474    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
475    // MISCREG_CP15ISB
476    bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
477    // MISCREG_BPIALL
478    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
479    // MISCREG_BPIMVA
480    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
481    // MISCREG_DCIMVAC
482    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
483    // MISCREG_DCISW
484    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
485    // MISCREG_ATS1CPR
486    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
487    // MISCREG_ATS1CPW
488    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
489    // MISCREG_ATS1CUR
490    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
491    // MISCREG_ATS1CUW
492    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
493    // MISCREG_ATS12NSOPR
494    bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
495    // MISCREG_ATS12NSOPW
496    bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
497    // MISCREG_ATS12NSOUR
498    bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
499    // MISCREG_ATS12NSOUW
500    bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
501    // MISCREG_DCCMVAC
502    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
503    // MISCREG_DCCSW
504    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
505    // MISCREG_CP15DSB
506    bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
507    // MISCREG_CP15DMB
508    bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
509    // MISCREG_DCCMVAU
510    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
511    // MISCREG_DCCIMVAC
512    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
513    // MISCREG_DCCISW
514    bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
515    // MISCREG_ATS1HR
516    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
517    // MISCREG_ATS1HW
518    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
519    // MISCREG_TLBIALLIS
520    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
521    // MISCREG_TLBIMVAIS
522    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
523    // MISCREG_TLBIASIDIS
524    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
525    // MISCREG_TLBIMVAAIS
526    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
527    // MISCREG_TLBIMVALIS
528    bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
529    // MISCREG_TLBIMVAALIS
530    bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
531    // MISCREG_ITLBIALL
532    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
533    // MISCREG_ITLBIMVA
534    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
535    // MISCREG_ITLBIASID
536    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
537    // MISCREG_DTLBIALL
538    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
539    // MISCREG_DTLBIMVA
540    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
541    // MISCREG_DTLBIASID
542    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
543    // MISCREG_TLBIALL
544    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
545    // MISCREG_TLBIMVA
546    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
547    // MISCREG_TLBIASID
548    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
549    // MISCREG_TLBIMVAA
550    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
551    // MISCREG_TLBIMVAL
552    bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
553    // MISCREG_TLBIMVAAL
554    bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
555    // MISCREG_TLBIIPAS2IS
556    bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
557    // MISCREG_TLBIIPAS2LIS
558    bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
559    // MISCREG_TLBIALLHIS
560    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
561    // MISCREG_TLBIMVAHIS
562    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
563    // MISCREG_TLBIALLNSNHIS
564    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
565    // MISCREG_TLBIMVALHIS
566    bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
567    // MISCREG_TLBIIPAS2
568    bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
569    // MISCREG_TLBIIPAS2L
570    bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
571    // MISCREG_TLBIALLH
572    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
573    // MISCREG_TLBIMVAH
574    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
575    // MISCREG_TLBIALLNSNH
576    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
577    // MISCREG_TLBIMVALH
578    bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
579    // MISCREG_PMCR
580    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
581    // MISCREG_PMCNTENSET
582    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
583    // MISCREG_PMCNTENCLR
584    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
585    // MISCREG_PMOVSR
586    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
587    // MISCREG_PMSWINC
588    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
589    // MISCREG_PMSELR
590    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
591    // MISCREG_PMCEID0
592    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
593    // MISCREG_PMCEID1
594    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
595    // MISCREG_PMCCNTR
596    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
597    // MISCREG_PMXEVTYPER
598    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
599    // MISCREG_PMCCFILTR
600    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
601    // MISCREG_PMXEVCNTR
602    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
603    // MISCREG_PMUSERENR
604    bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
605    // MISCREG_PMINTENSET
606    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
607    // MISCREG_PMINTENCLR
608    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
609    // MISCREG_PMOVSSET
610    bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
611    // MISCREG_L2CTLR
612    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
613    // MISCREG_L2ECTLR
614    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
615    // MISCREG_PRRR
616    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
617    // MISCREG_PRRR_NS
618    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
619    // MISCREG_PRRR_S
620    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
621    // MISCREG_MAIR0
622    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
623    // MISCREG_MAIR0_NS
624    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
625    // MISCREG_MAIR0_S
626    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
627    // MISCREG_NMRR
628    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
629    // MISCREG_NMRR_NS
630    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
631    // MISCREG_NMRR_S
632    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
633    // MISCREG_MAIR1
634    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
635    // MISCREG_MAIR1_NS
636    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
637    // MISCREG_MAIR1_S
638    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
639    // MISCREG_AMAIR0
640    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
641    // MISCREG_AMAIR0_NS
642    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
643    // MISCREG_AMAIR0_S
644    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
645    // MISCREG_AMAIR1
646    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
647    // MISCREG_AMAIR1_NS
648    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
649    // MISCREG_AMAIR1_S
650    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
651    // MISCREG_HMAIR0
652    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
653    // MISCREG_HMAIR1
654    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
655    // MISCREG_HAMAIR0
656    bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
657    // MISCREG_HAMAIR1
658    bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
659    // MISCREG_VBAR
660    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
661    // MISCREG_VBAR_NS
662    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
663    // MISCREG_VBAR_S
664    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
665    // MISCREG_MVBAR
666    bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")),
667    // MISCREG_RMR
668    bitset<NUM_MISCREG_INFOS>(string("11110011000000000000")),
669    // MISCREG_ISR
670    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
671    // MISCREG_HVBAR
672    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
673    // MISCREG_FCSEIDR
674    bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
675    // MISCREG_CONTEXTIDR
676    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
677    // MISCREG_CONTEXTIDR_NS
678    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
679    // MISCREG_CONTEXTIDR_S
680    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
681    // MISCREG_TPIDRURW
682    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
683    // MISCREG_TPIDRURW_NS
684    bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
685    // MISCREG_TPIDRURW_S
686    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
687    // MISCREG_TPIDRURO
688    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
689    // MISCREG_TPIDRURO_NS
690    bitset<NUM_MISCREG_INFOS>(string("11001100110101100001")),
691    // MISCREG_TPIDRURO_S
692    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
693    // MISCREG_TPIDRPRW
694    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
695    // MISCREG_TPIDRPRW_NS
696    bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
697    // MISCREG_TPIDRPRW_S
698    bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
699    // MISCREG_HTPIDR
700    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
701    // MISCREG_CNTFRQ
702    bitset<NUM_MISCREG_INFOS>(string("11110101010101000011")),
703    // MISCREG_CNTKCTL
704    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
705    // MISCREG_CNTP_TVAL
706    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
707    // MISCREG_CNTP_TVAL_NS
708    bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
709    // MISCREG_CNTP_TVAL_S
710    bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
711    // MISCREG_CNTP_CTL
712    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
713    // MISCREG_CNTP_CTL_NS
714    bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
715    // MISCREG_CNTP_CTL_S
716    bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
717    // MISCREG_CNTV_TVAL
718    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
719    // MISCREG_CNTV_CTL
720    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
721    // MISCREG_CNTHCTL
722    bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
723    // MISCREG_CNTHP_TVAL
724    bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
725    // MISCREG_CNTHP_CTL
726    bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
727    // MISCREG_IL1DATA0
728    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
729    // MISCREG_IL1DATA1
730    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
731    // MISCREG_IL1DATA2
732    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
733    // MISCREG_IL1DATA3
734    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
735    // MISCREG_DL1DATA0
736    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
737    // MISCREG_DL1DATA1
738    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
739    // MISCREG_DL1DATA2
740    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
741    // MISCREG_DL1DATA3
742    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
743    // MISCREG_DL1DATA4
744    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
745    // MISCREG_RAMINDEX
746    bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
747    // MISCREG_L2ACTLR
748    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
749    // MISCREG_CBAR
750    bitset<NUM_MISCREG_INFOS>(string("01010101010000000000")),
751    // MISCREG_HTTBR
752    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
753    // MISCREG_VTTBR
754    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
755    // MISCREG_CNTPCT
756    bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
757    // MISCREG_CNTVCT
758    bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")),
759    // MISCREG_CNTP_CVAL
760    bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
761    // MISCREG_CNTP_CVAL_NS
762    bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
763    // MISCREG_CNTP_CVAL_S
764    bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
765    // MISCREG_CNTV_CVAL
766    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
767    // MISCREG_CNTVOFF
768    bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
769    // MISCREG_CNTHP_CVAL
770    bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
771    // MISCREG_CPUMERRSR
772    bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
773    // MISCREG_L2MERRSR
774    bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
775
776    // AArch64 registers (Op0=2)
777    // MISCREG_MDCCINT_EL1
778    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
779    // MISCREG_OSDTRRX_EL1
780    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
781    // MISCREG_MDSCR_EL1
782    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
783    // MISCREG_OSDTRTX_EL1
784    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
785    // MISCREG_OSECCR_EL1
786    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
787    // MISCREG_DBGBVR0_EL1
788    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
789    // MISCREG_DBGBVR1_EL1
790    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
791    // MISCREG_DBGBVR2_EL1
792    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
793    // MISCREG_DBGBVR3_EL1
794    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
795    // MISCREG_DBGBVR4_EL1
796    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
797    // MISCREG_DBGBVR5_EL1
798    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
799    // MISCREG_DBGBCR0_EL1
800    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
801    // MISCREG_DBGBCR1_EL1
802    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
803    // MISCREG_DBGBCR2_EL1
804    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
805    // MISCREG_DBGBCR3_EL1
806    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
807    // MISCREG_DBGBCR4_EL1
808    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
809    // MISCREG_DBGBCR5_EL1
810    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
811    // MISCREG_DBGWVR0_EL1
812    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
813    // MISCREG_DBGWVR1_EL1
814    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
815    // MISCREG_DBGWVR2_EL1
816    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
817    // MISCREG_DBGWVR3_EL1
818    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
819    // MISCREG_DBGWCR0_EL1
820    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
821    // MISCREG_DBGWCR1_EL1
822    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
823    // MISCREG_DBGWCR2_EL1
824    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
825    // MISCREG_DBGWCR3_EL1
826    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
827    // MISCREG_MDCCSR_EL0
828    bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
829    // MISCREG_MDDTR_EL0
830    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
831    // MISCREG_MDDTRTX_EL0
832    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
833    // MISCREG_MDDTRRX_EL0
834    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
835    // MISCREG_DBGVCR32_EL2
836    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
837    // MISCREG_MDRAR_EL1
838    bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
839    // MISCREG_OSLAR_EL1
840    bitset<NUM_MISCREG_INFOS>(string("10101111111111000001")),
841    // MISCREG_OSLSR_EL1
842    bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
843    // MISCREG_OSDLR_EL1
844    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
845    // MISCREG_DBGPRCR_EL1
846    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
847    // MISCREG_DBGCLAIMSET_EL1
848    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
849    // MISCREG_DBGCLAIMCLR_EL1
850    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
851    // MISCREG_DBGAUTHSTATUS_EL1
852    bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
853    // MISCREG_TEECR32_EL1
854    bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")),
855    // MISCREG_TEEHBR32_EL1
856    bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")),
857
858    // AArch64 registers (Op0=1,3)
859    // MISCREG_MIDR_EL1
860    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
861    // MISCREG_MPIDR_EL1
862    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
863    // MISCREG_REVIDR_EL1
864    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
865    // MISCREG_ID_PFR0_EL1
866    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
867    // MISCREG_ID_PFR1_EL1
868    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
869    // MISCREG_ID_DFR0_EL1
870    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
871    // MISCREG_ID_AFR0_EL1
872    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
873    // MISCREG_ID_MMFR0_EL1
874    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
875    // MISCREG_ID_MMFR1_EL1
876    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
877    // MISCREG_ID_MMFR2_EL1
878    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
879    // MISCREG_ID_MMFR3_EL1
880    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
881    // MISCREG_ID_ISAR0_EL1
882    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
883    // MISCREG_ID_ISAR1_EL1
884    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
885    // MISCREG_ID_ISAR2_EL1
886    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
887    // MISCREG_ID_ISAR3_EL1
888    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
889    // MISCREG_ID_ISAR4_EL1
890    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
891    // MISCREG_ID_ISAR5_EL1
892    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
893    // MISCREG_MVFR0_EL1
894    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
895    // MISCREG_MVFR1_EL1
896    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
897    // MISCREG_MVFR2_EL1
898    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
899    // MISCREG_ID_AA64PFR0_EL1
900    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
901    // MISCREG_ID_AA64PFR1_EL1
902    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
903    // MISCREG_ID_AA64DFR0_EL1
904    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
905    // MISCREG_ID_AA64DFR1_EL1
906    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
907    // MISCREG_ID_AA64AFR0_EL1
908    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
909    // MISCREG_ID_AA64AFR1_EL1
910    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
911    // MISCREG_ID_AA64ISAR0_EL1
912    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
913    // MISCREG_ID_AA64ISAR1_EL1
914    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
915    // MISCREG_ID_AA64MMFR0_EL1
916    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
917    // MISCREG_ID_AA64MMFR1_EL1
918    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
919    // MISCREG_CCSIDR_EL1
920    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
921    // MISCREG_CLIDR_EL1
922    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
923    // MISCREG_AIDR_EL1
924    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
925    // MISCREG_CSSELR_EL1
926    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
927    // MISCREG_CTR_EL0
928    bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
929    // MISCREG_DCZID_EL0
930    bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
931    // MISCREG_VPIDR_EL2
932    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
933    // MISCREG_VMPIDR_EL2
934    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
935    // MISCREG_SCTLR_EL1
936    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
937    // MISCREG_ACTLR_EL1
938    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
939    // MISCREG_CPACR_EL1
940    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
941    // MISCREG_SCTLR_EL2
942    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
943    // MISCREG_ACTLR_EL2
944    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
945    // MISCREG_HCR_EL2
946    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
947    // MISCREG_MDCR_EL2
948    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
949    // MISCREG_CPTR_EL2
950    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
951    // MISCREG_HSTR_EL2
952    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
953    // MISCREG_HACR_EL2
954    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
955    // MISCREG_SCTLR_EL3
956    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
957    // MISCREG_ACTLR_EL3
958    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
959    // MISCREG_SCR_EL3
960    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
961    // MISCREG_SDER32_EL3
962    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
963    // MISCREG_CPTR_EL3
964    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
965    // MISCREG_MDCR_EL3
966    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
967    // MISCREG_TTBR0_EL1
968    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
969    // MISCREG_TTBR1_EL1
970    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
971    // MISCREG_TCR_EL1
972    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
973    // MISCREG_TTBR0_EL2
974    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
975    // MISCREG_TCR_EL2
976    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
977    // MISCREG_VTTBR_EL2
978    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
979    // MISCREG_VTCR_EL2
980    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
981    // MISCREG_TTBR0_EL3
982    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
983    // MISCREG_TCR_EL3
984    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
985    // MISCREG_DACR32_EL2
986    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
987    // MISCREG_SPSR_EL1
988    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
989    // MISCREG_ELR_EL1
990    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
991    // MISCREG_SP_EL0
992    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
993    // MISCREG_SPSEL
994    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
995    // MISCREG_CURRENTEL
996    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
997    // MISCREG_NZCV
998    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
999    // MISCREG_DAIF
1000    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1001    // MISCREG_FPCR
1002    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1003    // MISCREG_FPSR
1004    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1005    // MISCREG_DSPSR_EL0
1006    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1007    // MISCREG_DLR_EL0
1008    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1009    // MISCREG_SPSR_EL2
1010    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1011    // MISCREG_ELR_EL2
1012    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1013    // MISCREG_SP_EL1
1014    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1015    // MISCREG_SPSR_IRQ_AA64
1016    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1017    // MISCREG_SPSR_ABT_AA64
1018    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1019    // MISCREG_SPSR_UND_AA64
1020    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1021    // MISCREG_SPSR_FIQ_AA64
1022    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1023    // MISCREG_SPSR_EL3
1024    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1025    // MISCREG_ELR_EL3
1026    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1027    // MISCREG_SP_EL2
1028    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1029    // MISCREG_AFSR0_EL1
1030    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1031    // MISCREG_AFSR1_EL1
1032    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1033    // MISCREG_ESR_EL1
1034    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1035    // MISCREG_IFSR32_EL2
1036    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1037    // MISCREG_AFSR0_EL2
1038    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1039    // MISCREG_AFSR1_EL2
1040    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1041    // MISCREG_ESR_EL2
1042    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1043    // MISCREG_FPEXC32_EL2
1044    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1045    // MISCREG_AFSR0_EL3
1046    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1047    // MISCREG_AFSR1_EL3
1048    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1049    // MISCREG_ESR_EL3
1050    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1051    // MISCREG_FAR_EL1
1052    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1053    // MISCREG_FAR_EL2
1054    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1055    // MISCREG_HPFAR_EL2
1056    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1057    // MISCREG_FAR_EL3
1058    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1059    // MISCREG_IC_IALLUIS
1060    bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1061    // MISCREG_PAR_EL1
1062    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1063    // MISCREG_IC_IALLU
1064    bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1065    // MISCREG_DC_IVAC_Xt
1066    bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1067    // MISCREG_DC_ISW_Xt
1068    bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1069    // MISCREG_AT_S1E1R_Xt
1070    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1071    // MISCREG_AT_S1E1W_Xt
1072    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1073    // MISCREG_AT_S1E0R_Xt
1074    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1075    // MISCREG_AT_S1E0W_Xt
1076    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1077    // MISCREG_DC_CSW_Xt
1078    bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1079    // MISCREG_DC_CISW_Xt
1080    bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1081    // MISCREG_DC_ZVA_Xt
1082    bitset<NUM_MISCREG_INFOS>(string("10101010100010000101")),
1083    // MISCREG_IC_IVAU_Xt
1084    bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
1085    // MISCREG_DC_CVAC_Xt
1086    bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1087    // MISCREG_DC_CVAU_Xt
1088    bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1089    // MISCREG_DC_CIVAC_Xt
1090    bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1091    // MISCREG_AT_S1E2R_Xt
1092    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1093    // MISCREG_AT_S1E2W_Xt
1094    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1095    // MISCREG_AT_S12E1R_Xt
1096    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1097    // MISCREG_AT_S12E1W_Xt
1098    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1099    // MISCREG_AT_S12E0R_Xt
1100    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1101    // MISCREG_AT_S12E0W_Xt
1102    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1103    // MISCREG_AT_S1E3R_Xt
1104    bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1105    // MISCREG_AT_S1E3W_Xt
1106    bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1107    // MISCREG_TLBI_VMALLE1IS
1108    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1109    // MISCREG_TLBI_VAE1IS_Xt
1110    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1111    // MISCREG_TLBI_ASIDE1IS_Xt
1112    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1113    // MISCREG_TLBI_VAAE1IS_Xt
1114    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1115    // MISCREG_TLBI_VALE1IS_Xt
1116    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1117    // MISCREG_TLBI_VAALE1IS_Xt
1118    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1119    // MISCREG_TLBI_VMALLE1
1120    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1121    // MISCREG_TLBI_VAE1_Xt
1122    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1123    // MISCREG_TLBI_ASIDE1_Xt
1124    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1125    // MISCREG_TLBI_VAAE1_Xt
1126    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1127    // MISCREG_TLBI_VALE1_Xt
1128    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1129    // MISCREG_TLBI_VAALE1_Xt
1130    bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1131    // MISCREG_TLBI_IPAS2E1IS_Xt
1132    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1133    // MISCREG_TLBI_IPAS2LE1IS_Xt
1134    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1135    // MISCREG_TLBI_ALLE2IS
1136    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1137    // MISCREG_TLBI_VAE2IS_Xt
1138    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1139    // MISCREG_TLBI_ALLE1IS
1140    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1141    // MISCREG_TLBI_VALE2IS_Xt
1142    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1143    // MISCREG_TLBI_VMALLS12E1IS
1144    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1145    // MISCREG_TLBI_IPAS2E1_Xt
1146    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1147    // MISCREG_TLBI_IPAS2LE1_Xt
1148    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1149    // MISCREG_TLBI_ALLE2
1150    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1151    // MISCREG_TLBI_VAE2_Xt
1152    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1153    // MISCREG_TLBI_ALLE1
1154    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1155    // MISCREG_TLBI_VALE2_Xt
1156    bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1157    // MISCREG_TLBI_VMALLS12E1
1158    bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1159    // MISCREG_TLBI_ALLE3IS
1160    bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1161    // MISCREG_TLBI_VAE3IS_Xt
1162    bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1163    // MISCREG_TLBI_VALE3IS_Xt
1164    bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1165    // MISCREG_TLBI_ALLE3
1166    bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1167    // MISCREG_TLBI_VAE3_Xt
1168    bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1169    // MISCREG_TLBI_VALE3_Xt
1170    bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1171    // MISCREG_PMINTENSET_EL1
1172    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1173    // MISCREG_PMINTENCLR_EL1
1174    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1175    // MISCREG_PMCR_EL0
1176    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1177    // MISCREG_PMCNTENSET_EL0
1178    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1179    // MISCREG_PMCNTENCLR_EL0
1180    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1181    // MISCREG_PMOVSCLR_EL0
1182    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1183    // MISCREG_PMSWINC_EL0
1184    bitset<NUM_MISCREG_INFOS>(string("10101010101111000001")),
1185    // MISCREG_PMSELR_EL0
1186    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1187    // MISCREG_PMCEID0_EL0
1188    bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")),
1189    // MISCREG_PMCEID1_EL0
1190    bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")),
1191    // MISCREG_PMCCNTR_EL0
1192    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1193    // MISCREG_PMXEVTYPER_EL0
1194    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1195    // MISCREG_PMCCFILTR_EL0
1196    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1197    // MISCREG_PMXEVCNTR_EL0
1198    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1199    // MISCREG_PMUSERENR_EL0
1200    bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
1201    // MISCREG_PMOVSSET_EL0
1202    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1203    // MISCREG_MAIR_EL1
1204    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1205    // MISCREG_AMAIR_EL1
1206    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1207    // MISCREG_MAIR_EL2
1208    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1209    // MISCREG_AMAIR_EL2
1210    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1211    // MISCREG_MAIR_EL3
1212    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1213    // MISCREG_AMAIR_EL3
1214    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1215    // MISCREG_L2CTLR_EL1
1216    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1217    // MISCREG_L2ECTLR_EL1
1218    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1219    // MISCREG_VBAR_EL1
1220    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1221    // MISCREG_RVBAR_EL1
1222    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1223    // MISCREG_ISR_EL1
1224    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1225    // MISCREG_VBAR_EL2
1226    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1227    // MISCREG_RVBAR_EL2
1228    bitset<NUM_MISCREG_INFOS>(string("01010100000000000001")),
1229    // MISCREG_VBAR_EL3
1230    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1231    // MISCREG_RVBAR_EL3
1232    bitset<NUM_MISCREG_INFOS>(string("01010000000000000001")),
1233    // MISCREG_RMR_EL3
1234    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1235    // MISCREG_CONTEXTIDR_EL1
1236    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1237    // MISCREG_TPIDR_EL1
1238    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1239    // MISCREG_TPIDR_EL0
1240    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1241    // MISCREG_TPIDRRO_EL0
1242    bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
1243    // MISCREG_TPIDR_EL2
1244    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1245    // MISCREG_TPIDR_EL3
1246    bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1247    // MISCREG_CNTKCTL_EL1
1248    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1249    // MISCREG_CNTFRQ_EL0
1250    bitset<NUM_MISCREG_INFOS>(string("11110101010101000001")),
1251    // MISCREG_CNTPCT_EL0
1252    bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
1253    // MISCREG_CNTVCT_EL0
1254    bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")),
1255    // MISCREG_CNTP_TVAL_EL0
1256    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1257    // MISCREG_CNTP_CTL_EL0
1258    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1259    // MISCREG_CNTP_CVAL_EL0
1260    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1261    // MISCREG_CNTV_TVAL_EL0
1262    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1263    // MISCREG_CNTV_CTL_EL0
1264    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1265    // MISCREG_CNTV_CVAL_EL0
1266    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1267    // MISCREG_PMEVCNTR0_EL0
1268    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1269    // MISCREG_PMEVCNTR1_EL0
1270    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1271    // MISCREG_PMEVCNTR2_EL0
1272    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1273    // MISCREG_PMEVCNTR3_EL0
1274    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1275    // MISCREG_PMEVCNTR4_EL0
1276    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1277    // MISCREG_PMEVCNTR5_EL0
1278    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1279    // MISCREG_PMEVTYPER0_EL0
1280    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1281    // MISCREG_PMEVTYPER1_EL0
1282    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1283    // MISCREG_PMEVTYPER2_EL0
1284    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1285    // MISCREG_PMEVTYPER3_EL0
1286    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1287    // MISCREG_PMEVTYPER4_EL0
1288    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1289    // MISCREG_PMEVTYPER5_EL0
1290    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1291    // MISCREG_CNTVOFF_EL2
1292    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1293    // MISCREG_CNTHCTL_EL2
1294    bitset<NUM_MISCREG_INFOS>(string("01111000000000000100")),
1295    // MISCREG_CNTHP_TVAL_EL2
1296    bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1297    // MISCREG_CNTHP_CTL_EL2
1298    bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1299    // MISCREG_CNTHP_CVAL_EL2
1300    bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1301    // MISCREG_CNTPS_TVAL_EL1
1302    bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1303    // MISCREG_CNTPS_CTL_EL1
1304    bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1305    // MISCREG_CNTPS_CVAL_EL1
1306    bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1307    // MISCREG_IL1DATA0_EL1
1308    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1309    // MISCREG_IL1DATA1_EL1
1310    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1311    // MISCREG_IL1DATA2_EL1
1312    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1313    // MISCREG_IL1DATA3_EL1
1314    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1315    // MISCREG_DL1DATA0_EL1
1316    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1317    // MISCREG_DL1DATA1_EL1
1318    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1319    // MISCREG_DL1DATA2_EL1
1320    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1321    // MISCREG_DL1DATA3_EL1
1322    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1323    // MISCREG_DL1DATA4_EL1
1324    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1325    // MISCREG_L2ACTLR_EL1
1326    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1327    // MISCREG_CPUACTLR_EL1
1328    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1329    // MISCREG_CPUECTLR_EL1
1330    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1331    // MISCREG_CPUMERRSR_EL1
1332    bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1333    // MISCREG_L2MERRSR_EL1
1334    bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
1335    // MISCREG_CBAR_EL1
1336    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1337    // MISCREG_CONTEXTIDR_EL2
1338    bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1339
1340    // Dummy registers
1341    // MISCREG_NOP
1342    bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1343    // MISCREG_RAZ
1344    bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1345    // MISCREG_CP14_UNIMPL
1346    bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
1347    // MISCREG_CP15_UNIMPL
1348    bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
1349    // MISCREG_A64_UNIMPL
1350    bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
1351    // MISCREG_UNKNOWN
1352    bitset<NUM_MISCREG_INFOS>(string("00000000000000000001"))
1353};
1354
1355MiscRegIndex
1356decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
1357{
1358    switch (crn) {
1359      case 0:
1360        switch (opc1) {
1361          case 0:
1362            switch (crm) {
1363              case 0:
1364                switch (opc2) {
1365                  case 1:
1366                    return MISCREG_CTR;
1367                  case 2:
1368                    return MISCREG_TCMTR;
1369                  case 3:
1370                    return MISCREG_TLBTR;
1371                  case 5:
1372                    return MISCREG_MPIDR;
1373                  case 6:
1374                    return MISCREG_REVIDR;
1375                  default:
1376                    return MISCREG_MIDR;
1377                }
1378                break;
1379              case 1:
1380                switch (opc2) {
1381                  case 0:
1382                    return MISCREG_ID_PFR0;
1383                  case 1:
1384                    return MISCREG_ID_PFR1;
1385                  case 2:
1386                    return MISCREG_ID_DFR0;
1387                  case 3:
1388                    return MISCREG_ID_AFR0;
1389                  case 4:
1390                    return MISCREG_ID_MMFR0;
1391                  case 5:
1392                    return MISCREG_ID_MMFR1;
1393                  case 6:
1394                    return MISCREG_ID_MMFR2;
1395                  case 7:
1396                    return MISCREG_ID_MMFR3;
1397                }
1398                break;
1399              case 2:
1400                switch (opc2) {
1401                  case 0:
1402                    return MISCREG_ID_ISAR0;
1403                  case 1:
1404                    return MISCREG_ID_ISAR1;
1405                  case 2:
1406                    return MISCREG_ID_ISAR2;
1407                  case 3:
1408                    return MISCREG_ID_ISAR3;
1409                  case 4:
1410                    return MISCREG_ID_ISAR4;
1411                  case 5:
1412                    return MISCREG_ID_ISAR5;
1413                  case 6:
1414                  case 7:
1415                    return MISCREG_RAZ; // read as zero
1416                }
1417                break;
1418              default:
1419                return MISCREG_RAZ; // read as zero
1420            }
1421            break;
1422          case 1:
1423            if (crm == 0) {
1424                switch (opc2) {
1425                  case 0:
1426                    return MISCREG_CCSIDR;
1427                  case 1:
1428                    return MISCREG_CLIDR;
1429                  case 7:
1430                    return MISCREG_AIDR;
1431                }
1432            }
1433            break;
1434          case 2:
1435            if (crm == 0 && opc2 == 0) {
1436                return MISCREG_CSSELR;
1437            }
1438            break;
1439          case 4:
1440            if (crm == 0) {
1441                if (opc2 == 0)
1442                    return MISCREG_VPIDR;
1443                else if (opc2 == 5)
1444                    return MISCREG_VMPIDR;
1445            }
1446            break;
1447        }
1448        break;
1449      case 1:
1450        if (opc1 == 0) {
1451            if (crm == 0) {
1452                switch (opc2) {
1453                  case 0:
1454                    return MISCREG_SCTLR;
1455                  case 1:
1456                    return MISCREG_ACTLR;
1457                  case 0x2:
1458                    return MISCREG_CPACR;
1459                }
1460            } else if (crm == 1) {
1461                switch (opc2) {
1462                  case 0:
1463                    return MISCREG_SCR;
1464                  case 1:
1465                    return MISCREG_SDER;
1466                  case 2:
1467                    return MISCREG_NSACR;
1468                }
1469            }
1470        } else if (opc1 == 4) {
1471            if (crm == 0) {
1472                if (opc2 == 0)
1473                    return MISCREG_HSCTLR;
1474                else if (opc2 == 1)
1475                    return MISCREG_HACTLR;
1476            } else if (crm == 1) {
1477                switch (opc2) {
1478                  case 0:
1479                    return MISCREG_HCR;
1480                  case 1:
1481                    return MISCREG_HDCR;
1482                  case 2:
1483                    return MISCREG_HCPTR;
1484                  case 3:
1485                    return MISCREG_HSTR;
1486                  case 7:
1487                    return MISCREG_HACR;
1488                }
1489            }
1490        }
1491        break;
1492      case 2:
1493        if (opc1 == 0 && crm == 0) {
1494            switch (opc2) {
1495              case 0:
1496                return MISCREG_TTBR0;
1497              case 1:
1498                return MISCREG_TTBR1;
1499              case 2:
1500                return MISCREG_TTBCR;
1501            }
1502        } else if (opc1 == 4) {
1503            if (crm == 0 && opc2 == 2)
1504                return MISCREG_HTCR;
1505            else if (crm == 1 && opc2 == 2)
1506                return MISCREG_VTCR;
1507        }
1508        break;
1509      case 3:
1510        if (opc1 == 0 && crm == 0 && opc2 == 0) {
1511            return MISCREG_DACR;
1512        }
1513        break;
1514      case 5:
1515        if (opc1 == 0) {
1516            if (crm == 0) {
1517                if (opc2 == 0) {
1518                    return MISCREG_DFSR;
1519                } else if (opc2 == 1) {
1520                    return MISCREG_IFSR;
1521                }
1522            } else if (crm == 1) {
1523                if (opc2 == 0) {
1524                    return MISCREG_ADFSR;
1525                } else if (opc2 == 1) {
1526                    return MISCREG_AIFSR;
1527                }
1528            }
1529        } else if (opc1 == 4) {
1530            if (crm == 1) {
1531                if (opc2 == 0)
1532                    return MISCREG_HADFSR;
1533                else if (opc2 == 1)
1534                    return MISCREG_HAIFSR;
1535            } else if (crm == 2 && opc2 == 0) {
1536                return MISCREG_HSR;
1537            }
1538        }
1539        break;
1540      case 6:
1541        if (opc1 == 0 && crm == 0) {
1542            switch (opc2) {
1543              case 0:
1544                return MISCREG_DFAR;
1545              case 2:
1546                return MISCREG_IFAR;
1547            }
1548        } else if (opc1 == 4 && crm == 0) {
1549            switch (opc2) {
1550              case 0:
1551                return MISCREG_HDFAR;
1552              case 2:
1553                return MISCREG_HIFAR;
1554              case 4:
1555                return MISCREG_HPFAR;
1556            }
1557        }
1558        break;
1559      case 7:
1560        if (opc1 == 0) {
1561            switch (crm) {
1562              case 0:
1563                if (opc2 == 4) {
1564                    return MISCREG_NOP;
1565                }
1566                break;
1567              case 1:
1568                switch (opc2) {
1569                  case 0:
1570                    return MISCREG_ICIALLUIS;
1571                  case 6:
1572                    return MISCREG_BPIALLIS;
1573                }
1574                break;
1575              case 4:
1576                if (opc2 == 0) {
1577                    return MISCREG_PAR;
1578                }
1579                break;
1580              case 5:
1581                switch (opc2) {
1582                  case 0:
1583                    return MISCREG_ICIALLU;
1584                  case 1:
1585                    return MISCREG_ICIMVAU;
1586                  case 4:
1587                    return MISCREG_CP15ISB;
1588                  case 6:
1589                    return MISCREG_BPIALL;
1590                  case 7:
1591                    return MISCREG_BPIMVA;
1592                }
1593                break;
1594              case 6:
1595                if (opc2 == 1) {
1596                    return MISCREG_DCIMVAC;
1597                } else if (opc2 == 2) {
1598                    return MISCREG_DCISW;
1599                }
1600                break;
1601              case 8:
1602                switch (opc2) {
1603                  case 0:
1604                    return MISCREG_ATS1CPR;
1605                  case 1:
1606                    return MISCREG_ATS1CPW;
1607                  case 2:
1608                    return MISCREG_ATS1CUR;
1609                  case 3:
1610                    return MISCREG_ATS1CUW;
1611                  case 4:
1612                    return MISCREG_ATS12NSOPR;
1613                  case 5:
1614                    return MISCREG_ATS12NSOPW;
1615                  case 6:
1616                    return MISCREG_ATS12NSOUR;
1617                  case 7:
1618                    return MISCREG_ATS12NSOUW;
1619                }
1620                break;
1621              case 10:
1622                switch (opc2) {
1623                  case 1:
1624                    return MISCREG_DCCMVAC;
1625                  case 2:
1626                    return MISCREG_DCCSW;
1627                  case 4:
1628                    return MISCREG_CP15DSB;
1629                  case 5:
1630                    return MISCREG_CP15DMB;
1631                }
1632                break;
1633              case 11:
1634                if (opc2 == 1) {
1635                    return MISCREG_DCCMVAU;
1636                }
1637                break;
1638              case 13:
1639                if (opc2 == 1) {
1640                    return MISCREG_NOP;
1641                }
1642                break;
1643              case 14:
1644                if (opc2 == 1) {
1645                    return MISCREG_DCCIMVAC;
1646                } else if (opc2 == 2) {
1647                    return MISCREG_DCCISW;
1648                }
1649                break;
1650            }
1651        } else if (opc1 == 4 && crm == 8) {
1652            if (opc2 == 0)
1653                return MISCREG_ATS1HR;
1654            else if (opc2 == 1)
1655                return MISCREG_ATS1HW;
1656        }
1657        break;
1658      case 8:
1659        if (opc1 == 0) {
1660            switch (crm) {
1661              case 3:
1662                switch (opc2) {
1663                  case 0:
1664                    return MISCREG_TLBIALLIS;
1665                  case 1:
1666                    return MISCREG_TLBIMVAIS;
1667                  case 2:
1668                    return MISCREG_TLBIASIDIS;
1669                  case 3:
1670                    return MISCREG_TLBIMVAAIS;
1671                }
1672                break;
1673              case 5:
1674                switch (opc2) {
1675                  case 0:
1676                    return MISCREG_ITLBIALL;
1677                  case 1:
1678                    return MISCREG_ITLBIMVA;
1679                  case 2:
1680                    return MISCREG_ITLBIASID;
1681                }
1682                break;
1683              case 6:
1684                switch (opc2) {
1685                  case 0:
1686                    return MISCREG_DTLBIALL;
1687                  case 1:
1688                    return MISCREG_DTLBIMVA;
1689                  case 2:
1690                    return MISCREG_DTLBIASID;
1691                }
1692                break;
1693              case 7:
1694                switch (opc2) {
1695                  case 0:
1696                    return MISCREG_TLBIALL;
1697                  case 1:
1698                    return MISCREG_TLBIMVA;
1699                  case 2:
1700                    return MISCREG_TLBIASID;
1701                  case 3:
1702                    return MISCREG_TLBIMVAA;
1703                }
1704                break;
1705            }
1706        } else if (opc1 == 4) {
1707            if (crm == 3) {
1708                switch (opc2) {
1709                  case 0:
1710                    return MISCREG_TLBIALLHIS;
1711                  case 1:
1712                    return MISCREG_TLBIMVAHIS;
1713                  case 4:
1714                    return MISCREG_TLBIALLNSNHIS;
1715                }
1716            } else if (crm == 7) {
1717                switch (opc2) {
1718                  case 0:
1719                    return MISCREG_TLBIALLH;
1720                  case 1:
1721                    return MISCREG_TLBIMVAH;
1722                  case 4:
1723                    return MISCREG_TLBIALLNSNH;
1724                }
1725            }
1726        }
1727        break;
1728      case 9:
1729        if (opc1 == 0) {
1730            switch (crm) {
1731              case 12:
1732                switch (opc2) {
1733                  case 0:
1734                    return MISCREG_PMCR;
1735                  case 1:
1736                    return MISCREG_PMCNTENSET;
1737                  case 2:
1738                    return MISCREG_PMCNTENCLR;
1739                  case 3:
1740                    return MISCREG_PMOVSR;
1741                  case 4:
1742                    return MISCREG_PMSWINC;
1743                  case 5:
1744                    return MISCREG_PMSELR;
1745                  case 6:
1746                    return MISCREG_PMCEID0;
1747                  case 7:
1748                    return MISCREG_PMCEID1;
1749                }
1750                break;
1751              case 13:
1752                switch (opc2) {
1753                  case 0:
1754                    return MISCREG_PMCCNTR;
1755                  case 1:
1756                    // Selector is PMSELR.SEL
1757                    return MISCREG_PMXEVTYPER_PMCCFILTR;
1758                  case 2:
1759                    return MISCREG_PMXEVCNTR;
1760                }
1761                break;
1762              case 14:
1763                switch (opc2) {
1764                  case 0:
1765                    return MISCREG_PMUSERENR;
1766                  case 1:
1767                    return MISCREG_PMINTENSET;
1768                  case 2:
1769                    return MISCREG_PMINTENCLR;
1770                  case 3:
1771                    return MISCREG_PMOVSSET;
1772                }
1773                break;
1774            }
1775        } else if (opc1 == 1) {
1776            switch (crm) {
1777              case 0:
1778                switch (opc2) {
1779                  case 2: // L2CTLR, L2 Control Register
1780                    return MISCREG_L2CTLR;
1781                  case 3:
1782                    return MISCREG_L2ECTLR;
1783                }
1784                break;
1785                break;
1786            }
1787        }
1788        break;
1789      case 10:
1790        if (opc1 == 0) {
1791            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
1792            if (crm == 2) { // TEX Remap Registers
1793                if (opc2 == 0) {
1794                    // Selector is TTBCR.EAE
1795                    return MISCREG_PRRR_MAIR0;
1796                } else if (opc2 == 1) {
1797                    // Selector is TTBCR.EAE
1798                    return MISCREG_NMRR_MAIR1;
1799                }
1800            } else if (crm == 3) {
1801                if (opc2 == 0) {
1802                    return MISCREG_AMAIR0;
1803                } else if (opc2 == 1) {
1804                    return MISCREG_AMAIR1;
1805                }
1806            }
1807        } else if (opc1 == 4) {
1808            // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
1809            if (crm == 2) {
1810                if (opc2 == 0)
1811                    return MISCREG_HMAIR0;
1812                else if (opc2 == 1)
1813                    return MISCREG_HMAIR1;
1814            } else if (crm == 3) {
1815                if (opc2 == 0)
1816                    return MISCREG_HAMAIR0;
1817                else if (opc2 == 1)
1818                    return MISCREG_HAMAIR1;
1819            }
1820        }
1821        break;
1822      case 11:
1823        if (opc1 <=7) {
1824            switch (crm) {
1825              case 0:
1826              case 1:
1827              case 2:
1828              case 3:
1829              case 4:
1830              case 5:
1831              case 6:
1832              case 7:
1833              case 8:
1834              case 15:
1835                // Reserved for DMA operations for TCM access
1836                break;
1837            }
1838        }
1839        break;
1840      case 12:
1841        if (opc1 == 0) {
1842            if (crm == 0) {
1843                if (opc2 == 0) {
1844                    return MISCREG_VBAR;
1845                } else if (opc2 == 1) {
1846                    return MISCREG_MVBAR;
1847                }
1848            } else if (crm == 1) {
1849                if (opc2 == 0) {
1850                    return MISCREG_ISR;
1851                }
1852            }
1853        } else if (opc1 == 4) {
1854            if (crm == 0 && opc2 == 0)
1855                return MISCREG_HVBAR;
1856        }
1857        break;
1858      case 13:
1859        if (opc1 == 0) {
1860            if (crm == 0) {
1861                switch (opc2) {
1862                  case 0:
1863                    return MISCREG_FCSEIDR;
1864                  case 1:
1865                    return MISCREG_CONTEXTIDR;
1866                  case 2:
1867                    return MISCREG_TPIDRURW;
1868                  case 3:
1869                    return MISCREG_TPIDRURO;
1870                  case 4:
1871                    return MISCREG_TPIDRPRW;
1872                }
1873            }
1874        } else if (opc1 == 4) {
1875            if (crm == 0 && opc2 == 2)
1876                return MISCREG_HTPIDR;
1877        }
1878        break;
1879      case 14:
1880        if (opc1 == 0) {
1881            switch (crm) {
1882              case 0:
1883                if (opc2 == 0)
1884                    return MISCREG_CNTFRQ;
1885                break;
1886              case 1:
1887                if (opc2 == 0)
1888                    return MISCREG_CNTKCTL;
1889                break;
1890              case 2:
1891                if (opc2 == 0)
1892                    return MISCREG_CNTP_TVAL;
1893                else if (opc2 == 1)
1894                    return MISCREG_CNTP_CTL;
1895                break;
1896              case 3:
1897                if (opc2 == 0)
1898                    return MISCREG_CNTV_TVAL;
1899                else if (opc2 == 1)
1900                    return MISCREG_CNTV_CTL;
1901                break;
1902            }
1903        } else if (opc1 == 4) {
1904            if (crm == 1 && opc2 == 0) {
1905                return MISCREG_CNTHCTL;
1906            } else if (crm == 2) {
1907                if (opc2 == 0)
1908                    return MISCREG_CNTHP_TVAL;
1909                else if (opc2 == 1)
1910                    return MISCREG_CNTHP_CTL;
1911            }
1912        }
1913        break;
1914      case 15:
1915        // Implementation defined
1916        return MISCREG_CP15_UNIMPL;
1917    }
1918    // Unrecognized register
1919    return MISCREG_CP15_UNIMPL;
1920}
1921
1922MiscRegIndex
1923decodeCP15Reg64(unsigned crm, unsigned opc1)
1924{
1925    switch (crm) {
1926      case 2:
1927        switch (opc1) {
1928          case 0:
1929            return MISCREG_TTBR0;
1930          case 1:
1931            return MISCREG_TTBR1;
1932          case 4:
1933            return MISCREG_HTTBR;
1934          case 6:
1935            return MISCREG_VTTBR;
1936        }
1937        break;
1938      case 7:
1939        if (opc1 == 0)
1940            return MISCREG_PAR;
1941        break;
1942      case 14:
1943        switch (opc1) {
1944          case 0:
1945            return MISCREG_CNTPCT;
1946          case 1:
1947            return MISCREG_CNTVCT;
1948          case 2:
1949            return MISCREG_CNTP_CVAL;
1950          case 3:
1951            return MISCREG_CNTV_CVAL;
1952          case 4:
1953            return MISCREG_CNTVOFF;
1954          case 6:
1955            return MISCREG_CNTHP_CVAL;
1956        }
1957        break;
1958      case 15:
1959        if (opc1 == 0)
1960            return MISCREG_CPUMERRSR;
1961        else if (opc1 == 1)
1962            return MISCREG_L2MERRSR;
1963        break;
1964    }
1965    // Unrecognized register
1966    return MISCREG_CP15_UNIMPL;
1967}
1968
1969bool
1970canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1971{
1972    bool secure = !scr.ns;
1973    bool canRead;
1974
1975    switch (cpsr.mode) {
1976      case MODE_USER:
1977        canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1978                           miscRegInfo[reg][MISCREG_USR_NS_RD];
1979        break;
1980      case MODE_FIQ:
1981      case MODE_IRQ:
1982      case MODE_SVC:
1983      case MODE_ABORT:
1984      case MODE_UNDEFINED:
1985      case MODE_SYSTEM:
1986        canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1987                           miscRegInfo[reg][MISCREG_PRI_NS_RD];
1988        break;
1989      case MODE_MON:
1990        canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1991                           miscRegInfo[reg][MISCREG_MON_NS1_RD];
1992        break;
1993      case MODE_HYP:
1994        canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1995        break;
1996      default:
1997        panic("Unrecognized mode setting in CPSR.\n");
1998    }
1999    // can't do permissions checkes on the root of a banked pair of regs
2000    assert(!miscRegInfo[reg][MISCREG_BANKED]);
2001    return canRead;
2002}
2003
2004bool
2005canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
2006{
2007    bool secure = !scr.ns;
2008    bool canWrite;
2009
2010    switch (cpsr.mode) {
2011      case MODE_USER:
2012        canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
2013                            miscRegInfo[reg][MISCREG_USR_NS_WR];
2014        break;
2015      case MODE_FIQ:
2016      case MODE_IRQ:
2017      case MODE_SVC:
2018      case MODE_ABORT:
2019      case MODE_UNDEFINED:
2020      case MODE_SYSTEM:
2021        canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
2022                            miscRegInfo[reg][MISCREG_PRI_NS_WR];
2023        break;
2024      case MODE_MON:
2025        canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
2026                            miscRegInfo[reg][MISCREG_MON_NS1_WR];
2027        break;
2028      case MODE_HYP:
2029        canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
2030        break;
2031      default:
2032        panic("Unrecognized mode setting in CPSR.\n");
2033    }
2034    // can't do permissions checkes on the root of a banked pair of regs
2035    assert(!miscRegInfo[reg][MISCREG_BANKED]);
2036    return canWrite;
2037}
2038
2039int
2040flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
2041{
2042    int reg_as_int = static_cast<int>(reg);
2043    if (miscRegInfo[reg][MISCREG_BANKED]) {
2044        SCR scr = tc->readMiscReg(MISCREG_SCR);
2045        reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1;
2046    }
2047    return reg_as_int;
2048}
2049
2050int
2051flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
2052{
2053    int reg_as_int = static_cast<int>(reg);
2054    if (miscRegInfo[reg][MISCREG_BANKED]) {
2055        reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1;
2056    }
2057    return reg_as_int;
2058}
2059
2060
2061/**
2062 * If the reg is a child reg of a banked set, then the parent is the last
2063 * banked one in the list. This is messy, and the wish is to eventually have
2064 * the bitmap replaced with a better data structure. the preUnflatten function
2065 * initializes a lookup table to speed up the search for these banked
2066 * registers.
2067 */
2068
2069int unflattenResultMiscReg[NUM_MISCREGS];
2070
2071void
2072preUnflattenMiscReg()
2073{
2074    int reg = -1;
2075    for (int i = 0 ; i < NUM_MISCREGS; i++){
2076        if (miscRegInfo[i][MISCREG_BANKED])
2077            reg = i;
2078        if (miscRegInfo[i][MISCREG_BANKED_CHILD])
2079            unflattenResultMiscReg[i] = reg;
2080        else
2081            unflattenResultMiscReg[i] = i;
2082        // if this assert fails, no parent was found, and something is broken
2083        assert(unflattenResultMiscReg[i] > -1);
2084    }
2085}
2086
2087int
2088unflattenMiscReg(int reg)
2089{
2090    return unflattenResultMiscReg[reg];
2091}
2092
2093bool
2094canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
2095{
2096    // Check for SP_EL0 access while SPSEL == 0
2097    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
2098        return false;
2099
2100    // Check for RVBAR access
2101    if (reg == MISCREG_RVBAR_EL1) {
2102        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
2103        if (highest_el == EL2 || highest_el == EL3)
2104            return false;
2105    }
2106    if (reg == MISCREG_RVBAR_EL2) {
2107        ExceptionLevel highest_el = ArmSystem::highestEL(tc);
2108        if (highest_el == EL3)
2109            return false;
2110    }
2111
2112    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
2113
2114    switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
2115      case EL0:
2116        return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
2117            miscRegInfo[reg][MISCREG_USR_NS_RD];
2118      case EL1:
2119        return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
2120            miscRegInfo[reg][MISCREG_PRI_NS_RD];
2121      case EL2:
2122        return miscRegInfo[reg][MISCREG_HYP_RD];
2123      case EL3:
2124        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
2125            miscRegInfo[reg][MISCREG_MON_NS1_RD];
2126      default:
2127        panic("Invalid exception level");
2128    }
2129}
2130
2131bool
2132canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
2133{
2134    // Check for SP_EL0 access while SPSEL == 0
2135    if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
2136        return false;
2137    ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
2138    if (reg == MISCREG_DAIF) {
2139        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2140        if (el == EL0 && !sctlr.uma)
2141            return false;
2142    }
2143    if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
2144        // In syscall-emulation mode, this test is skipped and DCZVA is always
2145        // allowed at EL0
2146        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2147        if (el == EL0 && !sctlr.dze)
2148            return false;
2149    }
2150    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
2151        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2152        if (el == EL0 && !sctlr.uci)
2153            return false;
2154    }
2155
2156    bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
2157
2158    switch (el) {
2159      case EL0:
2160        return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
2161            miscRegInfo[reg][MISCREG_USR_NS_WR];
2162      case EL1:
2163        return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
2164            miscRegInfo[reg][MISCREG_PRI_NS_WR];
2165      case EL2:
2166        return miscRegInfo[reg][MISCREG_HYP_WR];
2167      case EL3:
2168        return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
2169            miscRegInfo[reg][MISCREG_MON_NS1_WR];
2170      default:
2171        panic("Invalid exception level");
2172    }
2173}
2174
2175MiscRegIndex
2176decodeAArch64SysReg(unsigned op0, unsigned op1,
2177                    unsigned crn, unsigned crm,
2178                    unsigned op2)
2179{
2180    switch (op0) {
2181      case 1:
2182        switch (crn) {
2183          case 7:
2184            switch (op1) {
2185              case 0:
2186                switch (crm) {
2187                  case 1:
2188                    switch (op2) {
2189                      case 0:
2190                        return MISCREG_IC_IALLUIS;
2191                    }
2192                    break;
2193                  case 5:
2194                    switch (op2) {
2195                      case 0:
2196                        return MISCREG_IC_IALLU;
2197                    }
2198                    break;
2199                  case 6:
2200                    switch (op2) {
2201                      case 1:
2202                        return MISCREG_DC_IVAC_Xt;
2203                      case 2:
2204                        return MISCREG_DC_ISW_Xt;
2205                    }
2206                    break;
2207                  case 8:
2208                    switch (op2) {
2209                      case 0:
2210                        return MISCREG_AT_S1E1R_Xt;
2211                      case 1:
2212                        return MISCREG_AT_S1E1W_Xt;
2213                      case 2:
2214                        return MISCREG_AT_S1E0R_Xt;
2215                      case 3:
2216                        return MISCREG_AT_S1E0W_Xt;
2217                    }
2218                    break;
2219                  case 10:
2220                    switch (op2) {
2221                      case 2:
2222                        return MISCREG_DC_CSW_Xt;
2223                    }
2224                    break;
2225                  case 14:
2226                    switch (op2) {
2227                      case 2:
2228                        return MISCREG_DC_CISW_Xt;
2229                    }
2230                    break;
2231                }
2232                break;
2233              case 3:
2234                switch (crm) {
2235                  case 4:
2236                    switch (op2) {
2237                      case 1:
2238                        return MISCREG_DC_ZVA_Xt;
2239                    }
2240                    break;
2241                  case 5:
2242                    switch (op2) {
2243                      case 1:
2244                        return MISCREG_IC_IVAU_Xt;
2245                    }
2246                    break;
2247                  case 10:
2248                    switch (op2) {
2249                      case 1:
2250                        return MISCREG_DC_CVAC_Xt;
2251                    }
2252                    break;
2253                  case 11:
2254                    switch (op2) {
2255                      case 1:
2256                        return MISCREG_DC_CVAU_Xt;
2257                    }
2258                    break;
2259                  case 14:
2260                    switch (op2) {
2261                      case 1:
2262                        return MISCREG_DC_CIVAC_Xt;
2263                    }
2264                    break;
2265                }
2266                break;
2267              case 4:
2268                switch (crm) {
2269                  case 8:
2270                    switch (op2) {
2271                      case 0:
2272                        return MISCREG_AT_S1E2R_Xt;
2273                      case 1:
2274                        return MISCREG_AT_S1E2W_Xt;
2275                      case 4:
2276                        return MISCREG_AT_S12E1R_Xt;
2277                      case 5:
2278                        return MISCREG_AT_S12E1W_Xt;
2279                      case 6:
2280                        return MISCREG_AT_S12E0R_Xt;
2281                      case 7:
2282                        return MISCREG_AT_S12E0W_Xt;
2283                    }
2284                    break;
2285                }
2286                break;
2287              case 6:
2288                switch (crm) {
2289                  case 8:
2290                    switch (op2) {
2291                      case 0:
2292                        return MISCREG_AT_S1E3R_Xt;
2293                      case 1:
2294                        return MISCREG_AT_S1E3W_Xt;
2295                    }
2296                    break;
2297                }
2298                break;
2299            }
2300            break;
2301          case 8:
2302            switch (op1) {
2303              case 0:
2304                switch (crm) {
2305                  case 3:
2306                    switch (op2) {
2307                      case 0:
2308                        return MISCREG_TLBI_VMALLE1IS;
2309                      case 1:
2310                        return MISCREG_TLBI_VAE1IS_Xt;
2311                      case 2:
2312                        return MISCREG_TLBI_ASIDE1IS_Xt;
2313                      case 3:
2314                        return MISCREG_TLBI_VAAE1IS_Xt;
2315                      case 5:
2316                        return MISCREG_TLBI_VALE1IS_Xt;
2317                      case 7:
2318                        return MISCREG_TLBI_VAALE1IS_Xt;
2319                    }
2320                    break;
2321                  case 7:
2322                    switch (op2) {
2323                      case 0:
2324                        return MISCREG_TLBI_VMALLE1;
2325                      case 1:
2326                        return MISCREG_TLBI_VAE1_Xt;
2327                      case 2:
2328                        return MISCREG_TLBI_ASIDE1_Xt;
2329                      case 3:
2330                        return MISCREG_TLBI_VAAE1_Xt;
2331                      case 5:
2332                        return MISCREG_TLBI_VALE1_Xt;
2333                      case 7:
2334                        return MISCREG_TLBI_VAALE1_Xt;
2335                    }
2336                    break;
2337                }
2338                break;
2339              case 4:
2340                switch (crm) {
2341                  case 0:
2342                    switch (op2) {
2343                      case 1:
2344                        return MISCREG_TLBI_IPAS2E1IS_Xt;
2345                      case 5:
2346                        return MISCREG_TLBI_IPAS2LE1IS_Xt;
2347                    }
2348                    break;
2349                  case 3:
2350                    switch (op2) {
2351                      case 0:
2352                        return MISCREG_TLBI_ALLE2IS;
2353                      case 1:
2354                        return MISCREG_TLBI_VAE2IS_Xt;
2355                      case 4:
2356                        return MISCREG_TLBI_ALLE1IS;
2357                      case 5:
2358                        return MISCREG_TLBI_VALE2IS_Xt;
2359                      case 6:
2360                        return MISCREG_TLBI_VMALLS12E1IS;
2361                    }
2362                    break;
2363                  case 4:
2364                    switch (op2) {
2365                      case 1:
2366                        return MISCREG_TLBI_IPAS2E1_Xt;
2367                      case 5:
2368                        return MISCREG_TLBI_IPAS2LE1_Xt;
2369                    }
2370                    break;
2371                  case 7:
2372                    switch (op2) {
2373                      case 0:
2374                        return MISCREG_TLBI_ALLE2;
2375                      case 1:
2376                        return MISCREG_TLBI_VAE2_Xt;
2377                      case 4:
2378                        return MISCREG_TLBI_ALLE1;
2379                      case 5:
2380                        return MISCREG_TLBI_VALE2_Xt;
2381                      case 6:
2382                        return MISCREG_TLBI_VMALLS12E1;
2383                    }
2384                    break;
2385                }
2386                break;
2387              case 6:
2388                switch (crm) {
2389                  case 3:
2390                    switch (op2) {
2391                      case 0:
2392                        return MISCREG_TLBI_ALLE3IS;
2393                      case 1:
2394                        return MISCREG_TLBI_VAE3IS_Xt;
2395                      case 5:
2396                        return MISCREG_TLBI_VALE3IS_Xt;
2397                    }
2398                    break;
2399                  case 7:
2400                    switch (op2) {
2401                      case 0:
2402                        return MISCREG_TLBI_ALLE3;
2403                      case 1:
2404                        return MISCREG_TLBI_VAE3_Xt;
2405                      case 5:
2406                        return MISCREG_TLBI_VALE3_Xt;
2407                    }
2408                    break;
2409                }
2410                break;
2411            }
2412            break;
2413        }
2414        break;
2415      case 2:
2416        switch (crn) {
2417          case 0:
2418            switch (op1) {
2419              case 0:
2420                switch (crm) {
2421                  case 0:
2422                    switch (op2) {
2423                      case 2:
2424                        return MISCREG_OSDTRRX_EL1;
2425                      case 4:
2426                        return MISCREG_DBGBVR0_EL1;
2427                      case 5:
2428                        return MISCREG_DBGBCR0_EL1;
2429                      case 6:
2430                        return MISCREG_DBGWVR0_EL1;
2431                      case 7:
2432                        return MISCREG_DBGWCR0_EL1;
2433                    }
2434                    break;
2435                  case 1:
2436                    switch (op2) {
2437                      case 4:
2438                        return MISCREG_DBGBVR1_EL1;
2439                      case 5:
2440                        return MISCREG_DBGBCR1_EL1;
2441                      case 6:
2442                        return MISCREG_DBGWVR1_EL1;
2443                      case 7:
2444                        return MISCREG_DBGWCR1_EL1;
2445                    }
2446                    break;
2447                  case 2:
2448                    switch (op2) {
2449                      case 0:
2450                        return MISCREG_MDCCINT_EL1;
2451                      case 2:
2452                        return MISCREG_MDSCR_EL1;
2453                      case 4:
2454                        return MISCREG_DBGBVR2_EL1;
2455                      case 5:
2456                        return MISCREG_DBGBCR2_EL1;
2457                      case 6:
2458                        return MISCREG_DBGWVR2_EL1;
2459                      case 7:
2460                        return MISCREG_DBGWCR2_EL1;
2461                    }
2462                    break;
2463                  case 3:
2464                    switch (op2) {
2465                      case 2:
2466                        return MISCREG_OSDTRTX_EL1;
2467                      case 4:
2468                        return MISCREG_DBGBVR3_EL1;
2469                      case 5:
2470                        return MISCREG_DBGBCR3_EL1;
2471                      case 6:
2472                        return MISCREG_DBGWVR3_EL1;
2473                      case 7:
2474                        return MISCREG_DBGWCR3_EL1;
2475                    }
2476                    break;
2477                  case 4:
2478                    switch (op2) {
2479                      case 4:
2480                        return MISCREG_DBGBVR4_EL1;
2481                      case 5:
2482                        return MISCREG_DBGBCR4_EL1;
2483                    }
2484                    break;
2485                  case 5:
2486                    switch (op2) {
2487                      case 4:
2488                        return MISCREG_DBGBVR5_EL1;
2489                      case 5:
2490                        return MISCREG_DBGBCR5_EL1;
2491                    }
2492                    break;
2493                  case 6:
2494                    switch (op2) {
2495                      case 2:
2496                        return MISCREG_OSECCR_EL1;
2497                    }
2498                    break;
2499                }
2500                break;
2501              case 2:
2502                switch (crm) {
2503                  case 0:
2504                    switch (op2) {
2505                      case 0:
2506                        return MISCREG_TEECR32_EL1;
2507                    }
2508                    break;
2509                }
2510                break;
2511              case 3:
2512                switch (crm) {
2513                  case 1:
2514                    switch (op2) {
2515                      case 0:
2516                        return MISCREG_MDCCSR_EL0;
2517                    }
2518                    break;
2519                  case 4:
2520                    switch (op2) {
2521                      case 0:
2522                        return MISCREG_MDDTR_EL0;
2523                    }
2524                    break;
2525                  case 5:
2526                    switch (op2) {
2527                      case 0:
2528                        return MISCREG_MDDTRRX_EL0;
2529                    }
2530                    break;
2531                }
2532                break;
2533              case 4:
2534                switch (crm) {
2535                  case 7:
2536                    switch (op2) {
2537                      case 0:
2538                        return MISCREG_DBGVCR32_EL2;
2539                    }
2540                    break;
2541                }
2542                break;
2543            }
2544            break;
2545          case 1:
2546            switch (op1) {
2547              case 0:
2548                switch (crm) {
2549                  case 0:
2550                    switch (op2) {
2551                      case 0:
2552                        return MISCREG_MDRAR_EL1;
2553                      case 4:
2554                        return MISCREG_OSLAR_EL1;
2555                    }
2556                    break;
2557                  case 1:
2558                    switch (op2) {
2559                      case 4:
2560                        return MISCREG_OSLSR_EL1;
2561                    }
2562                    break;
2563                  case 3:
2564                    switch (op2) {
2565                      case 4:
2566                        return MISCREG_OSDLR_EL1;
2567                    }
2568                    break;
2569                  case 4:
2570                    switch (op2) {
2571                      case 4:
2572                        return MISCREG_DBGPRCR_EL1;
2573                    }
2574                    break;
2575                }
2576                break;
2577              case 2:
2578                switch (crm) {
2579                  case 0:
2580                    switch (op2) {
2581                      case 0:
2582                        return MISCREG_TEEHBR32_EL1;
2583                    }
2584                    break;
2585                }
2586                break;
2587            }
2588            break;
2589          case 7:
2590            switch (op1) {
2591              case 0:
2592                switch (crm) {
2593                  case 8:
2594                    switch (op2) {
2595                      case 6:
2596                        return MISCREG_DBGCLAIMSET_EL1;
2597                    }
2598                    break;
2599                  case 9:
2600                    switch (op2) {
2601                      case 6:
2602                        return MISCREG_DBGCLAIMCLR_EL1;
2603                    }
2604                    break;
2605                  case 14:
2606                    switch (op2) {
2607                      case 6:
2608                        return MISCREG_DBGAUTHSTATUS_EL1;
2609                    }
2610                    break;
2611                }
2612                break;
2613            }
2614            break;
2615        }
2616        break;
2617      case 3:
2618        switch (crn) {
2619          case 0:
2620            switch (op1) {
2621              case 0:
2622                switch (crm) {
2623                  case 0:
2624                    switch (op2) {
2625                      case 0:
2626                        return MISCREG_MIDR_EL1;
2627                      case 5:
2628                        return MISCREG_MPIDR_EL1;
2629                      case 6:
2630                        return MISCREG_REVIDR_EL1;
2631                    }
2632                    break;
2633                  case 1:
2634                    switch (op2) {
2635                      case 0:
2636                        return MISCREG_ID_PFR0_EL1;
2637                      case 1:
2638                        return MISCREG_ID_PFR1_EL1;
2639                      case 2:
2640                        return MISCREG_ID_DFR0_EL1;
2641                      case 3:
2642                        return MISCREG_ID_AFR0_EL1;
2643                      case 4:
2644                        return MISCREG_ID_MMFR0_EL1;
2645                      case 5:
2646                        return MISCREG_ID_MMFR1_EL1;
2647                      case 6:
2648                        return MISCREG_ID_MMFR2_EL1;
2649                      case 7:
2650                        return MISCREG_ID_MMFR3_EL1;
2651                    }
2652                    break;
2653                  case 2:
2654                    switch (op2) {
2655                      case 0:
2656                        return MISCREG_ID_ISAR0_EL1;
2657                      case 1:
2658                        return MISCREG_ID_ISAR1_EL1;
2659                      case 2:
2660                        return MISCREG_ID_ISAR2_EL1;
2661                      case 3:
2662                        return MISCREG_ID_ISAR3_EL1;
2663                      case 4:
2664                        return MISCREG_ID_ISAR4_EL1;
2665                      case 5:
2666                        return MISCREG_ID_ISAR5_EL1;
2667                    }
2668                    break;
2669                  case 3:
2670                    switch (op2) {
2671                      case 0:
2672                        return MISCREG_MVFR0_EL1;
2673                      case 1:
2674                        return MISCREG_MVFR1_EL1;
2675                      case 2:
2676                        return MISCREG_MVFR2_EL1;
2677                      case 3 ... 7:
2678                        return MISCREG_RAZ;
2679                    }
2680                    break;
2681                  case 4:
2682                    switch (op2) {
2683                      case 0:
2684                        return MISCREG_ID_AA64PFR0_EL1;
2685                      case 1:
2686                        return MISCREG_ID_AA64PFR1_EL1;
2687                      case 2 ... 7:
2688                        return MISCREG_RAZ;
2689                    }
2690                    break;
2691                  case 5:
2692                    switch (op2) {
2693                      case 0:
2694                        return MISCREG_ID_AA64DFR0_EL1;
2695                      case 1:
2696                        return MISCREG_ID_AA64DFR1_EL1;
2697                      case 4:
2698                        return MISCREG_ID_AA64AFR0_EL1;
2699                      case 5:
2700                        return MISCREG_ID_AA64AFR1_EL1;
2701                      case 2:
2702                      case 3:
2703                      case 6:
2704                      case 7:
2705                        return MISCREG_RAZ;
2706                    }
2707                    break;
2708                  case 6:
2709                    switch (op2) {
2710                      case 0:
2711                        return MISCREG_ID_AA64ISAR0_EL1;
2712                      case 1:
2713                        return MISCREG_ID_AA64ISAR1_EL1;
2714                      case 2 ... 7:
2715                        return MISCREG_RAZ;
2716                    }
2717                    break;
2718                  case 7:
2719                    switch (op2) {
2720                      case 0:
2721                        return MISCREG_ID_AA64MMFR0_EL1;
2722                      case 1:
2723                        return MISCREG_ID_AA64MMFR1_EL1;
2724                      case 2 ... 7:
2725                        return MISCREG_RAZ;
2726                    }
2727                    break;
2728                }
2729                break;
2730              case 1:
2731                switch (crm) {
2732                  case 0:
2733                    switch (op2) {
2734                      case 0:
2735                        return MISCREG_CCSIDR_EL1;
2736                      case 1:
2737                        return MISCREG_CLIDR_EL1;
2738                      case 7:
2739                        return MISCREG_AIDR_EL1;
2740                    }
2741                    break;
2742                }
2743                break;
2744              case 2:
2745                switch (crm) {
2746                  case 0:
2747                    switch (op2) {
2748                      case 0:
2749                        return MISCREG_CSSELR_EL1;
2750                    }
2751                    break;
2752                }
2753                break;
2754              case 3:
2755                switch (crm) {
2756                  case 0:
2757                    switch (op2) {
2758                      case 1:
2759                        return MISCREG_CTR_EL0;
2760                      case 7:
2761                        return MISCREG_DCZID_EL0;
2762                    }
2763                    break;
2764                }
2765                break;
2766              case 4:
2767                switch (crm) {
2768                  case 0:
2769                    switch (op2) {
2770                      case 0:
2771                        return MISCREG_VPIDR_EL2;
2772                      case 5:
2773                        return MISCREG_VMPIDR_EL2;
2774                    }
2775                    break;
2776                }
2777                break;
2778            }
2779            break;
2780          case 1:
2781            switch (op1) {
2782              case 0:
2783                switch (crm) {
2784                  case 0:
2785                    switch (op2) {
2786                      case 0:
2787                        return MISCREG_SCTLR_EL1;
2788                      case 1:
2789                        return MISCREG_ACTLR_EL1;
2790                      case 2:
2791                        return MISCREG_CPACR_EL1;
2792                    }
2793                    break;
2794                }
2795                break;
2796              case 4:
2797                switch (crm) {
2798                  case 0:
2799                    switch (op2) {
2800                      case 0:
2801                        return MISCREG_SCTLR_EL2;
2802                      case 1:
2803                        return MISCREG_ACTLR_EL2;
2804                    }
2805                    break;
2806                  case 1:
2807                    switch (op2) {
2808                      case 0:
2809                        return MISCREG_HCR_EL2;
2810                      case 1:
2811                        return MISCREG_MDCR_EL2;
2812                      case 2:
2813                        return MISCREG_CPTR_EL2;
2814                      case 3:
2815                        return MISCREG_HSTR_EL2;
2816                      case 7:
2817                        return MISCREG_HACR_EL2;
2818                    }
2819                    break;
2820                }
2821                break;
2822              case 6:
2823                switch (crm) {
2824                  case 0:
2825                    switch (op2) {
2826                      case 0:
2827                        return MISCREG_SCTLR_EL3;
2828                      case 1:
2829                        return MISCREG_ACTLR_EL3;
2830                    }
2831                    break;
2832                  case 1:
2833                    switch (op2) {
2834                      case 0:
2835                        return MISCREG_SCR_EL3;
2836                      case 1:
2837                        return MISCREG_SDER32_EL3;
2838                      case 2:
2839                        return MISCREG_CPTR_EL3;
2840                    }
2841                    break;
2842                  case 3:
2843                    switch (op2) {
2844                      case 1:
2845                        return MISCREG_MDCR_EL3;
2846                    }
2847                    break;
2848                }
2849                break;
2850            }
2851            break;
2852          case 2:
2853            switch (op1) {
2854              case 0:
2855                switch (crm) {
2856                  case 0:
2857                    switch (op2) {
2858                      case 0:
2859                        return MISCREG_TTBR0_EL1;
2860                      case 1:
2861                        return MISCREG_TTBR1_EL1;
2862                      case 2:
2863                        return MISCREG_TCR_EL1;
2864                    }
2865                    break;
2866                }
2867                break;
2868              case 4:
2869                switch (crm) {
2870                  case 0:
2871                    switch (op2) {
2872                      case 0:
2873                        return MISCREG_TTBR0_EL2;
2874                      case 2:
2875                        return MISCREG_TCR_EL2;
2876                    }
2877                    break;
2878                  case 1:
2879                    switch (op2) {
2880                      case 0:
2881                        return MISCREG_VTTBR_EL2;
2882                      case 2:
2883                        return MISCREG_VTCR_EL2;
2884                    }
2885                    break;
2886                }
2887                break;
2888              case 6:
2889                switch (crm) {
2890                  case 0:
2891                    switch (op2) {
2892                      case 0:
2893                        return MISCREG_TTBR0_EL3;
2894                      case 2:
2895                        return MISCREG_TCR_EL3;
2896                    }
2897                    break;
2898                }
2899                break;
2900            }
2901            break;
2902          case 3:
2903            switch (op1) {
2904              case 4:
2905                switch (crm) {
2906                  case 0:
2907                    switch (op2) {
2908                      case 0:
2909                        return MISCREG_DACR32_EL2;
2910                    }
2911                    break;
2912                }
2913                break;
2914            }
2915            break;
2916          case 4:
2917            switch (op1) {
2918              case 0:
2919                switch (crm) {
2920                  case 0:
2921                    switch (op2) {
2922                      case 0:
2923                        return MISCREG_SPSR_EL1;
2924                      case 1:
2925                        return MISCREG_ELR_EL1;
2926                    }
2927                    break;
2928                  case 1:
2929                    switch (op2) {
2930                      case 0:
2931                        return MISCREG_SP_EL0;
2932                    }
2933                    break;
2934                  case 2:
2935                    switch (op2) {
2936                      case 0:
2937                        return MISCREG_SPSEL;
2938                      case 2:
2939                        return MISCREG_CURRENTEL;
2940                    }
2941                    break;
2942                }
2943                break;
2944              case 3:
2945                switch (crm) {
2946                  case 2:
2947                    switch (op2) {
2948                      case 0:
2949                        return MISCREG_NZCV;
2950                      case 1:
2951                        return MISCREG_DAIF;
2952                    }
2953                    break;
2954                  case 4:
2955                    switch (op2) {
2956                      case 0:
2957                        return MISCREG_FPCR;
2958                      case 1:
2959                        return MISCREG_FPSR;
2960                    }
2961                    break;
2962                  case 5:
2963                    switch (op2) {
2964                      case 0:
2965                        return MISCREG_DSPSR_EL0;
2966                      case 1:
2967                        return MISCREG_DLR_EL0;
2968                    }
2969                    break;
2970                }
2971                break;
2972              case 4:
2973                switch (crm) {
2974                  case 0:
2975                    switch (op2) {
2976                      case 0:
2977                        return MISCREG_SPSR_EL2;
2978                      case 1:
2979                        return MISCREG_ELR_EL2;
2980                    }
2981                    break;
2982                  case 1:
2983                    switch (op2) {
2984                      case 0:
2985                        return MISCREG_SP_EL1;
2986                    }
2987                    break;
2988                  case 3:
2989                    switch (op2) {
2990                      case 0:
2991                        return MISCREG_SPSR_IRQ_AA64;
2992                      case 1:
2993                        return MISCREG_SPSR_ABT_AA64;
2994                      case 2:
2995                        return MISCREG_SPSR_UND_AA64;
2996                      case 3:
2997                        return MISCREG_SPSR_FIQ_AA64;
2998                    }
2999                    break;
3000                }
3001                break;
3002              case 6:
3003                switch (crm) {
3004                  case 0:
3005                    switch (op2) {
3006                      case 0:
3007                        return MISCREG_SPSR_EL3;
3008                      case 1:
3009                        return MISCREG_ELR_EL3;
3010                    }
3011                    break;
3012                  case 1:
3013                    switch (op2) {
3014                      case 0:
3015                        return MISCREG_SP_EL2;
3016                    }
3017                    break;
3018                }
3019                break;
3020            }
3021            break;
3022          case 5:
3023            switch (op1) {
3024              case 0:
3025                switch (crm) {
3026                  case 1:
3027                    switch (op2) {
3028                      case 0:
3029                        return MISCREG_AFSR0_EL1;
3030                      case 1:
3031                        return MISCREG_AFSR1_EL1;
3032                    }
3033                    break;
3034                  case 2:
3035                    switch (op2) {
3036                      case 0:
3037                        return MISCREG_ESR_EL1;
3038                    }
3039                    break;
3040                }
3041                break;
3042              case 4:
3043                switch (crm) {
3044                  case 0:
3045                    switch (op2) {
3046                      case 1:
3047                        return MISCREG_IFSR32_EL2;
3048                    }
3049                    break;
3050                  case 1:
3051                    switch (op2) {
3052                      case 0:
3053                        return MISCREG_AFSR0_EL2;
3054                      case 1:
3055                        return MISCREG_AFSR1_EL2;
3056                    }
3057                    break;
3058                  case 2:
3059                    switch (op2) {
3060                      case 0:
3061                        return MISCREG_ESR_EL2;
3062                    }
3063                    break;
3064                  case 3:
3065                    switch (op2) {
3066                      case 0:
3067                        return MISCREG_FPEXC32_EL2;
3068                    }
3069                    break;
3070                }
3071                break;
3072              case 6:
3073                switch (crm) {
3074                  case 1:
3075                    switch (op2) {
3076                      case 0:
3077                        return MISCREG_AFSR0_EL3;
3078                      case 1:
3079                        return MISCREG_AFSR1_EL3;
3080                    }
3081                    break;
3082                  case 2:
3083                    switch (op2) {
3084                      case 0:
3085                        return MISCREG_ESR_EL3;
3086                    }
3087                    break;
3088                }
3089                break;
3090            }
3091            break;
3092          case 6:
3093            switch (op1) {
3094              case 0:
3095                switch (crm) {
3096                  case 0:
3097                    switch (op2) {
3098                      case 0:
3099                        return MISCREG_FAR_EL1;
3100                    }
3101                    break;
3102                }
3103                break;
3104              case 4:
3105                switch (crm) {
3106                  case 0:
3107                    switch (op2) {
3108                      case 0:
3109                        return MISCREG_FAR_EL2;
3110                      case 4:
3111                        return MISCREG_HPFAR_EL2;
3112                    }
3113                    break;
3114                }
3115                break;
3116              case 6:
3117                switch (crm) {
3118                  case 0:
3119                    switch (op2) {
3120                      case 0:
3121                        return MISCREG_FAR_EL3;
3122                    }
3123                    break;
3124                }
3125                break;
3126            }
3127            break;
3128          case 7:
3129            switch (op1) {
3130              case 0:
3131                switch (crm) {
3132                  case 4:
3133                    switch (op2) {
3134                      case 0:
3135                        return MISCREG_PAR_EL1;
3136                    }
3137                    break;
3138                }
3139                break;
3140            }
3141            break;
3142          case 9:
3143            switch (op1) {
3144              case 0:
3145                switch (crm) {
3146                  case 14:
3147                    switch (op2) {
3148                      case 1:
3149                        return MISCREG_PMINTENSET_EL1;
3150                      case 2:
3151                        return MISCREG_PMINTENCLR_EL1;
3152                    }
3153                    break;
3154                }
3155                break;
3156              case 3:
3157                switch (crm) {
3158                  case 12:
3159                    switch (op2) {
3160                      case 0:
3161                        return MISCREG_PMCR_EL0;
3162                      case 1:
3163                        return MISCREG_PMCNTENSET_EL0;
3164                      case 2:
3165                        return MISCREG_PMCNTENCLR_EL0;
3166                      case 3:
3167                        return MISCREG_PMOVSCLR_EL0;
3168                      case 4:
3169                        return MISCREG_PMSWINC_EL0;
3170                      case 5:
3171                        return MISCREG_PMSELR_EL0;
3172                      case 6:
3173                        return MISCREG_PMCEID0_EL0;
3174                      case 7:
3175                        return MISCREG_PMCEID1_EL0;
3176                    }
3177                    break;
3178                  case 13:
3179                    switch (op2) {
3180                      case 0:
3181                        return MISCREG_PMCCNTR_EL0;
3182                      case 1:
3183                        return MISCREG_PMXEVTYPER_EL0;
3184                      case 2:
3185                        return MISCREG_PMXEVCNTR_EL0;
3186                    }
3187                    break;
3188                  case 14:
3189                    switch (op2) {
3190                      case 0:
3191                        return MISCREG_PMUSERENR_EL0;
3192                      case 3:
3193                        return MISCREG_PMOVSSET_EL0;
3194                    }
3195                    break;
3196                }
3197                break;
3198            }
3199            break;
3200          case 10:
3201            switch (op1) {
3202              case 0:
3203                switch (crm) {
3204                  case 2:
3205                    switch (op2) {
3206                      case 0:
3207                        return MISCREG_MAIR_EL1;
3208                    }
3209                    break;
3210                  case 3:
3211                    switch (op2) {
3212                      case 0:
3213                        return MISCREG_AMAIR_EL1;
3214                    }
3215                    break;
3216                }
3217                break;
3218              case 4:
3219                switch (crm) {
3220                  case 2:
3221                    switch (op2) {
3222                      case 0:
3223                        return MISCREG_MAIR_EL2;
3224                    }
3225                    break;
3226                  case 3:
3227                    switch (op2) {
3228                      case 0:
3229                        return MISCREG_AMAIR_EL2;
3230                    }
3231                    break;
3232                }
3233                break;
3234              case 6:
3235                switch (crm) {
3236                  case 2:
3237                    switch (op2) {
3238                      case 0:
3239                        return MISCREG_MAIR_EL3;
3240                    }
3241                    break;
3242                  case 3:
3243                    switch (op2) {
3244                      case 0:
3245                        return MISCREG_AMAIR_EL3;
3246                    }
3247                    break;
3248                }
3249                break;
3250            }
3251            break;
3252          case 11:
3253            switch (op1) {
3254              case 1:
3255                switch (crm) {
3256                  case 0:
3257                    switch (op2) {
3258                      case 2:
3259                        return MISCREG_L2CTLR_EL1;
3260                      case 3:
3261                        return MISCREG_L2ECTLR_EL1;
3262                    }
3263                    break;
3264                }
3265                break;
3266            }
3267            break;
3268          case 12:
3269            switch (op1) {
3270              case 0:
3271                switch (crm) {
3272                  case 0:
3273                    switch (op2) {
3274                      case 0:
3275                        return MISCREG_VBAR_EL1;
3276                      case 1:
3277                        return MISCREG_RVBAR_EL1;
3278                    }
3279                    break;
3280                  case 1:
3281                    switch (op2) {
3282                      case 0:
3283                        return MISCREG_ISR_EL1;
3284                    }
3285                    break;
3286                }
3287                break;
3288              case 4:
3289                switch (crm) {
3290                  case 0:
3291                    switch (op2) {
3292                      case 0:
3293                        return MISCREG_VBAR_EL2;
3294                      case 1:
3295                        return MISCREG_RVBAR_EL2;
3296                    }
3297                    break;
3298                }
3299                break;
3300              case 6:
3301                switch (crm) {
3302                  case 0:
3303                    switch (op2) {
3304                      case 0:
3305                        return MISCREG_VBAR_EL3;
3306                      case 1:
3307                        return MISCREG_RVBAR_EL3;
3308                      case 2:
3309                        return MISCREG_RMR_EL3;
3310                    }
3311                    break;
3312                }
3313                break;
3314            }
3315            break;
3316          case 13:
3317            switch (op1) {
3318              case 0:
3319                switch (crm) {
3320                  case 0:
3321                    switch (op2) {
3322                      case 1:
3323                        return MISCREG_CONTEXTIDR_EL1;
3324                      case 4:
3325                        return MISCREG_TPIDR_EL1;
3326                    }
3327                    break;
3328                }
3329                break;
3330              case 3:
3331                switch (crm) {
3332                  case 0:
3333                    switch (op2) {
3334                      case 2:
3335                        return MISCREG_TPIDR_EL0;
3336                      case 3:
3337                        return MISCREG_TPIDRRO_EL0;
3338                    }
3339                    break;
3340                }
3341                break;
3342              case 4:
3343                switch (crm) {
3344                  case 0:
3345                    switch (op2) {
3346                      case 1:
3347                        return MISCREG_CONTEXTIDR_EL2;
3348                      case 2:
3349                        return MISCREG_TPIDR_EL2;
3350                    }
3351                    break;
3352                }
3353                break;
3354              case 6:
3355                switch (crm) {
3356                  case 0:
3357                    switch (op2) {
3358                      case 2:
3359                        return MISCREG_TPIDR_EL3;
3360                    }
3361                    break;
3362                }
3363                break;
3364            }
3365            break;
3366          case 14:
3367            switch (op1) {
3368              case 0:
3369                switch (crm) {
3370                  case 1:
3371                    switch (op2) {
3372                      case 0:
3373                        return MISCREG_CNTKCTL_EL1;
3374                    }
3375                    break;
3376                }
3377                break;
3378              case 3:
3379                switch (crm) {
3380                  case 0:
3381                    switch (op2) {
3382                      case 0:
3383                        return MISCREG_CNTFRQ_EL0;
3384                      case 1:
3385                        return MISCREG_CNTPCT_EL0;
3386                      case 2:
3387                        return MISCREG_CNTVCT_EL0;
3388                    }
3389                    break;
3390                  case 2:
3391                    switch (op2) {
3392                      case 0:
3393                        return MISCREG_CNTP_TVAL_EL0;
3394                      case 1:
3395                        return MISCREG_CNTP_CTL_EL0;
3396                      case 2:
3397                        return MISCREG_CNTP_CVAL_EL0;
3398                    }
3399                    break;
3400                  case 3:
3401                    switch (op2) {
3402                      case 0:
3403                        return MISCREG_CNTV_TVAL_EL0;
3404                      case 1:
3405                        return MISCREG_CNTV_CTL_EL0;
3406                      case 2:
3407                        return MISCREG_CNTV_CVAL_EL0;
3408                    }
3409                    break;
3410                  case 8:
3411                    switch (op2) {
3412                      case 0:
3413                        return MISCREG_PMEVCNTR0_EL0;
3414                      case 1:
3415                        return MISCREG_PMEVCNTR1_EL0;
3416                      case 2:
3417                        return MISCREG_PMEVCNTR2_EL0;
3418                      case 3:
3419                        return MISCREG_PMEVCNTR3_EL0;
3420                      case 4:
3421                        return MISCREG_PMEVCNTR4_EL0;
3422                      case 5:
3423                        return MISCREG_PMEVCNTR5_EL0;
3424                    }
3425                    break;
3426                  case 12:
3427                    switch (op2) {
3428                      case 0:
3429                        return MISCREG_PMEVTYPER0_EL0;
3430                      case 1:
3431                        return MISCREG_PMEVTYPER1_EL0;
3432                      case 2:
3433                        return MISCREG_PMEVTYPER2_EL0;
3434                      case 3:
3435                        return MISCREG_PMEVTYPER3_EL0;
3436                      case 4:
3437                        return MISCREG_PMEVTYPER4_EL0;
3438                      case 5:
3439                        return MISCREG_PMEVTYPER5_EL0;
3440                    }
3441                    break;
3442                  case 15:
3443                    switch (op2) {
3444                      case 7:
3445                        return MISCREG_PMCCFILTR_EL0;
3446                    }
3447                }
3448                break;
3449              case 4:
3450                switch (crm) {
3451                  case 0:
3452                    switch (op2) {
3453                      case 3:
3454                        return MISCREG_CNTVOFF_EL2;
3455                    }
3456                    break;
3457                  case 1:
3458                    switch (op2) {
3459                      case 0:
3460                        return MISCREG_CNTHCTL_EL2;
3461                    }
3462                    break;
3463                  case 2:
3464                    switch (op2) {
3465                      case 0:
3466                        return MISCREG_CNTHP_TVAL_EL2;
3467                      case 1:
3468                        return MISCREG_CNTHP_CTL_EL2;
3469                      case 2:
3470                        return MISCREG_CNTHP_CVAL_EL2;
3471                    }
3472                    break;
3473                }
3474                break;
3475              case 7:
3476                switch (crm) {
3477                  case 2:
3478                    switch (op2) {
3479                      case 0:
3480                        return MISCREG_CNTPS_TVAL_EL1;
3481                      case 1:
3482                        return MISCREG_CNTPS_CTL_EL1;
3483                      case 2:
3484                        return MISCREG_CNTPS_CVAL_EL1;
3485                    }
3486                    break;
3487                }
3488                break;
3489            }
3490            break;
3491          case 15:
3492            switch (op1) {
3493              case 0:
3494                switch (crm) {
3495                  case 0:
3496                    switch (op2) {
3497                      case 0:
3498                        return MISCREG_IL1DATA0_EL1;
3499                      case 1:
3500                        return MISCREG_IL1DATA1_EL1;
3501                      case 2:
3502                        return MISCREG_IL1DATA2_EL1;
3503                      case 3:
3504                        return MISCREG_IL1DATA3_EL1;
3505                    }
3506                    break;
3507                  case 1:
3508                    switch (op2) {
3509                      case 0:
3510                        return MISCREG_DL1DATA0_EL1;
3511                      case 1:
3512                        return MISCREG_DL1DATA1_EL1;
3513                      case 2:
3514                        return MISCREG_DL1DATA2_EL1;
3515                      case 3:
3516                        return MISCREG_DL1DATA3_EL1;
3517                      case 4:
3518                        return MISCREG_DL1DATA4_EL1;
3519                    }
3520                    break;
3521                }
3522                break;
3523              case 1:
3524                switch (crm) {
3525                  case 0:
3526                    switch (op2) {
3527                      case 0:
3528                        return MISCREG_L2ACTLR_EL1;
3529                    }
3530                    break;
3531                  case 2:
3532                    switch (op2) {
3533                      case 0:
3534                        return MISCREG_CPUACTLR_EL1;
3535                      case 1:
3536                        return MISCREG_CPUECTLR_EL1;
3537                      case 2:
3538                        return MISCREG_CPUMERRSR_EL1;
3539                      case 3:
3540                        return MISCREG_L2MERRSR_EL1;
3541                    }
3542                    break;
3543                  case 3:
3544                    switch (op2) {
3545                      case 0:
3546                        return MISCREG_CBAR_EL1;
3547
3548                    }
3549                    break;
3550                }
3551                break;
3552            }
3553            break;
3554        }
3555        break;
3556    }
3557
3558    return MISCREG_UNKNOWN;
3559}
3560
3561} // namespace ArmISA
3562