locked_mem.hh revision 8209:9e3f7f00fa90 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Ali Saidi
30 *          Steve Reinhardt
31 *          Stephen Hines
32 */
33
34#ifndef __ARCH_ARM_LOCKED_MEM_HH__
35#define __ARCH_ARM_LOCKED_MEM_HH__
36
37/**
38 * @file
39 *
40 * ISA-specific helper functions for locked memory accesses.
41 */
42
43#include "arch/arm/miscregs.hh"
44#include "mem/request.hh"
45
46
47namespace ArmISA
48{
49template <class XC>
50inline void
51handleLockedRead(XC *xc, Request *req)
52{
53    xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
54    xc->setMiscReg(MISCREG_LOCKFLAG, true);
55}
56
57
58template <class XC>
59inline bool
60handleLockedWrite(XC *xc, Request *req)
61{
62    if (req->isSwap())
63        return true;
64
65    // Verify that the lock flag is still set and the address
66    // is correct
67    bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
68    Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
69    if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
70        // Lock flag not set or addr mismatch in CPU;
71        // don't even bother sending to memory system
72        req->setExtraData(0);
73        xc->setMiscReg(MISCREG_LOCKFLAG, false);
74        // the rest of this code is not architectural;
75        // it's just a debugging aid to help detect
76        // livelock by warning on long sequences of failed
77        // store conditionals
78        int stCondFailures = xc->readStCondFailures();
79        stCondFailures++;
80        xc->setStCondFailures(stCondFailures);
81        if (stCondFailures % 100000 == 0) {
82            warn("context %d: %d consecutive "
83                 "store conditional failures\n",
84                 xc->contextId(), stCondFailures);
85        }
86
87        // store conditional failed already, so don't issue it to mem
88        return false;
89    }
90    return true;
91}
92
93
94} // namespace ArmISA
95
96#endif
97