locked_mem.hh revision 9383
12568SN/A/* 212652Sandreas.sandberg@arm.com * Copyright (c) 2012 ARM Limited 38668Sgeoffrey.blake@arm.com * All rights reserved 48668Sgeoffrey.blake@arm.com * 58668Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68668Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78668Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88668Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98668Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108668Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118668Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128668Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138668Sgeoffrey.blake@arm.com * 142568SN/A * Copyright (c) 2006 The Regents of The University of Michigan 1510975Sdavid.hashe@amd.com * Copyright (c) 2007-2008 The Florida State University 162568SN/A * All rights reserved. 172568SN/A * 182568SN/A * Redistribution and use in source and binary forms, with or without 192568SN/A * modification, are permitted provided that the following conditions are 202568SN/A * met: redistributions of source code must retain the above copyright 212568SN/A * notice, this list of conditions and the following disclaimer; 222568SN/A * redistributions in binary form must reproduce the above copyright 232568SN/A * notice, this list of conditions and the following disclaimer in the 242568SN/A * documentation and/or other materials provided with the distribution; 252568SN/A * neither the name of the copyright holders nor the names of its 262568SN/A * contributors may be used to endorse or promote products derived from 272568SN/A * this software without specific prior written permission. 282568SN/A * 292568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 422665Ssaidi@eecs.umich.edu * Steve Reinhardt 432568SN/A * Stephen Hines 442568SN/A */ 452568SN/A 462568SN/A#ifndef __ARCH_ARM_LOCKED_MEM_HH__ 472568SN/A#define __ARCH_ARM_LOCKED_MEM_HH__ 482568SN/A 492568SN/A/** 503260Ssaidi@eecs.umich.edu * @file 5111793Sbrandon.potter@amd.com * 5211793Sbrandon.potter@amd.com * ISA-specific helper functions for locked memory accesses. 538229Snate@binkert.org */ 543260Ssaidi@eecs.umich.edu 558229Snate@binkert.org#include "arch/arm/miscregs.hh" 565314Sstever@gmail.com#include "mem/packet.hh" 5712334Sgabeblack@google.com#include "mem/request.hh" 583348Sbinkertn@umich.edu 5912652Sandreas.sandberg@arm.comnamespace ArmISA 602568SN/A{ 615735Snate@binkert.orgtemplate <class XC> 625735Snate@binkert.orginline void 634022Sstever@eecs.umich.eduhandleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) 644022Sstever@eecs.umich.edu{ 654022Sstever@eecs.umich.edu if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 664022Sstever@eecs.umich.edu return; 674022Sstever@eecs.umich.edu 684022Sstever@eecs.umich.edu Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 694022Sstever@eecs.umich.edu Addr snoop_addr = pkt->getAddr(); 7011600Sandreas.hansson@arm.com 7111600Sandreas.hansson@arm.com assert((cacheBlockMask & snoop_addr) == snoop_addr); 722641Sstever@eecs.umich.edu 734022Sstever@eecs.umich.edu if (locked_addr == snoop_addr) 744022Sstever@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKFLAG, false); 752641Sstever@eecs.umich.edu} 764022Sstever@eecs.umich.edu 774022Sstever@eecs.umich.edutemplate <class XC> 7810885Sandreas.hansson@arm.cominline void 7910885Sandreas.hansson@arm.comhandleLockedRead(XC *xc, Request *req) 804022Sstever@eecs.umich.edu{ 814473Sstever@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 824473Sstever@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKFLAG, true); 835319Sstever@gmail.com} 845319Sstever@gmail.com 855319Sstever@gmail.com 864022Sstever@eecs.umich.edutemplate <class XC> 8711284Sandreas.hansson@arm.cominline bool 884022Sstever@eecs.umich.eduhandleLockedWrite(XC *xc, Request *req) 894022Sstever@eecs.umich.edu{ 9011287Sandreas.hansson@arm.com if (req->isSwap()) 9111199Sandreas.hansson@arm.com return true; 9211600Sandreas.hansson@arm.com 9311199Sandreas.hansson@arm.com // Verify that the lock flag is still set and the address 9411199Sandreas.hansson@arm.com // is correct 9511199Sandreas.hansson@arm.com bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 9611199Sandreas.hansson@arm.com Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); 9711600Sandreas.hansson@arm.com if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 9811199Sandreas.hansson@arm.com // Lock flag not set or addr mismatch in CPU; 9912344Snikos.nikoleris@arm.com // don't even bother sending to memory system 10012344Snikos.nikoleris@arm.com req->setExtraData(0); 10112344Snikos.nikoleris@arm.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 10210883Sali.jafri@arm.com // the rest of this code is not architectural; 10311600Sandreas.hansson@arm.com // it's just a debugging aid to help detect 1044022Sstever@eecs.umich.edu // livelock by warning on long sequences of failed 1054022Sstever@eecs.umich.edu // store conditionals 1064022Sstever@eecs.umich.edu int stCondFailures = xc->readStCondFailures(); 1074022Sstever@eecs.umich.edu stCondFailures++; 10811600Sandreas.hansson@arm.com xc->setStCondFailures(stCondFailures); 1094022Sstever@eecs.umich.edu if (stCondFailures % 100000 == 0) { 1104022Sstever@eecs.umich.edu warn("context %d: %d consecutive " 1114022Sstever@eecs.umich.edu "store conditional failures\n", 1124022Sstever@eecs.umich.edu xc->contextId(), stCondFailures); 1134022Sstever@eecs.umich.edu } 1144022Sstever@eecs.umich.edu 1154022Sstever@eecs.umich.edu // store conditional failed already, so don't issue it to mem 11610886Sandreas.hansson@arm.com return false; 11711284Sandreas.hansson@arm.com } 11810886Sandreas.hansson@arm.com return true; 1194022Sstever@eecs.umich.edu} 12011600Sandreas.hansson@arm.com 12111600Sandreas.hansson@arm.com 1224628Sstever@eecs.umich.edu} // namespace ArmISA 1237465Ssteve.reinhardt@amd.com 12411600Sandreas.hansson@arm.com#endif 12511600Sandreas.hansson@arm.com