locked_mem.hh revision 10574
16019Shines@cs.fsu.edu/* 210030SAli.Saidi@ARM.com * Copyright (c) 2012-2013 ARM Limited 39383SAli.Saidi@ARM.com * All rights reserved 49383SAli.Saidi@ARM.com * 59383SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 69383SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 79383SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 89383SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 99383SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 109383SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 119383SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 129383SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 139383SAli.Saidi@ARM.com * 146019Shines@cs.fsu.edu * Copyright (c) 2006 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 418209SAli.Saidi@ARM.com * Authors: Ali Saidi 428209SAli.Saidi@ARM.com * Steve Reinhardt 436019Shines@cs.fsu.edu * Stephen Hines 446019Shines@cs.fsu.edu */ 456019Shines@cs.fsu.edu 466019Shines@cs.fsu.edu#ifndef __ARCH_ARM_LOCKED_MEM_HH__ 476019Shines@cs.fsu.edu#define __ARCH_ARM_LOCKED_MEM_HH__ 486019Shines@cs.fsu.edu 496019Shines@cs.fsu.edu/** 506019Shines@cs.fsu.edu * @file 516019Shines@cs.fsu.edu * 526019Shines@cs.fsu.edu * ISA-specific helper functions for locked memory accesses. 536019Shines@cs.fsu.edu */ 546019Shines@cs.fsu.edu 558209SAli.Saidi@ARM.com#include "arch/arm/miscregs.hh" 5610037SARM gem5 Developers#include "arch/arm/isa_traits.hh" 5710037SARM gem5 Developers#include "debug/LLSC.hh" 589383SAli.Saidi@ARM.com#include "mem/packet.hh" 596019Shines@cs.fsu.edu#include "mem/request.hh" 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.edunamespace ArmISA 626019Shines@cs.fsu.edu{ 636019Shines@cs.fsu.edutemplate <class XC> 646019Shines@cs.fsu.eduinline void 659383SAli.Saidi@ARM.comhandleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) 669383SAli.Saidi@ARM.com{ 6710037SARM gem5 Developers DPRINTF(LLSC,"%s: handleing snoop for address: %#x locked: %d\n", 6810037SARM gem5 Developers xc->getCpuPtr()->name(),pkt->getAddr(), 6910037SARM gem5 Developers xc->readMiscReg(MISCREG_LOCKFLAG)); 709383SAli.Saidi@ARM.com if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 719383SAli.Saidi@ARM.com return; 729383SAli.Saidi@ARM.com 739383SAli.Saidi@ARM.com Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 7410037SARM gem5 Developers // If no caches are attached, the snoop address always needs to be masked 7510030SAli.Saidi@ARM.com Addr snoop_addr = pkt->getAddr() & cacheBlockMask; 769383SAli.Saidi@ARM.com 7710037SARM gem5 Developers DPRINTF(LLSC,"%s: handleing snoop for address: %#x locked addr: %#x\n", 7810037SARM gem5 Developers xc->getCpuPtr()->name(),snoop_addr, locked_addr); 7910037SARM gem5 Developers if (locked_addr == snoop_addr) { 8010037SARM gem5 Developers DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n", 8110037SARM gem5 Developers xc->getCpuPtr()->name()); 829383SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 8310037SARM gem5 Developers // Implement ARMv8 WFE/SEV semantics 8410037SARM gem5 Developers xc->setMiscReg(MISCREG_SEV_MAILBOX, true); 8510037SARM gem5 Developers xc->getCpuPtr()->wakeup(); 8610037SARM gem5 Developers } 8710030SAli.Saidi@ARM.com} 8810030SAli.Saidi@ARM.com 8910030SAli.Saidi@ARM.comtemplate <class XC> 9010030SAli.Saidi@ARM.cominline void 916019Shines@cs.fsu.eduhandleLockedRead(XC *xc, Request *req) 926019Shines@cs.fsu.edu{ 9310030SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr()); 948209SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, true); 9510037SARM gem5 Developers DPRINTF(LLSC,"%s: Placing address %#x in monitor\n", xc->getCpuPtr()->name(), 9610037SARM gem5 Developers req->getPaddr()); 976019Shines@cs.fsu.edu} 986019Shines@cs.fsu.edu 9910037SARM gem5 Developerstemplate <class XC> 10010037SARM gem5 Developersinline void 10110037SARM gem5 DevelopershandleLockedSnoopHit(XC *xc) 10210037SARM gem5 Developers{ 10310037SARM gem5 Developers DPRINTF(LLSC,"%s: handling snoop lock hit address: %#x\n", 10410037SARM gem5 Developers xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR)); 10510037SARM gem5 Developers xc->setMiscReg(MISCREG_LOCKFLAG, false); 10610037SARM gem5 Developers xc->setMiscReg(MISCREG_SEV_MAILBOX, true); 10710037SARM gem5 Developers} 1086019Shines@cs.fsu.edu 1096019Shines@cs.fsu.edutemplate <class XC> 1106019Shines@cs.fsu.eduinline bool 11110030SAli.Saidi@ARM.comhandleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask) 1126019Shines@cs.fsu.edu{ 1138209SAli.Saidi@ARM.com if (req->isSwap()) 1148209SAli.Saidi@ARM.com return true; 1158209SAli.Saidi@ARM.com 11610037SARM gem5 Developers DPRINTF(LLSC,"%s: handling locked write for address %#x in monitor\n", 11710037SARM gem5 Developers xc->getCpuPtr()->name(), req->getPaddr()); 1188209SAli.Saidi@ARM.com // Verify that the lock flag is still set and the address 1198209SAli.Saidi@ARM.com // is correct 1208209SAli.Saidi@ARM.com bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 12110030SAli.Saidi@ARM.com Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 12210030SAli.Saidi@ARM.com if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) { 1238209SAli.Saidi@ARM.com // Lock flag not set or addr mismatch in CPU; 1248209SAli.Saidi@ARM.com // don't even bother sending to memory system 1258209SAli.Saidi@ARM.com req->setExtraData(0); 1268209SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 12710037SARM gem5 Developers DPRINTF(LLSC,"%s: clearing lock flag in handle locked write\n", 12810037SARM gem5 Developers xc->getCpuPtr()->name()); 1298209SAli.Saidi@ARM.com // the rest of this code is not architectural; 1308209SAli.Saidi@ARM.com // it's just a debugging aid to help detect 1318209SAli.Saidi@ARM.com // livelock by warning on long sequences of failed 1328209SAli.Saidi@ARM.com // store conditionals 1338209SAli.Saidi@ARM.com int stCondFailures = xc->readStCondFailures(); 1348209SAli.Saidi@ARM.com stCondFailures++; 1358209SAli.Saidi@ARM.com xc->setStCondFailures(stCondFailures); 1368209SAli.Saidi@ARM.com if (stCondFailures % 100000 == 0) { 1378209SAli.Saidi@ARM.com warn("context %d: %d consecutive " 1388209SAli.Saidi@ARM.com "store conditional failures\n", 1398209SAli.Saidi@ARM.com xc->contextId(), stCondFailures); 1408209SAli.Saidi@ARM.com } 1418209SAli.Saidi@ARM.com 1428209SAli.Saidi@ARM.com // store conditional failed already, so don't issue it to mem 1438209SAli.Saidi@ARM.com return false; 1448209SAli.Saidi@ARM.com } 1456019Shines@cs.fsu.edu return true; 1466019Shines@cs.fsu.edu} 1476019Shines@cs.fsu.edu 1486019Shines@cs.fsu.edu 1496019Shines@cs.fsu.edu} // namespace ArmISA 1506019Shines@cs.fsu.edu 1516019Shines@cs.fsu.edu#endif 152