locked_mem.hh revision 10037
15625Sgblack@eecs.umich.edu/* 25625Sgblack@eecs.umich.edu * Copyright (c) 2012-2013 ARM Limited 35625Sgblack@eecs.umich.edu * All rights reserved 45625Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 135625Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Copyright (c) 2006 The Regents of The University of Michigan 157087Snate@binkert.org * Copyright (c) 2007-2008 The Florida State University 167087Snate@binkert.org * All rights reserved. 177087Snate@binkert.org * 187087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 197087Snate@binkert.org * modification, are permitted provided that the following conditions are 207087Snate@binkert.org * met: redistributions of source code must retain the above copyright 217087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 225625Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 237087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 245625Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 255625Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265625Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275625Sgblack@eecs.umich.edu * this software without specific prior written permission. 285625Sgblack@eecs.umich.edu * 295625Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305625Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315625Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325625Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335625Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345625Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355625Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365625Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375625Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385625Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395625Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405625Sgblack@eecs.umich.edu * 415625Sgblack@eecs.umich.edu * Authors: Ali Saidi 425625Sgblack@eecs.umich.edu * Steve Reinhardt 435625Sgblack@eecs.umich.edu * Stephen Hines 445625Sgblack@eecs.umich.edu */ 455625Sgblack@eecs.umich.edu 465625Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_LOCKED_MEM_HH__ 475625Sgblack@eecs.umich.edu#define __ARCH_ARM_LOCKED_MEM_HH__ 485625Sgblack@eecs.umich.edu 495625Sgblack@eecs.umich.edu/** 505625Sgblack@eecs.umich.edu * @file 515625Sgblack@eecs.umich.edu * 528229Snate@binkert.org * ISA-specific helper functions for locked memory accesses. 535625Sgblack@eecs.umich.edu */ 548706Sandreas.hansson@arm.com 555625Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 565625Sgblack@eecs.umich.edu#include "arch/arm/isa_traits.hh" 575625Sgblack@eecs.umich.edu#include "debug/LLSC.hh" 585625Sgblack@eecs.umich.edu#include "mem/packet.hh" 595625Sgblack@eecs.umich.edu#include "mem/request.hh" 605625Sgblack@eecs.umich.edu 615625Sgblack@eecs.umich.edunamespace ArmISA 625625Sgblack@eecs.umich.edu{ 635625Sgblack@eecs.umich.edutemplate <class XC> 645625Sgblack@eecs.umich.eduinline void 655625Sgblack@eecs.umich.eduhandleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) 665625Sgblack@eecs.umich.edu{ 675625Sgblack@eecs.umich.edu DPRINTF(LLSC,"%s: handleing snoop for address: %#x locked: %d\n", 685625Sgblack@eecs.umich.edu xc->getCpuPtr()->name(),pkt->getAddr(), 695625Sgblack@eecs.umich.edu xc->readMiscReg(MISCREG_LOCKFLAG)); 705625Sgblack@eecs.umich.edu if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 715625Sgblack@eecs.umich.edu return; 725625Sgblack@eecs.umich.edu 735625Sgblack@eecs.umich.edu Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 745625Sgblack@eecs.umich.edu // If no caches are attached, the snoop address always needs to be masked 755625Sgblack@eecs.umich.edu Addr snoop_addr = pkt->getAddr() & cacheBlockMask; 765625Sgblack@eecs.umich.edu 775625Sgblack@eecs.umich.edu DPRINTF(LLSC,"%s: handleing snoop for address: %#x locked addr: %#x\n", 785625Sgblack@eecs.umich.edu xc->getCpuPtr()->name(),snoop_addr, locked_addr); 795625Sgblack@eecs.umich.edu if (locked_addr == snoop_addr) { 805625Sgblack@eecs.umich.edu DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n", 815625Sgblack@eecs.umich.edu xc->getCpuPtr()->name()); 825625Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKFLAG, false); 835625Sgblack@eecs.umich.edu // Implement ARMv8 WFE/SEV semantics 845625Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_SEV_MAILBOX, true); 855625Sgblack@eecs.umich.edu xc->getCpuPtr()->wakeup(); 865625Sgblack@eecs.umich.edu } 875625Sgblack@eecs.umich.edu} 885625Sgblack@eecs.umich.edu 895625Sgblack@eecs.umich.edutemplate <class XC> 905625Sgblack@eecs.umich.eduinline void 915625Sgblack@eecs.umich.eduhandleLockedRead(XC *xc, Request *req) 925625Sgblack@eecs.umich.edu{ 935625Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr()); 945625Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKFLAG, true); 955625Sgblack@eecs.umich.edu DPRINTF(LLSC,"%s: Placing address %#x in monitor\n", xc->getCpuPtr()->name(), 968706Sandreas.hansson@arm.com req->getPaddr()); 975625Sgblack@eecs.umich.edu} 985625Sgblack@eecs.umich.edu 995625Sgblack@eecs.umich.edutemplate <class XC> 1005625Sgblack@eecs.umich.eduinline void 1015625Sgblack@eecs.umich.eduhandleLockedSnoopHit(XC *xc) 1025625Sgblack@eecs.umich.edu{ 1035625Sgblack@eecs.umich.edu DPRINTF(LLSC,"%s: handling snoop lock hit address: %#x\n", 1045625Sgblack@eecs.umich.edu xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR)); 1055625Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKFLAG, false); 1065625Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_SEV_MAILBOX, true); 1075625Sgblack@eecs.umich.edu} 1085625Sgblack@eecs.umich.edu 1095625Sgblack@eecs.umich.edutemplate <class XC> 1105625Sgblack@eecs.umich.eduinline bool 1115625Sgblack@eecs.umich.eduhandleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask) 1125625Sgblack@eecs.umich.edu{ 1135625Sgblack@eecs.umich.edu if (req->isSwap()) 1145625Sgblack@eecs.umich.edu return true; 1155625Sgblack@eecs.umich.edu 1165625Sgblack@eecs.umich.edu DPRINTF(LLSC,"%s: handling locked write for address %#x in monitor\n", 1175625Sgblack@eecs.umich.edu xc->getCpuPtr()->name(), req->getPaddr()); 1185625Sgblack@eecs.umich.edu // Verify that the lock flag is still set and the address 1195625Sgblack@eecs.umich.edu // is correct 1208706Sandreas.hansson@arm.com bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 1215625Sgblack@eecs.umich.edu Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 1225625Sgblack@eecs.umich.edu if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) { 1235625Sgblack@eecs.umich.edu // Lock flag not set or addr mismatch in CPU; 1245625Sgblack@eecs.umich.edu // don't even bother sending to memory system 1255625Sgblack@eecs.umich.edu req->setExtraData(0); 1265625Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_LOCKFLAG, false); 1275625Sgblack@eecs.umich.edu DPRINTF(LLSC,"%s: clearing lock flag in handle locked write\n", 1285625Sgblack@eecs.umich.edu xc->getCpuPtr()->name()); 1295625Sgblack@eecs.umich.edu // the rest of this code is not architectural; 1305625Sgblack@eecs.umich.edu // it's just a debugging aid to help detect 1315625Sgblack@eecs.umich.edu // livelock by warning on long sequences of failed 1325625Sgblack@eecs.umich.edu // store conditionals 1335625Sgblack@eecs.umich.edu int stCondFailures = xc->readStCondFailures(); 1345625Sgblack@eecs.umich.edu stCondFailures++; 1358706Sandreas.hansson@arm.com xc->setStCondFailures(stCondFailures); 1365625Sgblack@eecs.umich.edu if (stCondFailures % 100000 == 0) { 1375625Sgblack@eecs.umich.edu warn("context %d: %d consecutive " 1385625Sgblack@eecs.umich.edu "store conditional failures\n", 1395625Sgblack@eecs.umich.edu xc->contextId(), stCondFailures); 1405625Sgblack@eecs.umich.edu } 1415625Sgblack@eecs.umich.edu 1425625Sgblack@eecs.umich.edu // store conditional failed already, so don't issue it to mem 1435625Sgblack@eecs.umich.edu return false; 1445625Sgblack@eecs.umich.edu } 1455625Sgblack@eecs.umich.edu return true; 1465625Sgblack@eecs.umich.edu} 1475625Sgblack@eecs.umich.edu 1485625Sgblack@eecs.umich.edu 1495625Sgblack@eecs.umich.edu} // namespace ArmISA 1505625Sgblack@eecs.umich.edu 1515625Sgblack@eecs.umich.edu#endif 1525625Sgblack@eecs.umich.edu