gic.hh revision 11461:294fe30960f0
1/* 2 * Copyright (c) 2015-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Sandberg 38 */ 39 40#ifndef __ARCH_ARM_KVM_GIC_HH__ 41#define __ARCH_ARM_KVM_GIC_HH__ 42 43#include "arch/arm/system.hh" 44#include "cpu/kvm/device.hh" 45#include "cpu/kvm/vm.hh" 46#include "dev/arm/base_gic.hh" 47#include "dev/platform.hh" 48 49/** 50 * KVM in-kernel GIC abstraction 51 * 52 * This class defines a high-level interface to the KVM in-kernel GIC 53 * model. It exposes an API that is similar to that of 54 * software-emulated GIC models in gem5. 55 */ 56class KvmKernelGicV2 57{ 58 public: 59 /** 60 * Instantiate a KVM in-kernel GIC model. 61 * 62 * This constructor instantiates an in-kernel GIC model and wires 63 * it up to the virtual memory system. 64 * 65 * @param vm KVM VM representing this system 66 * @param cpu_addr GIC CPU interface base address 67 * @param dist_addr GIC distributor base address 68 */ 69 KvmKernelGicV2(KvmVM &vm, Addr cpu_addr, Addr dist_addr); 70 virtual ~KvmKernelGicV2(); 71 72 KvmKernelGicV2(const KvmKernelGicV2 &other) = delete; 73 KvmKernelGicV2(const KvmKernelGicV2 &&other) = delete; 74 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &&rhs) = delete; 75 KvmKernelGicV2 &operator=(const KvmKernelGicV2 &rhs) = delete; 76 77 public: 78 /** 79 * @{ 80 * @name In-kernel GIC API 81 */ 82 83 /** 84 * Raise a shared peripheral interrupt 85 * 86 * @param spi SPI number 87 */ 88 void setSPI(unsigned spi); 89 /** 90 * Clear a shared peripheral interrupt 91 * 92 * @param spi SPI number 93 */ 94 void clearSPI(unsigned spi); 95 96 /** 97 * Raise a private peripheral interrupt 98 * 99 * @param vcpu KVM virtual CPU number 100 * @parma ppi PPI interrupt number 101 */ 102 void setPPI(unsigned vcpu, unsigned ppi); 103 104 /** 105 * Clear a private peripheral interrupt 106 * 107 * @param vcpu KVM virtual CPU number 108 * @parma ppi PPI interrupt number 109 */ 110 void clearPPI(unsigned vcpu, unsigned ppi); 111 112 /** Address range for the CPU interfaces */ 113 const AddrRange cpuRange; 114 /** Address range for the distributor interface */ 115 const AddrRange distRange; 116 117 /* @} */ 118 119 protected: 120 /** 121 * Update the kernel's VGIC interrupt state 122 * 123 * @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI) 124 * @param vcpu CPU id within KVM (ignored for SPIs) 125 * @param irq Interrupt number 126 * @param high True to signal an interrupt, false to clear it. 127 */ 128 void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high); 129 130 /** KVM VM in the parent system */ 131 KvmVM &vm; 132 133 /** Kernel interface to the GIC */ 134 KvmDevice kdev; 135}; 136 137struct KvmGicParams; 138 139/** 140 * In-kernel GIC model. 141 * 142 * When using a KVM-based CPU model, it is possible to offload GIC 143 * emulation to the kernel. This reduces some overheads when the guest 144 * accesses the GIC and makes it possible to use in-kernel 145 * architected/generic timer emulation. 146 * 147 * This device uses interfaces with the kernel GicV2 model that is 148 * documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the 149 * Linux kernel sources. 150 * 151 * This GIC model has the following known limitations: 152 * <ul> 153 * <li>Checkpointing is not supported. 154 * <li>This model only works with kvm. Simulated CPUs are not 155 * supported since this would require the kernel to inject 156 * interrupt into the simulated CPU. 157 * </ul> 158 * 159 * @warn This GIC model cannot be used with simulated CPUs! 160 */ 161class KvmGic : public BaseGic 162{ 163 public: // SimObject / Serializable / Drainable 164 KvmGic(const KvmGicParams *p); 165 ~KvmGic(); 166 167 void startup() override { verifyMemoryMode(); } 168 void drainResume() override { verifyMemoryMode(); } 169 170 void serialize(CheckpointOut &cp) const override; 171 void unserialize(CheckpointIn &cp) override; 172 173 public: // PioDevice 174 AddrRangeList getAddrRanges() const { return addrRanges; } 175 Tick read(PacketPtr pkt) override; 176 Tick write(PacketPtr pkt) override; 177 178 public: // BaseGic 179 void sendInt(uint32_t num) override; 180 void clearInt(uint32_t num) override; 181 182 void sendPPInt(uint32_t num, uint32_t cpu) override; 183 void clearPPInt(uint32_t num, uint32_t cpu) override; 184 185 protected: 186 /** 187 * Do memory mode sanity checks 188 * 189 * This method only really exists to warn users that try to switch 190 * to a simulate CPU. There is no fool proof method to detect 191 * simulated CPUs, but checking that we're in atomic mode and 192 * bypassing caches should be robust enough. 193 */ 194 void verifyMemoryMode() const; 195 196 /** System this interrupt controller belongs to */ 197 System &system; 198 199 /** Kernel GIC device */ 200 KvmKernelGicV2 kernelGic; 201 202 /** Union of all memory */ 203 const AddrRangeList addrRanges; 204}; 205 206#endif // __ARCH_ARM_KVM_GIC_HH__ 207