gic.hh revision 11168:f98eb2da15a4 
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#ifndef __ARCH_ARM_KVM_GIC_HH__
41#define __ARCH_ARM_KVM_GIC_HH__
42
43#include "arch/arm/system.hh"
44#include "cpu/kvm/device.hh"
45#include "cpu/kvm/vm.hh"
46#include "dev/arm/base_gic.hh"
47#include "dev/platform.hh"
48
49class KvmGicParams;
50
51/**
52 * In-kernel GIC model.
53 *
54 * When using a KVM-based CPU model, it is possible to offload GIC
55 * emulation to the kernel. This reduces some overheads when the guest
56 * accesses the GIC and makes it possible to use in-kernel
57 * architected/generic timer emulation.
58 *
59 * This device uses interfaces with the kernel GicV2 model that is
60 * documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the
61 * Linux kernel sources.
62 *
63 * This GIC model has the following known limitations:
64 * <ul>
65 *   <li>Checkpointing is not supported.
66 *   <li>This model only works with kvm. Simulated CPUs are not
67 *       supported since this would require the kernel to inject
68 *       interrupt into the simulated CPU.
69 * </ul>
70 *
71 * @warn This GIC model cannot be used with simulated CPUs!
72 */
73class KvmGic : public BaseGic
74{
75  public: // SimObject / Serializable / Drainable
76    KvmGic(const KvmGicParams *p);
77    ~KvmGic();
78
79    void startup() override { verifyMemoryMode(); }
80    void drainResume() override { verifyMemoryMode(); }
81
82    void serialize(CheckpointOut &cp) const override;
83    void unserialize(Checkpoint *cp, const std::string &sec)  override;
84
85  public: // PioDevice
86    AddrRangeList getAddrRanges() const { return addrRanges; }
87    Tick read(PacketPtr pkt) override;
88    Tick write(PacketPtr pkt) override;
89
90  public: // BaseGic
91    void sendInt(uint32_t num) override;
92    void clearInt(uint32_t num) override;
93
94    void sendPPInt(uint32_t num, uint32_t cpu) override;
95    void clearPPInt(uint32_t num, uint32_t cpu) override;
96
97  protected:
98    /**
99     * Do memory mode sanity checks
100     *
101     * This method only really exists to warn users that try to switch
102     * to a simulate CPU. There is no fool proof method to detect
103     * simulated CPUs, but checking that we're in atomic mode and
104     * bypassing caches should be robust enough.
105     */
106    void verifyMemoryMode() const;
107
108    /**
109     * Update the kernel's VGIC interrupt state
110     *
111     * @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI)
112     * @param vcpu CPU id within KVM (ignored for SPIs)
113     * @param irq Interrupt number
114     * @param high True to signal an interrupt, false to clear it.
115     */
116    void setIntState(uint8_t type, uint8_t vcpu, uint16_t irq, bool high);
117
118    /** System this interrupt controller belongs to */
119    System &system;
120    /** VM for this system */
121    KvmVM &vm;
122    /** Kernel interface to the GIC */
123    KvmDevice kdev;
124
125    /** Address range for the distributor interface */
126    const AddrRange distRange;
127    /** Address range for the CPU interfaces */
128    const AddrRange cpuRange;
129    /** Union of all memory  */
130    const AddrRangeList addrRanges;
131};
132
133#endif // __ARCH_ARM_KVM_GIC_HH__
134