gic.hh revision 11168
110859Sandreas.sandberg@arm.com/* 210859Sandreas.sandberg@arm.com * Copyright (c) 2015 ARM Limited 310859Sandreas.sandberg@arm.com * All rights reserved 410859Sandreas.sandberg@arm.com * 510859Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 610859Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 710859Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 810859Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 910859Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1010859Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1110859Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1210859Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1310859Sandreas.sandberg@arm.com * 1410859Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1510859Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 1610859Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 1710859Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 1810859Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1910859Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2010859Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2110859Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2210859Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2310859Sandreas.sandberg@arm.com * this software without specific prior written permission. 2410859Sandreas.sandberg@arm.com * 2510859Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610859Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710859Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810859Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910859Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010859Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110859Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210859Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310859Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410859Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510859Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610859Sandreas.sandberg@arm.com * 3710859Sandreas.sandberg@arm.com * Authors: Andreas Sandberg 3810859Sandreas.sandberg@arm.com */ 3910859Sandreas.sandberg@arm.com 4010859Sandreas.sandberg@arm.com#ifndef __ARCH_ARM_KVM_GIC_HH__ 4110859Sandreas.sandberg@arm.com#define __ARCH_ARM_KVM_GIC_HH__ 4210859Sandreas.sandberg@arm.com 4310859Sandreas.sandberg@arm.com#include "arch/arm/system.hh" 4410859Sandreas.sandberg@arm.com#include "cpu/kvm/device.hh" 4510859Sandreas.sandberg@arm.com#include "cpu/kvm/vm.hh" 4610859Sandreas.sandberg@arm.com#include "dev/arm/base_gic.hh" 4710859Sandreas.sandberg@arm.com#include "dev/platform.hh" 4810859Sandreas.sandberg@arm.com 4910859Sandreas.sandberg@arm.comclass KvmGicParams; 5010859Sandreas.sandberg@arm.com 5110859Sandreas.sandberg@arm.com/** 5210859Sandreas.sandberg@arm.com * In-kernel GIC model. 5310859Sandreas.sandberg@arm.com * 5410859Sandreas.sandberg@arm.com * When using a KVM-based CPU model, it is possible to offload GIC 5510859Sandreas.sandberg@arm.com * emulation to the kernel. This reduces some overheads when the guest 5610859Sandreas.sandberg@arm.com * accesses the GIC and makes it possible to use in-kernel 5710859Sandreas.sandberg@arm.com * architected/generic timer emulation. 5810859Sandreas.sandberg@arm.com * 5910859Sandreas.sandberg@arm.com * This device uses interfaces with the kernel GicV2 model that is 6010859Sandreas.sandberg@arm.com * documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the 6110859Sandreas.sandberg@arm.com * Linux kernel sources. 6210859Sandreas.sandberg@arm.com * 6310859Sandreas.sandberg@arm.com * This GIC model has the following known limitations: 6410859Sandreas.sandberg@arm.com * <ul> 6510859Sandreas.sandberg@arm.com * <li>Checkpointing is not supported. 6610859Sandreas.sandberg@arm.com * <li>This model only works with kvm. Simulated CPUs are not 6710859Sandreas.sandberg@arm.com * supported since this would require the kernel to inject 6810859Sandreas.sandberg@arm.com * interrupt into the simulated CPU. 6910859Sandreas.sandberg@arm.com * </ul> 7010859Sandreas.sandberg@arm.com * 7110859Sandreas.sandberg@arm.com * @warn This GIC model cannot be used with simulated CPUs! 7210859Sandreas.sandberg@arm.com */ 7310859Sandreas.sandberg@arm.comclass KvmGic : public BaseGic 7410859Sandreas.sandberg@arm.com{ 7510859Sandreas.sandberg@arm.com public: // SimObject / Serializable / Drainable 7610859Sandreas.sandberg@arm.com KvmGic(const KvmGicParams *p); 7710859Sandreas.sandberg@arm.com ~KvmGic(); 7810859Sandreas.sandberg@arm.com 7911168Sandreas.hansson@arm.com void startup() override { verifyMemoryMode(); } 8011168Sandreas.hansson@arm.com void drainResume() override { verifyMemoryMode(); } 8110859Sandreas.sandberg@arm.com 8211168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 8311168Sandreas.hansson@arm.com void unserialize(Checkpoint *cp, const std::string &sec) override; 8410859Sandreas.sandberg@arm.com 8510859Sandreas.sandberg@arm.com public: // PioDevice 8610859Sandreas.sandberg@arm.com AddrRangeList getAddrRanges() const { return addrRanges; } 8711168Sandreas.hansson@arm.com Tick read(PacketPtr pkt) override; 8811168Sandreas.hansson@arm.com Tick write(PacketPtr pkt) override; 8910859Sandreas.sandberg@arm.com 9010859Sandreas.sandberg@arm.com public: // BaseGic 9111168Sandreas.hansson@arm.com void sendInt(uint32_t num) override; 9211168Sandreas.hansson@arm.com void clearInt(uint32_t num) override; 9310859Sandreas.sandberg@arm.com 9411168Sandreas.hansson@arm.com void sendPPInt(uint32_t num, uint32_t cpu) override; 9511168Sandreas.hansson@arm.com void clearPPInt(uint32_t num, uint32_t cpu) override; 9610859Sandreas.sandberg@arm.com 9710859Sandreas.sandberg@arm.com protected: 9810859Sandreas.sandberg@arm.com /** 9910859Sandreas.sandberg@arm.com * Do memory mode sanity checks 10010859Sandreas.sandberg@arm.com * 10110859Sandreas.sandberg@arm.com * This method only really exists to warn users that try to switch 10210859Sandreas.sandberg@arm.com * to a simulate CPU. There is no fool proof method to detect 10310859Sandreas.sandberg@arm.com * simulated CPUs, but checking that we're in atomic mode and 10410859Sandreas.sandberg@arm.com * bypassing caches should be robust enough. 10510859Sandreas.sandberg@arm.com */ 10610859Sandreas.sandberg@arm.com void verifyMemoryMode() const; 10710859Sandreas.sandberg@arm.com 10810859Sandreas.sandberg@arm.com /** 10910859Sandreas.sandberg@arm.com * Update the kernel's VGIC interrupt state 11010859Sandreas.sandberg@arm.com * 11110859Sandreas.sandberg@arm.com * @param type Interrupt type (KVM_ARM_IRQ_TYPE_PPI/KVM_ARM_IRQ_TYPE_SPI) 11210859Sandreas.sandberg@arm.com * @param vcpu CPU id within KVM (ignored for SPIs) 11310859Sandreas.sandberg@arm.com * @param irq Interrupt number 11410859Sandreas.sandberg@arm.com * @param high True to signal an interrupt, false to clear it. 11510859Sandreas.sandberg@arm.com */ 11610859Sandreas.sandberg@arm.com void setIntState(uint8_t type, uint8_t vcpu, uint16_t irq, bool high); 11710859Sandreas.sandberg@arm.com 11810859Sandreas.sandberg@arm.com /** System this interrupt controller belongs to */ 11910859Sandreas.sandberg@arm.com System &system; 12010859Sandreas.sandberg@arm.com /** VM for this system */ 12110859Sandreas.sandberg@arm.com KvmVM &vm; 12210859Sandreas.sandberg@arm.com /** Kernel interface to the GIC */ 12310859Sandreas.sandberg@arm.com KvmDevice kdev; 12410859Sandreas.sandberg@arm.com 12510859Sandreas.sandberg@arm.com /** Address range for the distributor interface */ 12610859Sandreas.sandberg@arm.com const AddrRange distRange; 12710859Sandreas.sandberg@arm.com /** Address range for the CPU interfaces */ 12810859Sandreas.sandberg@arm.com const AddrRange cpuRange; 12910859Sandreas.sandberg@arm.com /** Union of all memory */ 13010859Sandreas.sandberg@arm.com const AddrRangeList addrRanges; 13110859Sandreas.sandberg@arm.com}; 13210859Sandreas.sandberg@arm.com 13310859Sandreas.sandberg@arm.com#endif // __ARCH_ARM_KVM_GIC_HH__ 134