armv8_cpu.hh revision 10860:cba0f26038b4
12568SN/A/* 28713Sandreas.hansson@arm.com * Copyright (c) 2015 ARM Limited 38713Sandreas.hansson@arm.com * All rights reserved 48713Sandreas.hansson@arm.com * 58713Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68713Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78713Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88713Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98713Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108713Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118713Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128713Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138713Sandreas.hansson@arm.com * 142568SN/A * Redistribution and use in source and binary forms, with or without 152568SN/A * modification, are permitted provided that the following conditions are 162568SN/A * met: redistributions of source code must retain the above copyright 172568SN/A * notice, this list of conditions and the following disclaimer; 182568SN/A * redistributions in binary form must reproduce the above copyright 192568SN/A * notice, this list of conditions and the following disclaimer in the 202568SN/A * documentation and/or other materials provided with the distribution; 212568SN/A * neither the name of the copyright holders nor the names of its 222568SN/A * contributors may be used to endorse or promote products derived from 232568SN/A * this software without specific prior written permission. 242568SN/A * 252568SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262568SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302568SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312568SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362568SN/A * 372568SN/A * Authors: Andreas Sandberg 382568SN/A */ 392665Ssaidi@eecs.umich.edu 402665Ssaidi@eecs.umich.edu#ifndef __ARCH_ARM_KVM_ARMV8_CPU_HH__ 412665Ssaidi@eecs.umich.edu#define __ARCH_ARM_KVM_ARMV8_CPU_HH__ 428713Sandreas.hansson@arm.com 432568SN/A#include <vector> 442568SN/A 452568SN/A#include "arch/arm/intregs.hh" 462982Sstever@eecs.umich.edu#include "arch/arm/kvm/base_cpu.hh" 478713Sandreas.hansson@arm.com#include "arch/arm/miscregs.hh" 488713Sandreas.hansson@arm.com 492568SN/Astruct ArmV8KvmCPUParams; 502568SN/A 512568SN/A/** 522568SN/A * This is an implementation of a KVM-based ARMv8-compatible CPU. 532568SN/A * 542568SN/A * Known limitations: 552568SN/A * <ul> 568229Snate@binkert.org * 572568SN/A * <li>The system-register-based generic timer can only be simulated 585386Sstever@gmail.com * by the host kernel. Workaround: Use a memory mapped timer 596215Snate@binkert.org * instead to simulate the timer in gem5. 602568SN/A * 612568SN/A * <li>Simulating devices (e.g., the generic timer) in the host 622568SN/A * kernel requires that the host kernel also simulates the 634762Snate@binkert.org * GIC. 642568SN/A * 652568SN/A * <li>ID registers in the host and in gem5 must match for switching 668713Sandreas.hansson@arm.com * between simulated CPUs and KVM. This is particularly 678713Sandreas.hansson@arm.com * important for ID registers describing memory system 688713Sandreas.hansson@arm.com * capabilities (e.g., ASID size, physical address size). 698713Sandreas.hansson@arm.com * 708713Sandreas.hansson@arm.com * <li>Switching between a virtualized CPU and a simulated CPU is 718713Sandreas.hansson@arm.com * currently not supported if in-kernel device emulation is 728713Sandreas.hansson@arm.com * used. This could be worked around by adding support for 738713Sandreas.hansson@arm.com * switching to the gem5 (e.g., the KvmGic) side of the device 748713Sandreas.hansson@arm.com * models. A simpler workaround is to avoid in-kernel device 758713Sandreas.hansson@arm.com * models altogether. 768713Sandreas.hansson@arm.com * 778713Sandreas.hansson@arm.com * </ul> 788713Sandreas.hansson@arm.com * 792568SN/A */ 802568SN/Aclass ArmV8KvmCPU : public BaseArmKvmCPU 812568SN/A{ 828713Sandreas.hansson@arm.com public: 838713Sandreas.hansson@arm.com ArmV8KvmCPU(ArmV8KvmCPUParams *params); 848713Sandreas.hansson@arm.com virtual ~ArmV8KvmCPU(); 858713Sandreas.hansson@arm.com 868713Sandreas.hansson@arm.com void dump() M5_ATTR_OVERRIDE; 878713Sandreas.hansson@arm.com 888713Sandreas.hansson@arm.com protected: 898713Sandreas.hansson@arm.com void updateKvmState() M5_ATTR_OVERRIDE; 908713Sandreas.hansson@arm.com void updateThreadContext() M5_ATTR_OVERRIDE; 918713Sandreas.hansson@arm.com 928713Sandreas.hansson@arm.com protected: 938713Sandreas.hansson@arm.com /** Mapping between integer registers in gem5 and KVM */ 948713Sandreas.hansson@arm.com struct IntRegInfo { 958713Sandreas.hansson@arm.com IntRegInfo(uint64_t _kvm, IntRegIndex _idx, const char *_name) 968713Sandreas.hansson@arm.com : kvm(_kvm), idx(_idx), name(_name) {} 978713Sandreas.hansson@arm.com 988713Sandreas.hansson@arm.com /** Register index in KVM */ 998713Sandreas.hansson@arm.com uint64_t kvm; 1008713Sandreas.hansson@arm.com /** Register index in gem5 */ 1018713Sandreas.hansson@arm.com IntRegIndex idx; 1028713Sandreas.hansson@arm.com /** Name to use in debug dumps */ 1038713Sandreas.hansson@arm.com const char *name; 1048713Sandreas.hansson@arm.com }; 1058713Sandreas.hansson@arm.com 1068713Sandreas.hansson@arm.com /** Mapping between misc registers in gem5 and registers in KVM */ 1078713Sandreas.hansson@arm.com struct MiscRegInfo { 1088713Sandreas.hansson@arm.com MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name) 1098713Sandreas.hansson@arm.com : kvm(_kvm), idx(_idx), name(_name) {} 1108713Sandreas.hansson@arm.com 1118713Sandreas.hansson@arm.com /** Register index in KVM */ 1128713Sandreas.hansson@arm.com uint64_t kvm; 1138713Sandreas.hansson@arm.com /** Register index in gem5 */ 1148713Sandreas.hansson@arm.com MiscRegIndex idx; 1158713Sandreas.hansson@arm.com /** Name to use in debug dumps */ 1168713Sandreas.hansson@arm.com const char *name; 1178713Sandreas.hansson@arm.com }; 1188713Sandreas.hansson@arm.com 1198713Sandreas.hansson@arm.com /** 1208713Sandreas.hansson@arm.com * Get a map between system registers in kvm and gem5 registers 1218713Sandreas.hansson@arm.com * 1228713Sandreas.hansson@arm.com * This method returns a mapping between system registers in kvm 1238713Sandreas.hansson@arm.com * and misc regs in gem5. The actual mapping is only created the 1248713Sandreas.hansson@arm.com * first time the method is called and stored in a cache 1258713Sandreas.hansson@arm.com * (ArmV8KvmCPU::sysRegMap). 1262568SN/A * 1278713Sandreas.hansson@arm.com * @return Vector of kvm<->misc reg mappings. 1288713Sandreas.hansson@arm.com */ 1298713Sandreas.hansson@arm.com const std::vector<ArmV8KvmCPU::MiscRegInfo> &getSysRegMap() const; 1302643Sstever@eecs.umich.edu 1312568SN/A /** Mapping between gem5 integer registers and integer registers in kvm */ 1322568SN/A static const std::vector<ArmV8KvmCPU::IntRegInfo> intRegMap; 1332643Sstever@eecs.umich.edu /** Mapping between gem5 misc registers registers and registers in kvm */ 1348713Sandreas.hansson@arm.com static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegMap; 1352643Sstever@eecs.umich.edu 1362643Sstever@eecs.umich.edu /** Cached mapping between system registers in kvm and misc regs in gem5 */ 1378713Sandreas.hansson@arm.com mutable std::vector<ArmV8KvmCPU::MiscRegInfo> sysRegMap; 1388713Sandreas.hansson@arm.com}; 1398713Sandreas.hansson@arm.com 1408713Sandreas.hansson@arm.com#endif // __ARCH_ARM_KVM_ARMV8_CPU_HH__ 1418713Sandreas.hansson@arm.com