armv8_cpu.hh revision 11178
110860Sandreas.sandberg@arm.com/* 210860Sandreas.sandberg@arm.com * Copyright (c) 2015 ARM Limited 310860Sandreas.sandberg@arm.com * All rights reserved 410860Sandreas.sandberg@arm.com * 510860Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 610860Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 710860Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 810860Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 910860Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1010860Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1110860Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1210860Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1310860Sandreas.sandberg@arm.com * 1410860Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1510860Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 1610860Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 1710860Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 1810860Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1910860Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2010860Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2110860Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2210860Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2310860Sandreas.sandberg@arm.com * this software without specific prior written permission. 2410860Sandreas.sandberg@arm.com * 2510860Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610860Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710860Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810860Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910860Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010860Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110860Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210860Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310860Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410860Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510860Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610860Sandreas.sandberg@arm.com * 3710860Sandreas.sandberg@arm.com * Authors: Andreas Sandberg 3810860Sandreas.sandberg@arm.com */ 3910860Sandreas.sandberg@arm.com 4010860Sandreas.sandberg@arm.com#ifndef __ARCH_ARM_KVM_ARMV8_CPU_HH__ 4110860Sandreas.sandberg@arm.com#define __ARCH_ARM_KVM_ARMV8_CPU_HH__ 4210860Sandreas.sandberg@arm.com 4310860Sandreas.sandberg@arm.com#include <vector> 4410860Sandreas.sandberg@arm.com 4510860Sandreas.sandberg@arm.com#include "arch/arm/intregs.hh" 4610860Sandreas.sandberg@arm.com#include "arch/arm/kvm/base_cpu.hh" 4710860Sandreas.sandberg@arm.com#include "arch/arm/miscregs.hh" 4810860Sandreas.sandberg@arm.com 4910860Sandreas.sandberg@arm.comstruct ArmV8KvmCPUParams; 5010860Sandreas.sandberg@arm.com 5110860Sandreas.sandberg@arm.com/** 5210860Sandreas.sandberg@arm.com * This is an implementation of a KVM-based ARMv8-compatible CPU. 5310860Sandreas.sandberg@arm.com * 5410860Sandreas.sandberg@arm.com * Known limitations: 5510860Sandreas.sandberg@arm.com * <ul> 5610860Sandreas.sandberg@arm.com * 5710860Sandreas.sandberg@arm.com * <li>The system-register-based generic timer can only be simulated 5810860Sandreas.sandberg@arm.com * by the host kernel. Workaround: Use a memory mapped timer 5910860Sandreas.sandberg@arm.com * instead to simulate the timer in gem5. 6010860Sandreas.sandberg@arm.com * 6110860Sandreas.sandberg@arm.com * <li>Simulating devices (e.g., the generic timer) in the host 6210860Sandreas.sandberg@arm.com * kernel requires that the host kernel also simulates the 6310860Sandreas.sandberg@arm.com * GIC. 6410860Sandreas.sandberg@arm.com * 6510860Sandreas.sandberg@arm.com * <li>ID registers in the host and in gem5 must match for switching 6610860Sandreas.sandberg@arm.com * between simulated CPUs and KVM. This is particularly 6710860Sandreas.sandberg@arm.com * important for ID registers describing memory system 6810860Sandreas.sandberg@arm.com * capabilities (e.g., ASID size, physical address size). 6910860Sandreas.sandberg@arm.com * 7010860Sandreas.sandberg@arm.com * <li>Switching between a virtualized CPU and a simulated CPU is 7110860Sandreas.sandberg@arm.com * currently not supported if in-kernel device emulation is 7210860Sandreas.sandberg@arm.com * used. This could be worked around by adding support for 7310860Sandreas.sandberg@arm.com * switching to the gem5 (e.g., the KvmGic) side of the device 7410860Sandreas.sandberg@arm.com * models. A simpler workaround is to avoid in-kernel device 7510860Sandreas.sandberg@arm.com * models altogether. 7610860Sandreas.sandberg@arm.com * 7710860Sandreas.sandberg@arm.com * </ul> 7810860Sandreas.sandberg@arm.com * 7910860Sandreas.sandberg@arm.com */ 8010860Sandreas.sandberg@arm.comclass ArmV8KvmCPU : public BaseArmKvmCPU 8110860Sandreas.sandberg@arm.com{ 8210860Sandreas.sandberg@arm.com public: 8310860Sandreas.sandberg@arm.com ArmV8KvmCPU(ArmV8KvmCPUParams *params); 8410860Sandreas.sandberg@arm.com virtual ~ArmV8KvmCPU(); 8510860Sandreas.sandberg@arm.com 8611178Svictor.garcia@arm.com void dump() const override; 8710860Sandreas.sandberg@arm.com 8810860Sandreas.sandberg@arm.com protected: 8911168Sandreas.hansson@arm.com void updateKvmState() override; 9011168Sandreas.hansson@arm.com void updateThreadContext() override; 9110860Sandreas.sandberg@arm.com 9210860Sandreas.sandberg@arm.com protected: 9310860Sandreas.sandberg@arm.com /** Mapping between integer registers in gem5 and KVM */ 9410860Sandreas.sandberg@arm.com struct IntRegInfo { 9510860Sandreas.sandberg@arm.com IntRegInfo(uint64_t _kvm, IntRegIndex _idx, const char *_name) 9610860Sandreas.sandberg@arm.com : kvm(_kvm), idx(_idx), name(_name) {} 9710860Sandreas.sandberg@arm.com 9810860Sandreas.sandberg@arm.com /** Register index in KVM */ 9910860Sandreas.sandberg@arm.com uint64_t kvm; 10010860Sandreas.sandberg@arm.com /** Register index in gem5 */ 10110860Sandreas.sandberg@arm.com IntRegIndex idx; 10210860Sandreas.sandberg@arm.com /** Name to use in debug dumps */ 10310860Sandreas.sandberg@arm.com const char *name; 10410860Sandreas.sandberg@arm.com }; 10510860Sandreas.sandberg@arm.com 10610860Sandreas.sandberg@arm.com /** Mapping between misc registers in gem5 and registers in KVM */ 10710860Sandreas.sandberg@arm.com struct MiscRegInfo { 10810860Sandreas.sandberg@arm.com MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name) 10910860Sandreas.sandberg@arm.com : kvm(_kvm), idx(_idx), name(_name) {} 11010860Sandreas.sandberg@arm.com 11110860Sandreas.sandberg@arm.com /** Register index in KVM */ 11210860Sandreas.sandberg@arm.com uint64_t kvm; 11310860Sandreas.sandberg@arm.com /** Register index in gem5 */ 11410860Sandreas.sandberg@arm.com MiscRegIndex idx; 11510860Sandreas.sandberg@arm.com /** Name to use in debug dumps */ 11610860Sandreas.sandberg@arm.com const char *name; 11710860Sandreas.sandberg@arm.com }; 11810860Sandreas.sandberg@arm.com 11910860Sandreas.sandberg@arm.com /** 12010860Sandreas.sandberg@arm.com * Get a map between system registers in kvm and gem5 registers 12110860Sandreas.sandberg@arm.com * 12210860Sandreas.sandberg@arm.com * This method returns a mapping between system registers in kvm 12310860Sandreas.sandberg@arm.com * and misc regs in gem5. The actual mapping is only created the 12410860Sandreas.sandberg@arm.com * first time the method is called and stored in a cache 12510860Sandreas.sandberg@arm.com * (ArmV8KvmCPU::sysRegMap). 12610860Sandreas.sandberg@arm.com * 12710860Sandreas.sandberg@arm.com * @return Vector of kvm<->misc reg mappings. 12810860Sandreas.sandberg@arm.com */ 12910860Sandreas.sandberg@arm.com const std::vector<ArmV8KvmCPU::MiscRegInfo> &getSysRegMap() const; 13010860Sandreas.sandberg@arm.com 13110860Sandreas.sandberg@arm.com /** Mapping between gem5 integer registers and integer registers in kvm */ 13210860Sandreas.sandberg@arm.com static const std::vector<ArmV8KvmCPU::IntRegInfo> intRegMap; 13310860Sandreas.sandberg@arm.com /** Mapping between gem5 misc registers registers and registers in kvm */ 13410860Sandreas.sandberg@arm.com static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegMap; 13510860Sandreas.sandberg@arm.com 13610860Sandreas.sandberg@arm.com /** Cached mapping between system registers in kvm and misc regs in gem5 */ 13710860Sandreas.sandberg@arm.com mutable std::vector<ArmV8KvmCPU::MiscRegInfo> sysRegMap; 13810860Sandreas.sandberg@arm.com}; 13910860Sandreas.sandberg@arm.com 14010860Sandreas.sandberg@arm.com#endif // __ARCH_ARM_KVM_ARMV8_CPU_HH__ 141