armv8_cpu.cc revision 11178
17138Sgblack@eecs.umich.edu/* 27138Sgblack@eecs.umich.edu * Copyright (c) 2015 ARM Limited 310037SARM gem5 Developers * All rights reserved 47138Sgblack@eecs.umich.edu * 57138Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67138Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77138Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87138Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97138Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107138Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117138Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127138Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137138Sgblack@eecs.umich.edu * 147138Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 157138Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 167138Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 177138Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 187138Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 197138Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 207138Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 217138Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 227138Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237138Sgblack@eecs.umich.edu * this software without specific prior written permission. 247138Sgblack@eecs.umich.edu * 257138Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267138Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277138Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287138Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297138Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307138Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317138Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327138Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337138Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347138Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357138Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367138Sgblack@eecs.umich.edu * 377138Sgblack@eecs.umich.edu * Authors: Andreas Sandberg 387138Sgblack@eecs.umich.edu */ 397138Sgblack@eecs.umich.edu 407138Sgblack@eecs.umich.edu#include "arch/arm/kvm/armv8_cpu.hh" 417138Sgblack@eecs.umich.edu 427138Sgblack@eecs.umich.edu#include <linux/kvm.h> 437138Sgblack@eecs.umich.edu 447138Sgblack@eecs.umich.edu#include "debug/KvmContext.hh" 457138Sgblack@eecs.umich.edu#include "params/ArmV8KvmCPU.hh" 467214Sgblack@eecs.umich.edu 478303SAli.Saidi@ARM.com// Unlike gem5, kvm doesn't count the SP as a normal integer register, 487214Sgblack@eecs.umich.edu// which means we only have 31 normal integer registers. 497214Sgblack@eecs.umich.educonstexpr static unsigned NUM_XREGS = NUM_ARCH_INTREGS - 1; 507138Sgblack@eecs.umich.edustatic_assert(NUM_XREGS == 31, "Unexpected number of aarch64 int. regs."); 518302SAli.Saidi@ARM.com 527138Sgblack@eecs.umich.edu// The KVM interface accesses vector registers of 4 single precision 537138Sgblack@eecs.umich.edu// floats instead of individual registers. 548305SAli.Saidi@ARM.comconstexpr static unsigned NUM_QREGS = NumFloatV8ArchRegs / 4; 558305SAli.Saidi@ARM.comstatic_assert(NUM_QREGS == 32, "Unexpected number of aarch64 vector regs."); 568305SAli.Saidi@ARM.com 578305SAli.Saidi@ARM.com#define EXTRACT_FIELD(v, name) \ 588305SAli.Saidi@ARM.com (((v) & name ## _MASK) >> name ## _SHIFT) 598305SAli.Saidi@ARM.com 608305SAli.Saidi@ARM.com#define CORE_REG(name, size) \ 618305SAli.Saidi@ARM.com (KVM_REG_ARM64 | KVM_REG_ARM_CORE | \ 628305SAli.Saidi@ARM.com KVM_REG_SIZE_ ## size | \ 638305SAli.Saidi@ARM.com KVM_REG_ARM_CORE_REG(name)) 648305SAli.Saidi@ARM.com 658305SAli.Saidi@ARM.com#define INT_REG(name) CORE_REG(name, U64) 668305SAli.Saidi@ARM.com#define SIMD_REG(name) CORE_REG(name, U128) 678305SAli.Saidi@ARM.com 688305SAli.Saidi@ARM.comconstexpr uint64_t 698305SAli.Saidi@ARM.comkvmXReg(const int num) 708305SAli.Saidi@ARM.com{ 718305SAli.Saidi@ARM.com return INT_REG(regs.regs[0]) + 728305SAli.Saidi@ARM.com (INT_REG(regs.regs[1]) - INT_REG(regs.regs[0])) * num; 738305SAli.Saidi@ARM.com} 748305SAli.Saidi@ARM.com 758305SAli.Saidi@ARM.comconstexpr uint64_t 768305SAli.Saidi@ARM.comkvmFPReg(const int num) 778305SAli.Saidi@ARM.com{ 787138Sgblack@eecs.umich.edu return SIMD_REG(fp_regs.vregs[0]) + 797138Sgblack@eecs.umich.edu (SIMD_REG(fp_regs.vregs[1]) - SIMD_REG(fp_regs.vregs[0])) * num; 808303SAli.Saidi@ARM.com} 817138Sgblack@eecs.umich.edu 828305SAli.Saidi@ARM.comunion KvmFPReg { 838305SAli.Saidi@ARM.com union { 847193Sgblack@eecs.umich.edu uint32_t i; 857138Sgblack@eecs.umich.edu float f; 867215Sgblack@eecs.umich.edu } s[4]; 877138Sgblack@eecs.umich.edu 887138Sgblack@eecs.umich.edu union { 897138Sgblack@eecs.umich.edu uint64_t i; 907138Sgblack@eecs.umich.edu double f; 917138Sgblack@eecs.umich.edu } d[2]; 927138Sgblack@eecs.umich.edu 937138Sgblack@eecs.umich.edu uint8_t data[32]; 947138Sgblack@eecs.umich.edu}; 957138Sgblack@eecs.umich.edu 967138Sgblack@eecs.umich.edu#define FP_REGS_PER_VFP_REG 4 977138Sgblack@eecs.umich.edustatic_assert(sizeof(FloatRegBits) == 4, "Unexpected float reg size"); 987138Sgblack@eecs.umich.edu 997138Sgblack@eecs.umich.educonst std::vector<ArmV8KvmCPU::IntRegInfo> ArmV8KvmCPU::intRegMap = { 1007138Sgblack@eecs.umich.edu { INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" }, 1017138Sgblack@eecs.umich.edu { INT_REG(sp_el1), INTREG_SP1, "SP(EL1)" }, 1028305SAli.Saidi@ARM.com}; 1038305SAli.Saidi@ARM.com 1047193Sgblack@eecs.umich.educonst std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegMap = { 1057138Sgblack@eecs.umich.edu MiscRegInfo(INT_REG(regs.pstate), MISCREG_CPSR, "PSTATE"), 1067215Sgblack@eecs.umich.edu MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"), 1077138Sgblack@eecs.umich.edu MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]), MISCREG_SPSR_EL1, "SPSR(EL1)"), 1087138Sgblack@eecs.umich.edu MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]), MISCREG_SPSR_ABT, "SPSR(ABT)"), 1097138Sgblack@eecs.umich.edu MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"), 1108305SAli.Saidi@ARM.com MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"), 1117138Sgblack@eecs.umich.edu MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"), 1127138Sgblack@eecs.umich.edu MiscRegInfo(INT_REG(fp_regs.fpsr), MISCREG_FPSR, "FPSR"), 1137138Sgblack@eecs.umich.edu MiscRegInfo(INT_REG(fp_regs.fpcr), MISCREG_FPCR, "FPCR"), 1147138Sgblack@eecs.umich.edu}; 1158304SAli.Saidi@ARM.com 1168304SAli.Saidi@ARM.comArmV8KvmCPU::ArmV8KvmCPU(ArmV8KvmCPUParams *params) 1177138Sgblack@eecs.umich.edu : BaseArmKvmCPU(params) 1187193Sgblack@eecs.umich.edu{ 1199250SAli.Saidi@ARM.com} 1209250SAli.Saidi@ARM.com 1217138Sgblack@eecs.umich.eduArmV8KvmCPU::~ArmV8KvmCPU() 1227138Sgblack@eecs.umich.edu{ 1237138Sgblack@eecs.umich.edu} 1247138Sgblack@eecs.umich.edu 1257138Sgblack@eecs.umich.eduvoid 1267193Sgblack@eecs.umich.eduArmV8KvmCPU::dump() const 1277184Sgblack@eecs.umich.edu{ 1287214Sgblack@eecs.umich.edu inform("Integer registers:\n"); 1297214Sgblack@eecs.umich.edu inform(" PC: %s\n", getAndFormatOneReg(INT_REG(regs.pc))); 1307138Sgblack@eecs.umich.edu for (int i = 0; i < NUM_XREGS; ++i) 1318305SAli.Saidi@ARM.com inform(" X%i: %s\n", i, getAndFormatOneReg(kvmXReg(i))); 1328305SAli.Saidi@ARM.com 1338305SAli.Saidi@ARM.com for (int i = 0; i < NUM_QREGS; ++i) 1347184Sgblack@eecs.umich.edu inform(" Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i))); 1357188Sgblack@eecs.umich.edu 1368304SAli.Saidi@ARM.com for (const auto &ri : intRegMap) 1379250SAli.Saidi@ARM.com inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm)); 1388304SAli.Saidi@ARM.com 1397188Sgblack@eecs.umich.edu for (const auto &ri : miscRegMap) 1408304SAli.Saidi@ARM.com inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm)); 1418304SAli.Saidi@ARM.com 1429250SAli.Saidi@ARM.com for (const auto ® : getRegList()) { 1438304SAli.Saidi@ARM.com const uint64_t arch(reg & KVM_REG_ARCH_MASK); 1447184Sgblack@eecs.umich.edu if (arch != KVM_REG_ARM64) { 1457188Sgblack@eecs.umich.edu inform("0x%x: %s\n", reg, getAndFormatOneReg(reg)); 1467188Sgblack@eecs.umich.edu continue; 1477188Sgblack@eecs.umich.edu } 1487188Sgblack@eecs.umich.edu 1497188Sgblack@eecs.umich.edu const uint64_t type(reg & KVM_REG_ARM_COPROC_MASK); 1507188Sgblack@eecs.umich.edu switch (type) { 1517193Sgblack@eecs.umich.edu case KVM_REG_ARM_CORE: 1527193Sgblack@eecs.umich.edu // These have already been printed 1537188Sgblack@eecs.umich.edu break; 1547188Sgblack@eecs.umich.edu 1557188Sgblack@eecs.umich.edu case KVM_REG_ARM64_SYSREG: { 1567193Sgblack@eecs.umich.edu const uint64_t op0(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP0)); 1578203SAli.Saidi@ARM.com const uint64_t op1(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP1)); 1588203SAli.Saidi@ARM.com const uint64_t crn(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRN)); 1597184Sgblack@eecs.umich.edu const uint64_t crm(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRM)); 1607184Sgblack@eecs.umich.edu const uint64_t op2(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP2)); 1617184Sgblack@eecs.umich.edu const MiscRegIndex idx( 1628305SAli.Saidi@ARM.com decodeAArch64SysReg(op0, op1, crn, crm, op2)); 1637184Sgblack@eecs.umich.edu 1647184Sgblack@eecs.umich.edu inform(" %s (op0: %i, op1: %i, crn: %i, crm: %i, op2: %i): %s", 1657193Sgblack@eecs.umich.edu miscRegName[idx], op0, op1, crn, crm, op2, 1667184Sgblack@eecs.umich.edu getAndFormatOneReg(reg)); 1677214Sgblack@eecs.umich.edu } break; 1687215Sgblack@eecs.umich.edu 1697184Sgblack@eecs.umich.edu case KVM_REG_ARM_DEMUX: { 1708305SAli.Saidi@ARM.com const uint64_t id(EXTRACT_FIELD(reg, KVM_REG_ARM_DEMUX_ID)); 1718305SAli.Saidi@ARM.com const uint64_t val(EXTRACT_FIELD(reg, KVM_REG_ARM_DEMUX_VAL)); 1728305SAli.Saidi@ARM.com if (id == KVM_REG_ARM_DEMUX_ID_CCSIDR) { 1737184Sgblack@eecs.umich.edu inform(" CSSIDR[%i]: %s\n", val, 1748305SAli.Saidi@ARM.com getAndFormatOneReg(reg)); 1758305SAli.Saidi@ARM.com } else { 1768305SAli.Saidi@ARM.com inform(" UNKNOWN[%i:%i]: %s\n", id, val, 1778305SAli.Saidi@ARM.com getAndFormatOneReg(reg)); 1788305SAli.Saidi@ARM.com } 1798305SAli.Saidi@ARM.com } break; 1807188Sgblack@eecs.umich.edu 1818304SAli.Saidi@ARM.com default: 1828304SAli.Saidi@ARM.com inform("0x%x: %s\n", reg, getAndFormatOneReg(reg)); 1838304SAli.Saidi@ARM.com } 1847188Sgblack@eecs.umich.edu } 1858304SAli.Saidi@ARM.com} 1868304SAli.Saidi@ARM.com 1878304SAli.Saidi@ARM.comvoid 1888304SAli.Saidi@ARM.comArmV8KvmCPU::updateKvmState() 1898304SAli.Saidi@ARM.com{ 1907184Sgblack@eecs.umich.edu DPRINTF(KvmContext, "In updateKvmState():\n"); 1917188Sgblack@eecs.umich.edu for (const auto &ri : miscRegMap) { 1927188Sgblack@eecs.umich.edu const uint64_t value(tc->readMiscReg(ri.idx)); 1937188Sgblack@eecs.umich.edu DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value); 1947188Sgblack@eecs.umich.edu setOneReg(ri.kvm, value); 1957188Sgblack@eecs.umich.edu } 1967188Sgblack@eecs.umich.edu 1977193Sgblack@eecs.umich.edu for (int i = 0; i < NUM_XREGS; ++i) { 1987193Sgblack@eecs.umich.edu const uint64_t value(tc->readIntReg(INTREG_X0 + i)); 1997188Sgblack@eecs.umich.edu DPRINTF(KvmContext, " X%i := 0x%x\n", i, value); 2007188Sgblack@eecs.umich.edu setOneReg(kvmXReg(i), value); 2017188Sgblack@eecs.umich.edu } 2027188Sgblack@eecs.umich.edu 2037193Sgblack@eecs.umich.edu for (const auto &ri : intRegMap) { 2047193Sgblack@eecs.umich.edu const uint64_t value(tc->readIntReg(ri.idx)); 2057184Sgblack@eecs.umich.edu DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value); 2067184Sgblack@eecs.umich.edu setOneReg(ri.kvm, value); 2077184Sgblack@eecs.umich.edu } 2087184Sgblack@eecs.umich.edu 2097184Sgblack@eecs.umich.edu for (int i = 0; i < NUM_QREGS; ++i) { 2107193Sgblack@eecs.umich.edu const RegIndex reg_base(i * FP_REGS_PER_VFP_REG); 2117184Sgblack@eecs.umich.edu KvmFPReg reg; 2127214Sgblack@eecs.umich.edu for (int j = 0; j < FP_REGS_PER_VFP_REG; j++) 2137215Sgblack@eecs.umich.edu reg.s[j].i = tc->readFloatRegBits(reg_base + j); 2147184Sgblack@eecs.umich.edu 2158305SAli.Saidi@ARM.com setOneReg(kvmFPReg(i), reg.data); 2168305SAli.Saidi@ARM.com DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i))); 2178305SAli.Saidi@ARM.com } 2188305SAli.Saidi@ARM.com 2197138Sgblack@eecs.umich.edu for (const auto &ri : getSysRegMap()) { 2207188Sgblack@eecs.umich.edu const uint64_t value(tc->readMiscReg(ri.idx)); 2218304SAli.Saidi@ARM.com DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value); 2228304SAli.Saidi@ARM.com setOneReg(ri.kvm, value); 2238304SAli.Saidi@ARM.com } 2247138Sgblack@eecs.umich.edu 2258304SAli.Saidi@ARM.com setOneReg(INT_REG(regs.pc), tc->instAddr()); 2268304SAli.Saidi@ARM.com DPRINTF(KvmContext, " PC := 0x%x\n", tc->instAddr()); 2278304SAli.Saidi@ARM.com} 2288304SAli.Saidi@ARM.com 2297138Sgblack@eecs.umich.eduvoid 2307188Sgblack@eecs.umich.eduArmV8KvmCPU::updateThreadContext() 2317188Sgblack@eecs.umich.edu{ 2327188Sgblack@eecs.umich.edu DPRINTF(KvmContext, "In updateThreadContext():\n"); 2337188Sgblack@eecs.umich.edu 2347188Sgblack@eecs.umich.edu // Update core misc regs first as they (particularly PSTATE/CPSR) 2357184Sgblack@eecs.umich.edu // affect how other registers are mapped. 2367193Sgblack@eecs.umich.edu for (const auto &ri : miscRegMap) { 2377193Sgblack@eecs.umich.edu const auto value(getOneRegU64(ri.kvm)); 2387188Sgblack@eecs.umich.edu DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value); 2397188Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(ri.idx, value); 2407188Sgblack@eecs.umich.edu } 2417188Sgblack@eecs.umich.edu 2427188Sgblack@eecs.umich.edu for (int i = 0; i < NUM_XREGS; ++i) { 2438203SAli.Saidi@ARM.com const auto value(getOneRegU64(kvmXReg(i))); 2447188Sgblack@eecs.umich.edu DPRINTF(KvmContext, " X%i := 0x%x\n", i, value); 2457188Sgblack@eecs.umich.edu tc->setIntReg(INTREG_X0 + i, value); 2467188Sgblack@eecs.umich.edu } 2477188Sgblack@eecs.umich.edu 2487188Sgblack@eecs.umich.edu for (const auto &ri : intRegMap) { 2497188Sgblack@eecs.umich.edu const auto value(getOneRegU64(ri.kvm)); 2509250SAli.Saidi@ARM.com DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value); 2518203SAli.Saidi@ARM.com tc->setIntReg(ri.idx, value); 2528203SAli.Saidi@ARM.com } 2537188Sgblack@eecs.umich.edu 2547188Sgblack@eecs.umich.edu for (int i = 0; i < NUM_QREGS; ++i) { 2557188Sgblack@eecs.umich.edu const RegIndex reg_base(i * FP_REGS_PER_VFP_REG); 2567400SAli.Saidi@ARM.com KvmFPReg reg; 2578303SAli.Saidi@ARM.com DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i))); 2588303SAli.Saidi@ARM.com getOneReg(kvmFPReg(i), reg.data); 2598303SAli.Saidi@ARM.com for (int j = 0; j < FP_REGS_PER_VFP_REG; j++) 26010037SARM gem5 Developers tc->setFloatRegBits(reg_base + j, reg.s[j].i); 26110037SARM gem5 Developers } 2628303SAli.Saidi@ARM.com 2638303SAli.Saidi@ARM.com for (const auto &ri : getSysRegMap()) { 2648303SAli.Saidi@ARM.com const auto value(getOneRegU64(ri.kvm)); 2658303SAli.Saidi@ARM.com DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value); 2668303SAli.Saidi@ARM.com tc->setMiscRegNoEffect(ri.idx, value); 2678303SAli.Saidi@ARM.com } 2688303SAli.Saidi@ARM.com 2698303SAli.Saidi@ARM.com const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR)); 2708303SAli.Saidi@ARM.com PCState pc(getOneRegU64(INT_REG(regs.pc))); 2718303SAli.Saidi@ARM.com pc.aarch64(inAArch64(tc)); 2728285SPrakash.Ramrakhyani@arm.com pc.thumb(cpsr.t); 2737188Sgblack@eecs.umich.edu pc.nextAArch64(inAArch64(tc)); 2747188Sgblack@eecs.umich.edu // TODO: This is a massive assumption that will break when 2757648SAli.Saidi@ARM.com // switching to thumb. 2767648SAli.Saidi@ARM.com pc.nextThumb(cpsr.t); 2777188Sgblack@eecs.umich.edu DPRINTF(KvmContext, " PC := 0x%x (t: %i, a64: %i)\n", 2787648SAli.Saidi@ARM.com pc.instAddr(), pc.thumb(), pc.aarch64()); 2797648SAli.Saidi@ARM.com tc->pcState(pc); 2807188Sgblack@eecs.umich.edu} 2817188Sgblack@eecs.umich.edu 2827188Sgblack@eecs.umich.educonst std::vector<ArmV8KvmCPU::MiscRegInfo> & 2839250SAli.Saidi@ARM.comArmV8KvmCPU::getSysRegMap() const 2849250SAli.Saidi@ARM.com{ 2857188Sgblack@eecs.umich.edu // Try to use the cached map 2869250SAli.Saidi@ARM.com if (!sysRegMap.empty()) 2879250SAli.Saidi@ARM.com return sysRegMap; 2887185Sgblack@eecs.umich.edu 2897797Sgblack@eecs.umich.edu for (const auto ® : getRegList()) { 2907185Sgblack@eecs.umich.edu const uint64_t arch(reg & KVM_REG_ARCH_MASK); 2919250SAli.Saidi@ARM.com if (arch != KVM_REG_ARM64) 2927188Sgblack@eecs.umich.edu continue; 2937188Sgblack@eecs.umich.edu 2947188Sgblack@eecs.umich.edu const uint64_t type(reg & KVM_REG_ARM_COPROC_MASK); 2957188Sgblack@eecs.umich.edu if (type != KVM_REG_ARM64_SYSREG) 2967188Sgblack@eecs.umich.edu continue; 2977188Sgblack@eecs.umich.edu 2987188Sgblack@eecs.umich.edu const uint64_t op0(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP0)); 2997188Sgblack@eecs.umich.edu const uint64_t op1(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP1)); 3007188Sgblack@eecs.umich.edu const uint64_t crn(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRN)); 3018203SAli.Saidi@ARM.com const uint64_t crm(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_CRM)); 3029077SAli.Saidi@ARM.com const uint64_t op2(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP2)); 3037188Sgblack@eecs.umich.edu const MiscRegIndex idx(decodeAArch64SysReg(op0, op1, crn, crm, op2)); 3047188Sgblack@eecs.umich.edu const auto &info(miscRegInfo[idx]); 3057156Sgblack@eecs.umich.edu const bool writeable( 3067188Sgblack@eecs.umich.edu info[MISCREG_USR_NS_WR] || info[MISCREG_USR_S_WR] || 3077188Sgblack@eecs.umich.edu info[MISCREG_PRI_S_WR] || info[MISCREG_PRI_NS_WR] || 3087193Sgblack@eecs.umich.edu info[MISCREG_HYP_WR] || 3097193Sgblack@eecs.umich.edu info[MISCREG_MON_NS0_WR] || info[MISCREG_MON_NS1_WR]); 3107193Sgblack@eecs.umich.edu const bool implemented( 3118588Sgblack@eecs.umich.edu info[MISCREG_IMPLEMENTED] || info[MISCREG_WARN_NOT_FAIL]); 3127193Sgblack@eecs.umich.edu 3137193Sgblack@eecs.umich.edu // Only add implemented registers that we are going to be able 3147193Sgblack@eecs.umich.edu // to write. 3157193Sgblack@eecs.umich.edu if (implemented && writeable) 3167193Sgblack@eecs.umich.edu sysRegMap.emplace_back(reg, idx, miscRegName[idx]); 3177193Sgblack@eecs.umich.edu } 3187193Sgblack@eecs.umich.edu 3198588Sgblack@eecs.umich.edu return sysRegMap; 3208588Sgblack@eecs.umich.edu} 3217193Sgblack@eecs.umich.edu 3227193Sgblack@eecs.umich.eduArmV8KvmCPU * 3237193Sgblack@eecs.umich.eduArmV8KvmCPUParams::create() 3247193Sgblack@eecs.umich.edu{ 3257193Sgblack@eecs.umich.edu return new ArmV8KvmCPU(this); 3267193Sgblack@eecs.umich.edu} 3277193Sgblack@eecs.umich.edu