arm_cpu.hh revision 9657
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Sandberg 38 */ 39 40#ifndef __CPU_KVM_ARM_CPU_HH__ 41#define __CPU_KVM_ARM_CPU_HH__ 42 43#include <set> 44#include <vector> 45 46#include "cpu/kvm/base.hh" 47#include "params/ArmKvmCPU.hh" 48 49/** 50 * ARM implementation of a KVM-based hardware virtualized CPU. 51 * Architecture specific limitations: 52 * * LPAE is currently not supported by gem5. We therefore panic if LPAE 53 * is enabled when returning to gem5. 54 * * The co-processor based interface to the architected timer is 55 * unsupported. We can't support this due to limitations in the KVM 56 * API on ARM. 57 * * M5 ops are currently not supported. This requires either a kernel 58 * hack or a memory mapped device that handles the guest<->m5 59 * interface. 60 */ 61class ArmKvmCPU : public BaseKvmCPU 62{ 63 public: 64 ArmKvmCPU(ArmKvmCPUParams *params); 65 virtual ~ArmKvmCPU(); 66 67 void startup(); 68 69 protected: 70 struct KvmIntRegInfo { 71 /** KVM ID */ 72 const uint64_t id; 73 /** gem5 index */ 74 const IntRegIndex idx; 75 /** Name in debug output */ 76 const char *name; 77 }; 78 79 struct KvmCoreMiscRegInfo { 80 /** KVM ID */ 81 const uint64_t id; 82 /** gem5 index */ 83 const MiscRegIndex idx; 84 /** Name in debug output */ 85 const char *name; 86 }; 87 88 typedef std::vector<uint64_t> RegIndexVector; 89 90 void tick(); 91 92 void updateKvmState(); 93 void updateThreadContext(); 94 95 /** 96 * Get a list of registers supported by getOneReg() and setOneReg(). 97 */ 98 const RegIndexVector &getRegList() const; 99 100 void kvmArmVCpuInit(uint32_t target); 101 void kvmArmVCpuInit(const struct kvm_vcpu_init &init); 102 103 ArmISA::MiscRegIndex decodeCoProcReg(uint64_t id) const; 104 105 ArmISA::MiscRegIndex decodeVFPCtrlReg(uint64_t id) const; 106 107 /** 108 * Determine if a register is invariant. 109 * 110 * Some registers must have the same value in both the host and 111 * the guest. Such registers are referred to as "invariant" 112 * registers in KVM. This is a restriction imposed by KVM as 113 * having different values in ID registers (e.g., the cache 114 * identification registers) would confuse the guest kernel. 115 */ 116 bool isInvariantReg(uint64_t id); 117 118 static KvmIntRegInfo kvmIntRegs[]; 119 static KvmCoreMiscRegInfo kvmCoreMiscRegs[]; 120 121 private: 122 /** 123 * Get a list of registers supported by getOneReg() and setOneReg(). 124 * 125 * @return False if the number of elements allocated in the list 126 * is too small to hold the complete register list (the required 127 * value is written into n in this case). True on success. 128 */ 129 bool getRegList(struct kvm_reg_list ®s) const; 130 131 void updateKvmStateCore(); 132 void updateKvmStateMisc(); 133 void updateKvmStateCoProc(uint64_t id, bool show_warnings); 134 void updateKvmStateVFP(uint64_t id, bool show_warnings); 135 136 void updateTCStateCore(); 137 void updateTCStateMisc(); 138 void updateTCStateCoProc(uint64_t id, bool show_warnings); 139 void updateTCStateVFP(uint64_t id, bool show_warnings); 140 141 142 /** Cached state of the IRQ line */ 143 bool irqAsserted; 144 /** Cached state of the FIQ line */ 145 bool fiqAsserted; 146 147 /** 148 * Cached copy of the list of co-processor registers supported by 149 * KVM 150 */ 151 mutable RegIndexVector _regIndexList; 152 153 /** 154 * List of co-processor registers that KVM requires to be 155 * identical on both the host and the guest. KVM does not allow 156 * writes to these registers. 157 */ 158 static const std::set<uint64_t> invariant_regs; 159}; 160 161#endif 162