isa_traits.hh revision 10318:98771a936b61 
1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Gabe Black
42 *          Stephen Hines
43 */
44
45#ifndef __ARCH_ARM_ISA_TRAITS_HH__
46#define __ARCH_ARM_ISA_TRAITS_HH__
47
48#include "arch/arm/types.hh"
49#include "base/types.hh"
50#include "cpu/static_inst_fwd.hh"
51
52namespace LittleEndianGuest {}
53
54namespace ArmISA
55{
56    using namespace LittleEndianGuest;
57
58    StaticInstPtr decodeInst(ExtMachInst);
59
60    // ARM DOES NOT have a delay slot
61    #define ISA_HAS_DELAY_SLOT 0
62
63    const Addr PageShift = 12;
64    const Addr PageBytes = ULL(1) << PageShift;
65    const Addr Page_Mask = ~(PageBytes - 1);
66    const Addr PageOffset = PageBytes - 1;
67
68
69    ////////////////////////////////////////////////////////////////////////
70    //
71    //  Translation stuff
72    //
73
74    const Addr PteShift = 3;
75    const Addr NPtePageShift = PageShift - PteShift;
76    const Addr NPtePage = ULL(1) << NPtePageShift;
77    const Addr PteMask = NPtePage - 1;
78
79    //// All 'Mapped' segments go through the TLB
80    //// All other segments are translated by dropping the MSB, to give
81    //// the corresponding physical address
82    // User Segment - Mapped
83    const Addr USegBase = ULL(0x0);
84    const Addr USegEnd = ULL(0x7FFFFFFF);
85
86    const unsigned VABits = 32;
87    const unsigned PABits = 32; // Is this correct?
88    const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
89    const Addr VAddrUnImplMask = ~VAddrImplMask;
90    inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
91    inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
92    inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
93
94    const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
95
96    // Max. physical address range in bits supported by the architecture
97    const unsigned MaxPhysAddrRange = 48;
98
99    // return a no-op instruction... used for instruction fetch faults
100    const ExtMachInst NoopMachInst = 0x01E320F000ULL;
101
102    const int MachineBytes = 4;
103
104    const uint32_t HighVecs = 0xFFFF0000;
105
106    // Memory accesses cannot be unaligned
107    const bool HasUnalignedMemAcc = true;
108
109    const bool CurThreadInfoImplemented = false;
110    const int CurThreadInfoReg = -1;
111
112    enum InterruptTypes
113    {
114        INT_RST,
115        INT_ABT,
116        INT_IRQ,
117        INT_FIQ,
118        INT_SEV, // Special interrupt for recieving SEV's
119        INT_VIRT_IRQ,
120        INT_VIRT_FIQ,
121        NumInterruptTypes
122    };
123} // namespace ArmISA
124
125using namespace ArmISA;
126
127#endif // __ARCH_ARM_ISA_TRAITS_HH__
128