isa_traits.hh revision 7811
16019Shines@cs.fsu.edu/* 27158Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37158Sgblack@eecs.umich.edu * All rights reserved 47158Sgblack@eecs.umich.edu * 57158Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67158Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77158Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87158Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97158Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107158Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117158Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127158Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137158Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416019Shines@cs.fsu.edu * Authors: Gabe Black 426019Shines@cs.fsu.edu * Stephen Hines 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#ifndef __ARCH_ARM_ISA_TRAITS_HH__ 466019Shines@cs.fsu.edu#define __ARCH_ARM_ISA_TRAITS_HH__ 476019Shines@cs.fsu.edu 486019Shines@cs.fsu.edu#include "arch/arm/types.hh" 496214Snate@binkert.org#include "base/types.hh" 506019Shines@cs.fsu.edu 517811Ssteve.reinhardt@amd.comnamespace LittleEndianGuest {} 526019Shines@cs.fsu.edu 536019Shines@cs.fsu.edu#define TARGET_ARM 546019Shines@cs.fsu.edu 556019Shines@cs.fsu.educlass StaticInstPtr; 566019Shines@cs.fsu.edu 576019Shines@cs.fsu.edunamespace ArmISA 586019Shines@cs.fsu.edu{ 596019Shines@cs.fsu.edu using namespace LittleEndianGuest; 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.edu StaticInstPtr decodeInst(ExtMachInst); 626019Shines@cs.fsu.edu 636019Shines@cs.fsu.edu // ARM DOES NOT have a delay slot 646019Shines@cs.fsu.edu #define ISA_HAS_DELAY_SLOT 0 656019Shines@cs.fsu.edu 666019Shines@cs.fsu.edu const Addr PageShift = 12; 676019Shines@cs.fsu.edu const Addr PageBytes = ULL(1) << PageShift; 686019Shines@cs.fsu.edu const Addr Page_Mask = ~(PageBytes - 1); 696019Shines@cs.fsu.edu const Addr PageOffset = PageBytes - 1; 706019Shines@cs.fsu.edu 716019Shines@cs.fsu.edu 726019Shines@cs.fsu.edu //////////////////////////////////////////////////////////////////////// 736019Shines@cs.fsu.edu // 746019Shines@cs.fsu.edu // Translation stuff 756019Shines@cs.fsu.edu // 766019Shines@cs.fsu.edu 776019Shines@cs.fsu.edu const Addr PteShift = 3; 786019Shines@cs.fsu.edu const Addr NPtePageShift = PageShift - PteShift; 796019Shines@cs.fsu.edu const Addr NPtePage = ULL(1) << NPtePageShift; 806019Shines@cs.fsu.edu const Addr PteMask = NPtePage - 1; 816019Shines@cs.fsu.edu 826019Shines@cs.fsu.edu //// All 'Mapped' segments go through the TLB 836019Shines@cs.fsu.edu //// All other segments are translated by dropping the MSB, to give 846019Shines@cs.fsu.edu //// the corresponding physical address 856019Shines@cs.fsu.edu // User Segment - Mapped 866019Shines@cs.fsu.edu const Addr USegBase = ULL(0x0); 876019Shines@cs.fsu.edu const Addr USegEnd = ULL(0x7FFFFFFF); 886019Shines@cs.fsu.edu 896019Shines@cs.fsu.edu const unsigned VABits = 32; 906019Shines@cs.fsu.edu const unsigned PABits = 32; // Is this correct? 916019Shines@cs.fsu.edu const Addr VAddrImplMask = (ULL(1) << VABits) - 1; 926019Shines@cs.fsu.edu const Addr VAddrUnImplMask = ~VAddrImplMask; 936019Shines@cs.fsu.edu inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 946019Shines@cs.fsu.edu inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } 956019Shines@cs.fsu.edu inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } 966019Shines@cs.fsu.edu 976019Shines@cs.fsu.edu const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 986019Shines@cs.fsu.edu 996019Shines@cs.fsu.edu // return a no-op instruction... used for instruction fetch faults 1006019Shines@cs.fsu.edu const ExtMachInst NoopMachInst = 0x00000000; 1016019Shines@cs.fsu.edu 1027799Sgblack@eecs.umich.edu const int LogVMPageSize = 12; // 4K bytes 1036019Shines@cs.fsu.edu const int VMPageSize = (1 << LogVMPageSize); 1046019Shines@cs.fsu.edu 1057400SAli.Saidi@ARM.com // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali 1066019Shines@cs.fsu.edu const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 1076019Shines@cs.fsu.edu 1086019Shines@cs.fsu.edu const int MachineBytes = 4; 1096019Shines@cs.fsu.edu const int WordBytes = 4; 1106019Shines@cs.fsu.edu const int HalfwordBytes = 2; 1116019Shines@cs.fsu.edu const int ByteBytes = 1; 1126735Sgblack@eecs.umich.edu 1136735Sgblack@eecs.umich.edu const uint32_t HighVecs = 0xFFFF0000; 1146974Stjones1@inf.ed.ac.uk 1156974Stjones1@inf.ed.ac.uk // Memory accesses cannot be unaligned 1167654Sminkyu.jeong@arm.com const bool HasUnalignedMemAcc = true; 1177349SAli.Saidi@ARM.com 1187400SAli.Saidi@ARM.com enum InterruptTypes 1197400SAli.Saidi@ARM.com { 1207400SAli.Saidi@ARM.com INT_RST, 1217400SAli.Saidi@ARM.com INT_ABT, 1227400SAli.Saidi@ARM.com INT_IRQ, 1237400SAli.Saidi@ARM.com INT_FIQ, 1247400SAli.Saidi@ARM.com NumInterruptTypes 1257400SAli.Saidi@ARM.com }; 1267811Ssteve.reinhardt@amd.com} // namespace ArmISA 1276019Shines@cs.fsu.edu 1286019Shines@cs.fsu.eduusing namespace ArmISA; 1296019Shines@cs.fsu.edu 1306019Shines@cs.fsu.edu#endif // __ARCH_ARM_ISA_TRAITS_HH__ 131