110037SARM gem5 Developers// -*- mode:c++ -*- 210037SARM gem5 Developers 310183SCurtis.Dunham@arm.com// Copyright (c) 2012, 2014 ARM Limited 410037SARM gem5 Developers// All rights reserved 510037SARM gem5 Developers// 610037SARM gem5 Developers// The license below extends only to copyright in the software and shall 710037SARM gem5 Developers// not be construed as granting a license to any other intellectual 810037SARM gem5 Developers// property including but not limited to intellectual property relating 910037SARM gem5 Developers// to a hardware implementation of the functionality of the software 1010037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 1110037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1210037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1310037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1410037SARM gem5 Developers// 1510037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1610037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1710037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1910037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 2010037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 2110037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2210037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2310037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2410037SARM gem5 Developers// this software without specific prior written permission. 2510037SARM gem5 Developers// 2610037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2710037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2810037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2910037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3010037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3110037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3210037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3310037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3410037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3510037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3610037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3710037SARM gem5 Developers// 3810037SARM gem5 Developers// Authors: Thomas Grocutt 3910037SARM gem5 Developers 4010037SARM gem5 Developersdef template AA64FpRegRegOpConstructor {{ 4110184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 4210037SARM gem5 Developers IntRegIndex _dest, IntRegIndex _op1, 4310037SARM gem5 Developers VfpMicroMode mode) 4410037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4510037SARM gem5 Developers _dest, _op1, mode) 4610037SARM gem5 Developers { 4710037SARM gem5 Developers %(constructor)s; 4810037SARM gem5 Developers } 4910037SARM gem5 Developers}}; 5010037SARM gem5 Developers 5110037SARM gem5 Developersdef template AA64FpRegImmOpConstructor {{ 5210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 5310037SARM gem5 Developers IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode) 5410037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 5510037SARM gem5 Developers _dest, _imm, mode) 5610037SARM gem5 Developers { 5710037SARM gem5 Developers %(constructor)s; 5810037SARM gem5 Developers } 5910037SARM gem5 Developers}}; 6010037SARM gem5 Developers 6110037SARM gem5 Developersdef template AA64FpRegRegImmOpConstructor {{ 6210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 6310037SARM gem5 Developers IntRegIndex _dest, 6410037SARM gem5 Developers IntRegIndex _op1, 6510037SARM gem5 Developers uint64_t _imm, 6610037SARM gem5 Developers VfpMicroMode mode) 6710037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6810037SARM gem5 Developers _dest, _op1, _imm, mode) 6910037SARM gem5 Developers { 7010037SARM gem5 Developers %(constructor)s; 7110037SARM gem5 Developers } 7210037SARM gem5 Developers}}; 7310037SARM gem5 Developers 7410037SARM gem5 Developersdef template AA64FpRegRegRegOpConstructor {{ 7510184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 7610037SARM gem5 Developers IntRegIndex _dest, 7710037SARM gem5 Developers IntRegIndex _op1, 7810037SARM gem5 Developers IntRegIndex _op2, 7910037SARM gem5 Developers VfpMicroMode mode) 8010037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8110037SARM gem5 Developers _dest, _op1, _op2, mode) 8210037SARM gem5 Developers { 8310037SARM gem5 Developers %(constructor)s; 8410037SARM gem5 Developers } 8510037SARM gem5 Developers}}; 8610037SARM gem5 Developers 8710037SARM gem5 Developersdef template AA64FpRegRegRegRegOpDeclare {{ 8810037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 8910037SARM gem5 Developers{ 9010037SARM gem5 Developers public: 9110037SARM gem5 Developers // Constructor 9210037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 9310037SARM gem5 Developers IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 9410037SARM gem5 Developers IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop); 9512616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 9610037SARM gem5 Developers}; 9710037SARM gem5 Developers}}; 9810037SARM gem5 Developers 9910037SARM gem5 Developersdef template AA64FpRegRegRegRegOpConstructor {{ 10010184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10110037SARM gem5 Developers IntRegIndex _dest, 10210037SARM gem5 Developers IntRegIndex _op1, 10310037SARM gem5 Developers IntRegIndex _op2, 10410037SARM gem5 Developers IntRegIndex _op3, 10510037SARM gem5 Developers VfpMicroMode mode) 10610037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10710037SARM gem5 Developers _dest, _op1, _op2, _op3, mode) 10810037SARM gem5 Developers { 10910037SARM gem5 Developers %(constructor)s; 11010037SARM gem5 Developers } 11110037SARM gem5 Developers}}; 112