vfp.isa revision 7848
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 vfpEnabledCheckCode = ''' 42 if (!vfpEnabled(Cpacr, Cpsr, Fpexc)) 43 return disabledFault(); 44 ''' 45 46 vmsrEnabledCheckCode = ''' 47 if (!vfpEnabled(Cpacr, Cpsr)) 48 if (dest != (int)MISCREG_FPEXC && dest != (int)MISCREG_FPSID) 49 return disabledFault(); 50 if (!inPrivilegedMode(Cpsr)) 51 if (dest != (int)MISCREG_FPSCR) 52 return disabledFault(); 53 54 ''' 55 56 vmrsEnabledCheckCode = ''' 57 if (!vfpEnabled(Cpacr, Cpsr)) 58 if (op1 != (int)MISCREG_FPEXC && op1 != (int)MISCREG_FPSID && 59 op1 != (int)MISCREG_MVFR0 && op1 != (int)MISCREG_MVFR1) 60 return disabledFault(); 61 if (!inPrivilegedMode(Cpsr)) 62 if (op1 != (int)MISCREG_FPSCR) 63 return disabledFault(); 64 ''' 65}}; 66 67def template FpRegRegOpDeclare {{ 68class %(class_name)s : public %(base_class)s 69{ 70 public: 71 // Constructor 72 %(class_name)s(ExtMachInst machInst, 73 IntRegIndex _dest, IntRegIndex _op1, 74 VfpMicroMode mode = VfpNotAMicroop); 75 %(BasicExecDeclare)s 76}; 77}}; 78 79def template FpRegRegOpConstructor {{ 80 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 81 IntRegIndex _dest, IntRegIndex _op1, 82 VfpMicroMode mode) 83 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 84 _dest, _op1, mode) 85 { 86 %(constructor)s; 87 if (!(condCode == COND_AL || condCode == COND_UC)) { 88 for (int x = 0; x < _numDestRegs; x++) { 89 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 90 } 91 } 92 } 93}}; 94 95def template FpRegImmOpDeclare {{ 96class %(class_name)s : public %(base_class)s 97{ 98 public: 99 // Constructor 100 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 101 uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); 102 %(BasicExecDeclare)s 103}; 104}}; 105 106def template FpRegImmOpConstructor {{ 107 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 108 IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode) 109 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 110 _dest, _imm, mode) 111 { 112 %(constructor)s; 113 if (!(condCode == COND_AL || condCode == COND_UC)) { 114 for (int x = 0; x < _numDestRegs; x++) { 115 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 116 } 117 } 118 } 119}}; 120 121def template FpRegRegImmOpDeclare {{ 122class %(class_name)s : public %(base_class)s 123{ 124 public: 125 // Constructor 126 %(class_name)s(ExtMachInst machInst, 127 IntRegIndex _dest, IntRegIndex _op1, 128 uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); 129 %(BasicExecDeclare)s 130}; 131}}; 132 133def template FpRegRegImmOpConstructor {{ 134 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 135 IntRegIndex _dest, 136 IntRegIndex _op1, 137 uint64_t _imm, 138 VfpMicroMode mode) 139 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 140 _dest, _op1, _imm, mode) 141 { 142 %(constructor)s; 143 if (!(condCode == COND_AL || condCode == COND_UC)) { 144 for (int x = 0; x < _numDestRegs; x++) { 145 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 146 } 147 } 148 } 149}}; 150 151def template FpRegRegRegOpDeclare {{ 152class %(class_name)s : public %(base_class)s 153{ 154 public: 155 // Constructor 156 %(class_name)s(ExtMachInst machInst, 157 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 158 VfpMicroMode mode = VfpNotAMicroop); 159 %(BasicExecDeclare)s 160}; 161}}; 162 163def template FpRegRegRegOpConstructor {{ 164 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 165 IntRegIndex _dest, 166 IntRegIndex _op1, 167 IntRegIndex _op2, 168 VfpMicroMode mode) 169 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 170 _dest, _op1, _op2, mode) 171 { 172 %(constructor)s; 173 if (!(condCode == COND_AL || condCode == COND_UC)) { 174 for (int x = 0; x < _numDestRegs; x++) { 175 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 176 } 177 } 178 } 179}}; 180