vfp.isa revision 7644
16145SN/A// -*- mode:c++ -*- 26145SN/A 36145SN/A// Copyright (c) 2010 ARM Limited 46145SN/A// All rights reserved 56145SN/A// 66145SN/A// The license below extends only to copyright in the software and shall 76145SN/A// not be construed as granting a license to any other intellectual 86145SN/A// property including but not limited to intellectual property relating 96145SN/A// to a hardware implementation of the functionality of the software 106145SN/A// licensed hereunder. You may use the software subject to the license 116145SN/A// terms below provided that you ensure that this notice is replicated 126145SN/A// unmodified and in its entirety in all distributions of the software, 136145SN/A// modified or unmodified, in source code or in binary form. 146145SN/A// 156145SN/A// Redistribution and use in source and binary forms, with or without 166145SN/A// modification, are permitted provided that the following conditions are 176145SN/A// met: redistributions of source code must retain the above copyright 186145SN/A// notice, this list of conditions and the following disclaimer; 196145SN/A// redistributions in binary form must reproduce the above copyright 206145SN/A// notice, this list of conditions and the following disclaimer in the 216145SN/A// documentation and/or other materials provided with the distribution; 226145SN/A// neither the name of the copyright holders nor the names of its 236145SN/A// contributors may be used to endorse or promote products derived from 246145SN/A// this software without specific prior written permission. 256145SN/A// 266145SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 276145SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 286145SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2911793Sbrandon.potter@amd.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3011793Sbrandon.potter@amd.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317832SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327832SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 339356Snilay@cs.wisc.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 348232SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357054SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 368257SBrad.Beckmann@amd.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3711793Sbrandon.potter@amd.com// 387054SN/A// Authors: Gabe Black 396145SN/A 407055SN/Alet {{ 417055SN/A vfpEnabledCheckCode = ''' 427054SN/A if (!vfpEnabled(Cpacr, Cpsr, Fpexc)) 438257SBrad.Beckmann@amd.com return disabledFault(); 446145SN/A ''' 456145SN/A 466145SN/A vmsrEnabledCheckCode = ''' 476145SN/A if (!vfpEnabled(Cpacr, Cpsr)) 486145SN/A if (dest != (int)MISCREG_FPEXC && dest != (int)MISCREG_FPSID) 496145SN/A return disabledFault(); 506145SN/A if (!inPrivilegedMode(Cpsr)) 5111096Snilay@cs.wisc.edu if (dest != (int)MISCREG_FPSCR) 5211096Snilay@cs.wisc.edu return disabledFault(); 5311096Snilay@cs.wisc.edu 5411096Snilay@cs.wisc.edu ''' 5511096Snilay@cs.wisc.edu 566145SN/A vmrsEnabledCheckCode = ''' 576881SN/A if (!vfpEnabled(Cpacr, Cpsr)) 586881SN/A if (op1 != (int)MISCREG_FPEXC && op1 != (int)MISCREG_FPSID && 596285SN/A op1 != (int)MISCREG_MVFR0 && op1 != (int)MISCREG_MVFR1) 6011663Stushar@ece.gatech.edu return disabledFault(); 6111663Stushar@ece.gatech.edu if (!inPrivilegedMode(Cpsr)) 6211663Stushar@ece.gatech.edu if (op1 != (int)MISCREG_FPSCR) 6311663Stushar@ece.gatech.edu return disabledFault(); 6411663Stushar@ece.gatech.edu ''' 6511663Stushar@ece.gatech.edu}}; 6611663Stushar@ece.gatech.edu 6711663Stushar@ece.gatech.edudef template FpRegRegOpDeclare {{ 689594Snilay@cs.wisc.educlass %(class_name)s : public %(base_class)s 699594Snilay@cs.wisc.edu{ 708257SBrad.Beckmann@amd.com public: 718257SBrad.Beckmann@amd.com // Constructor 728257SBrad.Beckmann@amd.com %(class_name)s(ExtMachInst machInst, 736881SN/A IntRegIndex _dest, IntRegIndex _op1, 7410078Snilay@cs.wisc.edu VfpMicroMode mode = VfpNotAMicroop); 759869Sjthestness@gmail.com %(BasicExecDeclare)s 767054SN/A}; 778257SBrad.Beckmann@amd.com}}; 786145SN/A 798257SBrad.Beckmann@amd.comdef template FpRegRegOpConstructor {{ 8011663Stushar@ece.gatech.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8111663Stushar@ece.gatech.edu IntRegIndex _dest, IntRegIndex _op1, 8211663Stushar@ece.gatech.edu VfpMicroMode mode) 8311663Stushar@ece.gatech.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 847054SN/A _dest, _op1, mode) 856145SN/A { 8611663Stushar@ece.gatech.edu %(constructor)s; 879594Snilay@cs.wisc.edu } 889594Snilay@cs.wisc.edu}}; 898257SBrad.Beckmann@amd.com 9011663Stushar@ece.gatech.edudef template FpRegImmOpDeclare {{ 9111663Stushar@ece.gatech.educlass %(class_name)s : public %(base_class)s 926881SN/A{ 9311664Stushar@ece.gatech.edu public: 9411664Stushar@ece.gatech.edu // Constructor 9511664Stushar@ece.gatech.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 968257SBrad.Beckmann@amd.com uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); 978257SBrad.Beckmann@amd.com %(BasicExecDeclare)s 988257SBrad.Beckmann@amd.com}; 9911663Stushar@ece.gatech.edu}}; 10011663Stushar@ece.gatech.edu 1018257SBrad.Beckmann@amd.comdef template FpRegImmOpConstructor {{ 10211663Stushar@ece.gatech.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10311664Stushar@ece.gatech.edu IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode) 1047054SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1056145SN/A _dest, _imm, mode) 1066145SN/A { 1078257SBrad.Beckmann@amd.com %(constructor)s; 1089799Snilay@cs.wisc.edu } 1097054SN/A}}; 1107054SN/A 1117054SN/Adef template FpRegRegImmOpDeclare {{ 1128257SBrad.Beckmann@amd.comclass %(class_name)s : public %(base_class)s 1138257SBrad.Beckmann@amd.com{ 11410005Snilay@cs.wisc.edu public: 1158257SBrad.Beckmann@amd.com // Constructor 11611320Ssteve.reinhardt@amd.com %(class_name)s(ExtMachInst machInst, 1177054SN/A IntRegIndex _dest, IntRegIndex _op1, 1186881SN/A uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); 1198257SBrad.Beckmann@amd.com %(BasicExecDeclare)s 1207054SN/A}; 12111096Snilay@cs.wisc.edu}}; 12211096Snilay@cs.wisc.edu 12311096Snilay@cs.wisc.edudef template FpRegRegImmOpConstructor {{ 12411096Snilay@cs.wisc.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 12511096Snilay@cs.wisc.edu IntRegIndex _dest, 12611096Snilay@cs.wisc.edu IntRegIndex _op1, 1276145SN/A uint64_t _imm, 1287054SN/A VfpMicroMode mode) 1297054SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1307054SN/A _dest, _op1, _imm, mode) 1317054SN/A { 1326145SN/A %(constructor)s; 1337054SN/A } 1348257SBrad.Beckmann@amd.com}}; 1358257SBrad.Beckmann@amd.com 1368257SBrad.Beckmann@amd.comdef template FpRegRegRegOpDeclare {{ 1378257SBrad.Beckmann@amd.comclass %(class_name)s : public %(base_class)s 1388257SBrad.Beckmann@amd.com{ 1398257SBrad.Beckmann@amd.com public: 14011096Snilay@cs.wisc.edu // Constructor 1418257SBrad.Beckmann@amd.com %(class_name)s(ExtMachInst machInst, 1427054SN/A IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 14311320Ssteve.reinhardt@amd.com VfpMicroMode mode = VfpNotAMicroop); 1447054SN/A %(BasicExecDeclare)s 14511096Snilay@cs.wisc.edu}; 14611096Snilay@cs.wisc.edu}}; 14711096Snilay@cs.wisc.edu 1487054SN/Adef template FpRegRegRegOpConstructor {{ 1497054SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1507054SN/A IntRegIndex _dest, 1517054SN/A IntRegIndex _op1, 1529799Snilay@cs.wisc.edu IntRegIndex _op2, 1539799Snilay@cs.wisc.edu VfpMicroMode mode) 1549799Snilay@cs.wisc.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1557054SN/A _dest, _op1, _op2, mode) 1567054SN/A { 1576895SN/A %(constructor)s; 1586895SN/A } 1596895SN/A}}; 1607054SN/A