sve_mem.isa revision 13955:e0f46be83fc7 
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3//
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24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35//
36// Authors: Giacomo Gabrielli
37
38def template SveMemFillSpillOpDeclare {{
39    class %(class_name)s : public %(base_class)s
40    {
41      protected:
42        typedef uint8_t TPElem;
43        typedef uint8_t RegElemType;
44        typedef uint8_t MemElemType;
45
46      public:
47        %(class_name)s(ExtMachInst machInst,
48            IntRegIndex _dest, IntRegIndex _base, uint64_t _imm)
49            : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
50                _dest, _base, _imm)
51        {
52            %(constructor)s;
53        }
54
55        Fault execute(ExecContext *, Trace::InstRecord *) const;
56        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
57        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
58
59        virtual void
60        annotateFault(ArmFault *fault) {
61            %(fa_code)s
62        }
63    };
64}};
65
66def template SveContigMemSSOpDeclare {{
67    %(tpl_header)s
68    class %(class_name)s : public %(base_class)s
69    {
70      protected:
71        typedef RegElemType TPElem;
72
73      public:
74        %(class_name)s(const char* mnem, ExtMachInst machInst,
75            IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
76            IntRegIndex _offset)
77            : %(base_class)s(mnem, machInst, %(op_class)s,
78                _dest, _gp, _base, _offset)
79        {
80            %(constructor)s;
81        }
82
83        Fault execute(ExecContext *, Trace::InstRecord *) const;
84        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
85        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
86
87        virtual void
88        annotateFault(ArmFault *fault) {
89            %(fa_code)s
90        }
91    };
92}};
93
94def template SveContigMemSIOpDeclare {{
95    %(tpl_header)s
96    class %(class_name)s : public %(base_class)s
97    {
98      protected:
99        typedef RegElemType TPElem;
100
101      public:
102        %(class_name)s(const char* mnem, ExtMachInst machInst,
103            IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
104            uint64_t _imm)
105            : %(base_class)s(mnem, machInst, %(op_class)s,
106                _dest, _gp, _base, _imm)
107        {
108            %(constructor)s;
109        }
110
111        Fault execute(ExecContext *, Trace::InstRecord *) const;
112        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
113        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
114
115        virtual void
116        annotateFault(ArmFault *fault) {
117            %(fa_code)s
118        }
119    };
120}};
121
122def template SveContigMemExecDeclare {{
123    template
124    Fault %(class_name)s%(tpl_args)s::execute(ExecContext *,
125        Trace::InstRecord *) const;
126
127    template
128    Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *,
129        Trace::InstRecord *) const;
130
131    template
132    Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr,
133        ExecContext *, Trace::InstRecord *) const;
134}};
135
136def template SveContigLoadExecute {{
137    %(tpl_header)s
138    Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc,
139        Trace::InstRecord *traceData) const
140    {
141        Addr EA;
142        Fault fault = NoFault;
143        bool aarch64 M5_VAR_USED = true;
144        unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
145            xc->tcBase());
146
147        %(op_decl)s;
148        %(op_rd)s;
149        %(ea_code)s;
150
151        TheISA::VecRegContainer memData;
152        auto memDataView = memData.as<MemElemType>();
153
154        if (fault == NoFault) {
155            fault = xc->readMem(EA, memData.raw_ptr<uint8_t>(), memAccessSize,
156                this->memAccessFlags);
157            %(memacc_code)s;
158        }
159
160        if (fault == NoFault) {
161            %(op_wb)s;
162        }
163
164        return fault;
165    }
166}};
167
168def template SveContigLoadInitiateAcc {{
169    %(tpl_header)s
170    Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
171        Trace::InstRecord *traceData) const
172    {
173        Addr EA;
174        Fault fault = NoFault;
175        bool aarch64 M5_VAR_USED = true;
176        unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
177            xc->tcBase());
178
179        %(op_src_decl)s;
180        %(op_rd)s;
181
182        %(ea_code)s;
183
184        if (fault == NoFault) {
185            fault = xc->initiateMemRead(EA, memAccessSize,
186                this->memAccessFlags);
187        }
188
189        return fault;
190    }
191}};
192
193def template SveContigLoadCompleteAcc {{
194    %(tpl_header)s
195    Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
196        ExecContext *xc, Trace::InstRecord *traceData) const
197    {
198        Fault fault = NoFault;
199        bool aarch64 M5_VAR_USED = true;
200        unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
201            xc->tcBase());
202
203        %(op_decl)s;
204        %(op_rd)s;
205
206        TheISA::VecRegContainer memData;
207        auto memDataView = memData.as<MemElemType>();
208
209        memcpy(memData.raw_ptr<uint8_t>(), pkt->getPtr<uint8_t>(),
210            pkt->getSize());
211
212        if (fault == NoFault) {
213            %(memacc_code)s;
214        }
215
216        if (fault == NoFault) {
217            %(op_wb)s;
218        }
219
220        return fault;
221    }
222}};
223
224def template SveContigStoreExecute {{
225    %(tpl_header)s
226    Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc,
227        Trace::InstRecord *traceData) const
228    {
229        Addr EA;
230        Fault fault = NoFault;
231        bool aarch64 M5_VAR_USED = true;
232        unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
233            xc->tcBase());
234
235        %(op_decl)s;
236        %(op_rd)s;
237        %(ea_code)s;
238
239        TheISA::VecRegContainer memData;
240        auto memDataView = memData.as<MemElemType>();
241
242        %(wren_code)s;
243
244        if (fault == NoFault) {
245            %(memacc_code)s;
246        }
247
248        if (fault == NoFault) {
249            fault = xc->writeMem(memData.raw_ptr<uint8_t>(), memAccessSize, EA,
250                this->memAccessFlags, NULL, wrEn);
251        }
252
253        if (fault == NoFault) {
254            %(op_wb)s;
255        }
256
257        return fault;
258    }
259}};
260
261def template SveContigStoreInitiateAcc {{
262    %(tpl_header)s
263    Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
264        Trace::InstRecord *traceData) const
265    {
266        Addr EA;
267        Fault fault = NoFault;
268        bool aarch64 M5_VAR_USED = true;
269        unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
270            xc->tcBase());
271
272        %(op_decl)s;
273        %(op_rd)s;
274        %(ea_code)s;
275
276        TheISA::VecRegContainer memData;
277        auto memDataView = memData.as<MemElemType>();
278
279        %(wren_code)s;
280
281        if (fault == NoFault) {
282            %(memacc_code)s;
283        }
284
285        if (fault == NoFault) {
286            fault = xc->writeMem(memData.raw_ptr<uint8_t>(), memAccessSize, EA,
287                this->memAccessFlags, NULL, wrEn);
288        }
289
290        return fault;
291    }
292}};
293
294def template SveContigStoreCompleteAcc {{
295    %(tpl_header)s
296    Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
297        ExecContext *xc, Trace::InstRecord *traceData) const
298    {
299        return NoFault;
300    }
301}};
302
303def template SveLoadAndReplExecute {{
304    %(tpl_header)s
305    Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc,
306        Trace::InstRecord *traceData) const
307    {
308        Addr EA;
309        Fault fault = NoFault;
310        bool aarch64 M5_VAR_USED = true;
311        unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
312            xc->tcBase());
313
314        %(op_decl)s;
315        %(op_rd)s;
316        %(ea_code)s;
317
318        MemElemType memData;
319
320        if (fault == NoFault) {
321            fault = readMemAtomic(xc, traceData, EA, memData,
322                this->memAccessFlags);
323            %(memacc_code)s;
324        }
325
326        if (fault == NoFault) {
327            %(op_wb)s;
328        }
329
330        return fault;
331    }
332}};
333
334def template SveLoadAndReplInitiateAcc {{
335    %(tpl_header)s
336    Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
337        Trace::InstRecord *traceData) const
338    {
339        Addr EA;
340        Fault fault = NoFault;
341        bool aarch64 M5_VAR_USED = true;
342
343        %(op_src_decl)s;
344        %(op_rd)s;
345
346        %(ea_code)s;
347
348        MemElemType memData;
349
350        if (fault == NoFault) {
351            fault = initiateMemRead(xc, traceData, EA, memData,
352                this->memAccessFlags);
353        }
354
355        return fault;
356    }
357}};
358
359def template SveLoadAndReplCompleteAcc {{
360    %(tpl_header)s
361    Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
362        ExecContext *xc, Trace::InstRecord *traceData) const
363    {
364        Fault fault = NoFault;
365        bool aarch64 M5_VAR_USED = true;
366        unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
367            xc->tcBase());
368
369        %(op_decl)s;
370        %(op_rd)s;
371
372        MemElemType memData;
373        getMem(pkt, memData, traceData);
374
375        if (fault == NoFault) {
376            %(memacc_code)s;
377        }
378
379        if (fault == NoFault) {
380            %(op_wb)s;
381        }
382
383        return fault;
384    }
385}};
386
387