semihost.isa revision 12540
112540Sgiacomo.travaglini@arm.com// -*- mode:c++ -*- 212540Sgiacomo.travaglini@arm.com// Copyright (c) 2018 ARM Limited 312540Sgiacomo.travaglini@arm.com// All rights reserved 412540Sgiacomo.travaglini@arm.com// 512540Sgiacomo.travaglini@arm.com// The license below extends only to copyright in the software and shall 612540Sgiacomo.travaglini@arm.com// not be construed as granting a license to any other intellectual 712540Sgiacomo.travaglini@arm.com// property including but not limited to intellectual property relating 812540Sgiacomo.travaglini@arm.com// to a hardware implementation of the functionality of the software 912540Sgiacomo.travaglini@arm.com// licensed hereunder. You may use the software subject to the license 1012540Sgiacomo.travaglini@arm.com// terms below provided that you ensure that this notice is replicated 1112540Sgiacomo.travaglini@arm.com// unmodified and in its entirety in all distributions of the software, 1212540Sgiacomo.travaglini@arm.com// modified or unmodified, in source code or in binary form. 1312540Sgiacomo.travaglini@arm.com// 1412540Sgiacomo.travaglini@arm.com// Redistribution and use in source and binary forms, with or without 1512540Sgiacomo.travaglini@arm.com// modification, are permitted provided that the following conditions are 1612540Sgiacomo.travaglini@arm.com// met: redistributions of source code must retain the above copyright 1712540Sgiacomo.travaglini@arm.com// notice, this list of conditions and the following disclaimer; 1812540Sgiacomo.travaglini@arm.com// redistributions in binary form must reproduce the above copyright 1912540Sgiacomo.travaglini@arm.com// notice, this list of conditions and the following disclaimer in the 2012540Sgiacomo.travaglini@arm.com// documentation and/or other materials provided with the distribution; 2112540Sgiacomo.travaglini@arm.com// neither the name of the copyright holders nor the names of its 2212540Sgiacomo.travaglini@arm.com// contributors may be used to endorse or promote products derived from 2312540Sgiacomo.travaglini@arm.com// this software without specific prior written permission. 2412540Sgiacomo.travaglini@arm.com// 2512540Sgiacomo.travaglini@arm.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612540Sgiacomo.travaglini@arm.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712540Sgiacomo.travaglini@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812540Sgiacomo.travaglini@arm.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912540Sgiacomo.travaglini@arm.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012540Sgiacomo.travaglini@arm.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112540Sgiacomo.travaglini@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212540Sgiacomo.travaglini@arm.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312540Sgiacomo.travaglini@arm.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412540Sgiacomo.travaglini@arm.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512540Sgiacomo.travaglini@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612540Sgiacomo.travaglini@arm.com// 3712540Sgiacomo.travaglini@arm.com// Authors: Giacomo Travaglini 3812540Sgiacomo.travaglini@arm.com 3912540Sgiacomo.travaglini@arm.com// 4012540Sgiacomo.travaglini@arm.com// A new class of Semihosting constructor templates has been added. 4112540Sgiacomo.travaglini@arm.com// Their main purpose is to check if the Exception Generation 4212540Sgiacomo.travaglini@arm.com// Instructions (HLT, SVC) are actually a semihosting command. 4312540Sgiacomo.travaglini@arm.com// If that is the case, the IsMemBarrier flag is raised, so that 4412540Sgiacomo.travaglini@arm.com// in the O3 model we perform a coherent memory access during 4512540Sgiacomo.travaglini@arm.com// the semihosting operation. 4612540Sgiacomo.travaglini@arm.com// Please note: since we don't have a thread context pointer in the 4712540Sgiacomo.travaglini@arm.com// constructor we cannot check if semihosting is enabled in the 4812540Sgiacomo.travaglini@arm.com// system. This is not affecting functional correctness, it just 4912540Sgiacomo.travaglini@arm.com// means O3 models will flush the LSQ even if semihosting is disabled 5012540Sgiacomo.travaglini@arm.com// when a semihosting immediate is recognized. 5112540Sgiacomo.travaglini@arm.com 5212540Sgiacomo.travaglini@arm.comdef template SemihostConstructor {{ 5312540Sgiacomo.travaglini@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) 5412540Sgiacomo.travaglini@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 5512540Sgiacomo.travaglini@arm.com { 5612540Sgiacomo.travaglini@arm.com %(constructor)s; 5712540Sgiacomo.travaglini@arm.com if (!(condCode == COND_AL || condCode == COND_UC)) { 5812540Sgiacomo.travaglini@arm.com for (int x = 0; x < _numDestRegs; x++) { 5912540Sgiacomo.travaglini@arm.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 6012540Sgiacomo.travaglini@arm.com } 6112540Sgiacomo.travaglini@arm.com } 6212540Sgiacomo.travaglini@arm.com 6312540Sgiacomo.travaglini@arm.com // In AArch32 semihosting commands can be issued by either 6412540Sgiacomo.travaglini@arm.com // SVC and HLT instructions. Another degree of freedom 6512540Sgiacomo.travaglini@arm.com // is added by the operating mode (Arm or Thumb) 6612540Sgiacomo.travaglini@arm.com auto semihost_imm = machInst.thumb? %(thumb_semihost)s : 6712540Sgiacomo.travaglini@arm.com %(arm_semihost)s; 6812540Sgiacomo.travaglini@arm.com if (_imm == semihost_imm) { 6912540Sgiacomo.travaglini@arm.com flags[IsMemBarrier] = true; 7012540Sgiacomo.travaglini@arm.com } 7112540Sgiacomo.travaglini@arm.com } 7212540Sgiacomo.travaglini@arm.com}}; 7312540Sgiacomo.travaglini@arm.com 7412540Sgiacomo.travaglini@arm.comdef template SemihostConstructor64 {{ 7512540Sgiacomo.travaglini@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) 7612540Sgiacomo.travaglini@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 7712540Sgiacomo.travaglini@arm.com { 7812540Sgiacomo.travaglini@arm.com %(constructor)s; 7912540Sgiacomo.travaglini@arm.com 8012540Sgiacomo.travaglini@arm.com // In AArch64 there is only one instruction for issuing 8112540Sgiacomo.travaglini@arm.com // semhosting commands: HLT #0xF000 8212540Sgiacomo.travaglini@arm.com if (_imm == 0xF000) { 8312540Sgiacomo.travaglini@arm.com flags[IsMemBarrier] = true; 8412540Sgiacomo.travaglini@arm.com } 8512540Sgiacomo.travaglini@arm.com } 8612540Sgiacomo.travaglini@arm.com}}; 87