xref: /gem5/src/arch/arm/isa/templates/semihost.isa

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// Authors: Giacomo Travaglini

//
// A new class of Semihosting constructor templates has been added.
// Their main purpose is to check if the Exception Generation
// Instructions (HLT, SVC) are actually a semihosting command.
// If that is the case, the IsMemBarrier flag is raised, so that
// in the O3 model we perform a coherent memory access during
// the semihosting operation.
// Please note: since we don't have a thread context pointer in the
// constructor we cannot check if semihosting is enabled in the
// system. This is not affecting functional correctness, it just
// means O3 models will flush the LSQ even if semihosting is disabled
// when a semihosting immediate is recognized.

def template SemihostConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }

        // In AArch32 semihosting commands can be issued by either
        // SVC and HLT instructions. Another degree of freedom
        // is added by the operating mode (Arm or Thumb)
        auto semihost_imm = machInst.thumb? %(thumb_semihost)s :
                                            %(arm_semihost)s;
        if (_imm == semihost_imm) {
            flags[IsMemBarrier] = true;
        }
    }
}};

def template SemihostConstructor64 {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
    {
        %(constructor)s;

        // In AArch64 there is only one instruction for issuing
        // semhosting commands: HLT #0xF000
        if (_imm == 0xF000) {
            flags[IsMemBarrier] = true;
        }
    }
}};