pred.isa revision 7597 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Predicated Instruction Execution
46//
47
48let {{
49    predicateTest = 'testPredicate(OptCondCodes, condCode)'
50    condPredicateTest = 'testPredicate(CondCodes, condCode)'
51}};
52
53def template DataImmDeclare {{
54class %(class_name)s : public %(base_class)s
55{
56    public:
57        // Constructor
58        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
59                IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
60        %(BasicExecDeclare)s
61};
62}};
63
64def template DataImmConstructor {{
65    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
66                                          IntRegIndex _dest,
67                                          IntRegIndex _op1,
68                                          uint32_t _imm,
69                                          bool _rotC)
70        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
71                         _dest, _op1, _imm, _rotC)
72    {
73        %(constructor)s;
74    }
75}};
76
77def template DataRegDeclare {{
78class %(class_name)s : public %(base_class)s
79{
80    public:
81        // Constructor
82        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
83                IntRegIndex _op1, IntRegIndex _op2,
84                int32_t _shiftAmt, ArmShiftType _shiftType);
85        %(BasicExecDeclare)s
86};
87}};
88
89def template DataRegConstructor {{
90    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
91                                          IntRegIndex _dest,
92                                          IntRegIndex _op1,
93                                          IntRegIndex _op2,
94                                          int32_t _shiftAmt,
95                                          ArmShiftType _shiftType)
96        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
97                         _dest, _op1, _op2, _shiftAmt, _shiftType)
98    {
99        %(constructor)s;
100    }
101}};
102
103def template DataRegRegDeclare {{
104class %(class_name)s : public %(base_class)s
105{
106    public:
107        // Constructor
108        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
109                IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
110                ArmShiftType _shiftType);
111        %(BasicExecDeclare)s
112};
113}};
114
115def template DataRegRegConstructor {{
116    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
117                                          IntRegIndex _dest,
118                                          IntRegIndex _op1,
119                                          IntRegIndex _op2,
120                                          IntRegIndex _shift,
121                                          ArmShiftType _shiftType)
122        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
123                         _dest, _op1, _op2, _shift, _shiftType)
124    {
125        %(constructor)s;
126    }
127}};
128
129def template PredOpExecute {{
130    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
131    {
132        Fault fault = NoFault;
133        uint64_t resTemp = 0;
134        resTemp = resTemp;
135        %(op_decl)s;
136        %(op_rd)s;
137
138        if (%(predicate_test)s)
139        {
140            %(code)s;
141            if (fault == NoFault)
142            {
143                %(op_wb)s;
144            }
145        } else {
146            xc->setPredicate(false);
147        }
148
149        if (fault == NoFault && machInst.itstateMask != 0) {
150            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
151        }
152
153        return fault;
154    }
155}};
156
157def template DataDecode {{
158    if (machInst.opcode4 == 0) {
159        if (machInst.sField == 0)
160            return new %(class_name)sImm(machInst);
161        else
162            return new %(class_name)sImmCc(machInst);
163    } else {
164        if (machInst.sField == 0)
165            return new %(class_name)s(machInst);
166        else
167            return new %(class_name)sCc(machInst);
168    }
169}};
170
171def template DataImmDecode {{
172    if (machInst.sField == 0)
173        return new %(class_name)s(machInst);
174    else
175        return new %(class_name)sCc(machInst);
176}};
177