pred.isa revision 12236:126ac9da6050 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Predicated Instruction Execution
46//
47
48let {{
49    predicateTest = 'testPredicate(OptCondCodesNZ, OptCondCodesC, OptCondCodesV, condCode)'
50    condPredicateTest = 'testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)'
51}};
52
53def template DataImmDeclare {{
54class %(class_name)s : public %(base_class)s
55{
56    public:
57        // Constructor
58        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
59                IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
60        Fault execute(ExecContext *, Trace::InstRecord *) const;
61};
62}};
63
64def template DataImmConstructor {{
65    %(class_name)s::%(class_name)s(ExtMachInst machInst,
66                                          IntRegIndex _dest,
67                                          IntRegIndex _op1,
68                                          uint32_t _imm,
69                                          bool _rotC)
70        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
71                         _dest, _op1, _imm, _rotC)
72    {
73        %(constructor)s;
74        if (!(condCode == COND_AL || condCode == COND_UC)) {
75            for (int x = 0; x < _numDestRegs; x++) {
76                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
77            }
78        }
79
80        if (%(is_branch)s && !isFloating() && !isVector()){
81            flags[IsControl] = true;
82            flags[IsIndirectControl] = true;
83            if (condCode == COND_AL || condCode == COND_UC)
84                flags[IsUncondControl] = true;
85            else
86                flags[IsCondControl] = true;
87        }
88    }
89}};
90
91def template DataRegDeclare {{
92class %(class_name)s : public %(base_class)s
93{
94    public:
95        // Constructor
96        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
97                IntRegIndex _op1, IntRegIndex _op2,
98                int32_t _shiftAmt, ArmShiftType _shiftType);
99        Fault execute(ExecContext *, Trace::InstRecord *) const;
100};
101}};
102
103def template DataRegConstructor {{
104    %(class_name)s::%(class_name)s(ExtMachInst machInst,
105                                          IntRegIndex _dest,
106                                          IntRegIndex _op1,
107                                          IntRegIndex _op2,
108                                          int32_t _shiftAmt,
109                                          ArmShiftType _shiftType)
110        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
111                         _dest, _op1, _op2, _shiftAmt, _shiftType)
112    {
113        %(constructor)s;
114        if (!(condCode == COND_AL || condCode == COND_UC)) {
115            for (int x = 0; x < _numDestRegs; x++) {
116                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
117            }
118        }
119
120        if (%(is_branch)s && !isFloating() && !isVector()){
121            flags[IsControl] = true;
122            flags[IsIndirectControl] = true;
123            if (condCode == COND_AL || condCode == COND_UC)
124                flags[IsUncondControl] = true;
125            else
126                flags[IsCondControl] = true;
127
128            if (%(is_ras_pop)s) {
129                flags[IsReturn] = true;
130            }
131        }
132
133    }
134}};
135
136def template DataRegRegDeclare {{
137class %(class_name)s : public %(base_class)s
138{
139    public:
140        // Constructor
141        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
142                IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
143                ArmShiftType _shiftType);
144        Fault execute(ExecContext *, Trace::InstRecord *) const;
145};
146}};
147
148def template DataRegRegConstructor {{
149    %(class_name)s::%(class_name)s(ExtMachInst machInst,
150                                          IntRegIndex _dest,
151                                          IntRegIndex _op1,
152                                          IntRegIndex _op2,
153                                          IntRegIndex _shift,
154                                          ArmShiftType _shiftType)
155        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
156                         _dest, _op1, _op2, _shift, _shiftType)
157    {
158        %(constructor)s;
159        if (!(condCode == COND_AL || condCode == COND_UC)) {
160            for (int x = 0; x < _numDestRegs; x++) {
161                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
162            }
163        }
164    }
165}};
166
167def template PredOpExecute {{
168    Fault %(class_name)s::execute(
169        ExecContext *xc, Trace::InstRecord *traceData) const
170    {
171        Fault fault = NoFault;
172        uint64_t resTemp = 0;
173        resTemp = resTemp;
174        %(op_decl)s;
175        %(op_rd)s;
176
177        if (%(predicate_test)s)
178        {
179            %(code)s;
180            if (fault == NoFault)
181            {
182                %(op_wb)s;
183            }
184        } else {
185            xc->setPredicate(false);
186        }
187
188        return fault;
189    }
190}};
191
192def template QuiescePredOpExecute {{
193    Fault %(class_name)s::execute(
194        ExecContext *xc, Trace::InstRecord *traceData) const
195    {
196        Fault fault = NoFault;
197        uint64_t resTemp = 0;
198        resTemp = resTemp;
199        %(op_decl)s;
200        %(op_rd)s;
201
202        if (%(predicate_test)s)
203        {
204            %(code)s;
205            if (fault == NoFault)
206            {
207                %(op_wb)s;
208            }
209        } else {
210            xc->setPredicate(false);
211            PseudoInst::quiesceSkip(xc->tcBase());
212        }
213
214        return fault;
215    }
216}};
217
218def template QuiescePredOpExecuteWithFixup {{
219    Fault %(class_name)s::execute(
220        ExecContext *xc, Trace::InstRecord *traceData) const
221    {
222        Fault fault = NoFault;
223        uint64_t resTemp = 0;
224        resTemp = resTemp;
225        %(op_decl)s;
226        %(op_rd)s;
227
228        if (%(predicate_test)s)
229        {
230            %(code)s;
231            if (fault == NoFault)
232            {
233                %(op_wb)s;
234            }
235        } else {
236            xc->setPredicate(false);
237            %(pred_fixup)s;
238            PseudoInst::quiesceSkip(xc->tcBase());
239        }
240
241        return fault;
242    }
243}};
244
245def template DataDecode {{
246    if (machInst.opcode4 == 0) {
247        if (machInst.sField == 0)
248            return new %(class_name)sImm(machInst);
249        else
250            return new %(class_name)sImmCc(machInst);
251    } else {
252        if (machInst.sField == 0)
253            return new %(class_name)s(machInst);
254        else
255            return new %(class_name)sCc(machInst);
256    }
257}};
258
259def template DataImmDecode {{
260    if (machInst.sField == 0)
261        return new %(class_name)s(machInst);
262    else
263        return new %(class_name)sCc(machInst);
264}};
265