xref: /gem5/src/arch/arm/isa/templates/neon.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black

let {{
    simdEnabledCheckCode = '''
        if (!neonEnabled(Cpacr, Cpsr, Fpexc))
            return disabledFault();
    '''
}};


def template NeonRegRegRegOpDeclare {{
template <class _Element>
class %(class_name)s : public %(base_class)s
{
  protected:
    typedef _Element Element;
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }

    %(BasicExecDeclare)s
};
}};

def template NeonRegRegRegImmOpDeclare {{
template <class _Element>
class %(class_name)s : public %(base_class)s
{
  protected:
    typedef _Element Element;
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                   uint64_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, _imm)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }

    %(BasicExecDeclare)s
};
}};

def template NeonRegRegImmOpDeclare {{
template <class _Element>
class %(class_name)s : public %(base_class)s
{
  protected:
    typedef _Element Element;
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _imm)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }

    %(BasicExecDeclare)s
};
}};

def template NeonRegImmOpDeclare {{
template <class _Element>
class %(class_name)s : public %(base_class)s
{
  protected:
    typedef _Element Element;
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }

    %(BasicExecDeclare)s
};
}};

def template NeonRegRegOpDeclare {{
template <class _Element>
class %(class_name)s : public %(base_class)s
{
  protected:
    typedef _Element Element;
  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }

    %(BasicExecDeclare)s
};
}};

def template NeonExecDeclare {{
    template
    Fault %(class_name)s<%(targs)s>::execute(
            %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};

output header {{
    template <class T>
    // Implement a less-than-zero function: ltz()
    // this function exists because some versions of GCC complain when a
    // comparison is done between a unsigned variable and 0 and for GCC 4.2
    // there is no way to disable this warning
    inline bool ltz(T t);

    template <>
    inline bool ltz(uint8_t) { return false; }
    template <>
    inline bool ltz(uint16_t) { return false; }
    template <>
    inline bool ltz(uint32_t) { return false; }
    template <>
    inline bool ltz(uint64_t) { return false; }
    template <>
    inline bool ltz(int8_t v) { return v < 0; }
    template <>
    inline bool ltz(int16_t v) { return v < 0; }
    template <>
    inline bool ltz(int32_t v) { return v < 0; }
    template <>
    inline bool ltz(int64_t v) { return v < 0; }
}};

def template NeonEqualRegExecute {{
    template <class Element>
    Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
            Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;
        %(op_decl)s;
        %(op_rd)s;

        const unsigned rCount = %(r_count)d;
        const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);

        union RegVect {
            FloatRegBits regs[rCount];
            Element elements[eCount];
        };

        if (%(predicate_test)s)
        {
            %(code)s;
            if (fault == NoFault)
            {
                %(op_wb)s;
            }
        } else {
            xc->setPredicate(false);
        }

        if (fault == NoFault && machInst.itstateMask != 0) {
            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
        }

        return fault;
    }
}};

output header {{
    uint16_t nextBiggerType(uint8_t);
    uint32_t nextBiggerType(uint16_t);
    uint64_t nextBiggerType(uint32_t);
    int16_t nextBiggerType(int8_t);
    int32_t nextBiggerType(int16_t);
    int64_t nextBiggerType(int32_t);
}};

def template NeonUnequalRegExecute {{
    template <class Element>
    Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
            Trace::InstRecord *traceData) const
    {
        typedef typeof(nextBiggerType((Element)0)) BigElement;
        Fault fault = NoFault;
        %(op_decl)s;
        %(op_rd)s;

        const unsigned rCount = %(r_count)d;
        const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);

        union RegVect {
            FloatRegBits regs[rCount];
            Element elements[eCount];
            BigElement bigElements[eCount / 2];
        };

        union BigRegVect {
            FloatRegBits regs[2 * rCount];
            BigElement elements[eCount];
        };

        if (%(predicate_test)s)
        {
            %(code)s;
            if (fault == NoFault)
            {
                %(op_wb)s;
            }
        } else {
            xc->setPredicate(false);
        }

        if (fault == NoFault && machInst.itstateMask != 0) {
            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
        }

        return fault;
    }
}};