misc64.isa revision 12616:4b463b4dc098 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011,2017-2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template ImmOp64Declare {{
41class %(class_name)s : public %(base_class)s
42{
43  protected:
44    public:
45        // Constructor
46        %(class_name)s(ExtMachInst machInst,uint64_t _imm);
47
48        Fault execute(ExecContext *, Trace::InstRecord *) const override;
49};
50}};
51
52def template ImmOp64Constructor {{
53    %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
54        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
55    {
56        %(constructor)s;
57    }
58}};
59
60def template RegRegImmImmOp64Declare {{
61class %(class_name)s : public %(base_class)s
62{
63  protected:
64    public:
65        // Constructor
66        %(class_name)s(ExtMachInst machInst,
67                       IntRegIndex _dest, IntRegIndex _op1,
68                       uint64_t _imm1, uint64_t _imm2);
69        Fault execute(ExecContext *, Trace::InstRecord *) const override;
70};
71}};
72
73def template RegRegImmImmOp64Constructor {{
74    %(class_name)s::%(class_name)s(ExtMachInst machInst,
75                                          IntRegIndex _dest,
76                                          IntRegIndex _op1,
77                                          uint64_t _imm1,
78                                          uint64_t _imm2)
79        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
80                         _dest, _op1, _imm1, _imm2)
81    {
82        %(constructor)s;
83    }
84}};
85
86def template RegRegRegImmOp64Declare {{
87class %(class_name)s : public %(base_class)s
88{
89  protected:
90    public:
91        // Constructor
92        %(class_name)s(ExtMachInst machInst,
93                       IntRegIndex _dest, IntRegIndex _op1,
94                       IntRegIndex _op2, uint64_t _imm);
95        Fault execute(ExecContext *, Trace::InstRecord *) const override;
96};
97}};
98
99def template RegRegRegImmOp64Constructor {{
100    %(class_name)s::%(class_name)s(ExtMachInst machInst,
101                                          IntRegIndex _dest,
102                                          IntRegIndex _op1,
103                                          IntRegIndex _op2,
104                                          uint64_t _imm)
105        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
106                         _dest, _op1, _op2, _imm)
107    {
108        %(constructor)s;
109    }
110}};
111
112def template MiscRegRegOp64Declare {{
113class %(class_name)s : public %(base_class)s
114{
115    public:
116        // Constructor
117        %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
118                IntRegIndex _op1, uint64_t _imm);
119
120        Fault execute(ExecContext *, Trace::InstRecord *) const override;
121};
122}};
123
124def template MiscRegRegOp64Constructor {{
125    %(class_name)s::%(class_name)s(ExtMachInst machInst,
126                                          MiscRegIndex _dest,
127                                          IntRegIndex _op1,
128                                          uint64_t _imm)
129        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
130                         _dest, _op1, _imm)
131    {
132        %(constructor)s;
133    }
134}};
135
136def template RegMiscRegOp64Declare {{
137class %(class_name)s : public %(base_class)s
138{
139    public:
140        // Constructor
141        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
142                MiscRegIndex _op1, uint64_t _imm);
143
144        Fault execute(ExecContext *, Trace::InstRecord *) const override;
145};
146}};
147
148def template RegMiscRegOp64Constructor {{
149    %(class_name)s::%(class_name)s(ExtMachInst machInst,
150                                          IntRegIndex _dest,
151                                          MiscRegIndex _op1,
152                                          uint64_t _imm)
153        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
154                         _dest, _op1, _imm)
155    {
156        %(constructor)s;
157    }
158}};
159