mem.isa revision 7408:ee6949c5bb5b
15217Ssaidi@eecs.umich.edu// -*- mode:c++ -*- 29428SAndreas.Sandberg@ARM.com 39920Syasuko.eckert@amd.com// Copyright (c) 2010 ARM Limited 49428SAndreas.Sandberg@ARM.com// All rights reserved 59428SAndreas.Sandberg@ARM.com// 69428SAndreas.Sandberg@ARM.com// The license below extends only to copyright in the software and shall 79428SAndreas.Sandberg@ARM.com// not be construed as granting a license to any other intellectual 89428SAndreas.Sandberg@ARM.com// property including but not limited to intellectual property relating 99428SAndreas.Sandberg@ARM.com// to a hardware implementation of the functionality of the software 109428SAndreas.Sandberg@ARM.com// licensed hereunder. You may use the software subject to the license 119428SAndreas.Sandberg@ARM.com// terms below provided that you ensure that this notice is replicated 129428SAndreas.Sandberg@ARM.com// unmodified and in its entirety in all distributions of the software, 139428SAndreas.Sandberg@ARM.com// modified or unmodified, in source code or in binary form. 149428SAndreas.Sandberg@ARM.com// 155217Ssaidi@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 165217Ssaidi@eecs.umich.edu// All rights reserved. 175217Ssaidi@eecs.umich.edu// 185217Ssaidi@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 195217Ssaidi@eecs.umich.edu// modification, are permitted provided that the following conditions are 205217Ssaidi@eecs.umich.edu// met: redistributions of source code must retain the above copyright 215217Ssaidi@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 225217Ssaidi@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 235217Ssaidi@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 245217Ssaidi@eecs.umich.edu// documentation and/or other materials provided with the distribution; 255217Ssaidi@eecs.umich.edu// neither the name of the copyright holders nor the names of its 265217Ssaidi@eecs.umich.edu// contributors may be used to endorse or promote products derived from 275217Ssaidi@eecs.umich.edu// this software without specific prior written permission. 285217Ssaidi@eecs.umich.edu// 295217Ssaidi@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305217Ssaidi@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315217Ssaidi@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325217Ssaidi@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335217Ssaidi@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345217Ssaidi@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355217Ssaidi@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365217Ssaidi@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375217Ssaidi@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385217Ssaidi@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395217Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405217Ssaidi@eecs.umich.edu// 415217Ssaidi@eecs.umich.edu// Authors: Stephen Hines 425217Ssaidi@eecs.umich.edu 435217Ssaidi@eecs.umich.edu 445217Ssaidi@eecs.umich.edudef template SwapExecute {{ 455217Ssaidi@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 466658Snate@binkert.org Trace::InstRecord *traceData) const 479441SAndreas.Sandberg@ARM.com { 489441SAndreas.Sandberg@ARM.com Addr EA; 495217Ssaidi@eecs.umich.edu Fault fault = NoFault; 508232Snate@binkert.org 519441SAndreas.Sandberg@ARM.com %(op_decl)s; 525217Ssaidi@eecs.umich.edu uint64_t memData = 0; 535217Ssaidi@eecs.umich.edu %(op_rd)s; 545217Ssaidi@eecs.umich.edu %(ea_code)s; 555217Ssaidi@eecs.umich.edu 565217Ssaidi@eecs.umich.edu if (%(predicate_test)s) 575217Ssaidi@eecs.umich.edu { 585217Ssaidi@eecs.umich.edu %(preacc_code)s; 595217Ssaidi@eecs.umich.edu 605217Ssaidi@eecs.umich.edu if (fault == NoFault) { 615217Ssaidi@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 625217Ssaidi@eecs.umich.edu EA, memAccessFlags, &memData); 635217Ssaidi@eecs.umich.edu } 645217Ssaidi@eecs.umich.edu 655217Ssaidi@eecs.umich.edu if (fault == NoFault) { 665217Ssaidi@eecs.umich.edu %(postacc_code)s; 675217Ssaidi@eecs.umich.edu } 685217Ssaidi@eecs.umich.edu 695217Ssaidi@eecs.umich.edu if (fault == NoFault) { 705217Ssaidi@eecs.umich.edu %(op_wb)s; 715217Ssaidi@eecs.umich.edu } 725217Ssaidi@eecs.umich.edu } 735217Ssaidi@eecs.umich.edu 745217Ssaidi@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 755217Ssaidi@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 765217Ssaidi@eecs.umich.edu } 775217Ssaidi@eecs.umich.edu 785217Ssaidi@eecs.umich.edu return fault; 795217Ssaidi@eecs.umich.edu } 805217Ssaidi@eecs.umich.edu}}; 815217Ssaidi@eecs.umich.edu 825217Ssaidi@eecs.umich.edudef template SwapInitiateAcc {{ 839920Syasuko.eckert@amd.com Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 849920Syasuko.eckert@amd.com Trace::InstRecord *traceData) const 859920Syasuko.eckert@amd.com { 869920Syasuko.eckert@amd.com Addr EA; 879920Syasuko.eckert@amd.com Fault fault = NoFault; 889920Syasuko.eckert@amd.com 899920Syasuko.eckert@amd.com %(op_decl)s; 909920Syasuko.eckert@amd.com uint64_t memData = 0; 917720Sgblack@eecs.umich.edu %(op_rd)s; 927720Sgblack@eecs.umich.edu %(ea_code)s; 935712Shsul@eecs.umich.edu 945712Shsul@eecs.umich.edu if (%(predicate_test)s) 955217Ssaidi@eecs.umich.edu { 965217Ssaidi@eecs.umich.edu %(preacc_code)s; 975714Shsul@eecs.umich.edu 985714Shsul@eecs.umich.edu if (fault == NoFault) { 995714Shsul@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1005714Shsul@eecs.umich.edu memAccessFlags, &memData); 1015714Shsul@eecs.umich.edu } 1025714Shsul@eecs.umich.edu 1035714Shsul@eecs.umich.edu if (fault == NoFault) { 1045217Ssaidi@eecs.umich.edu %(op_wb)s; 1059428SAndreas.Sandberg@ARM.com } 1069428SAndreas.Sandberg@ARM.com } 1079428SAndreas.Sandberg@ARM.com 1089428SAndreas.Sandberg@ARM.com if (fault == NoFault && machInst.itstateMask != 0) { 1099428SAndreas.Sandberg@ARM.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1109428SAndreas.Sandberg@ARM.com } 1119428SAndreas.Sandberg@ARM.com 1129428SAndreas.Sandberg@ARM.com return fault; 1139428SAndreas.Sandberg@ARM.com } 1149428SAndreas.Sandberg@ARM.com}}; 1159428SAndreas.Sandberg@ARM.com 1169428SAndreas.Sandberg@ARM.comdef template SwapCompleteAcc {{ 1179428SAndreas.Sandberg@ARM.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 1189428SAndreas.Sandberg@ARM.com %(CPU_exec_context)s *xc, 1199428SAndreas.Sandberg@ARM.com Trace::InstRecord *traceData) const 1209428SAndreas.Sandberg@ARM.com { 1219428SAndreas.Sandberg@ARM.com Fault fault = NoFault; 1229428SAndreas.Sandberg@ARM.com 1239920Syasuko.eckert@amd.com %(op_decl)s; 1249920Syasuko.eckert@amd.com %(op_rd)s; 1259920Syasuko.eckert@amd.com 1269920Syasuko.eckert@amd.com if (%(predicate_test)s) 1279920Syasuko.eckert@amd.com { 1289920Syasuko.eckert@amd.com // ARM instructions will not have a pkt if the predicate is false 1299920Syasuko.eckert@amd.com uint64_t memData = pkt->get<typeof(Mem)>(); 1309428SAndreas.Sandberg@ARM.com 1319428SAndreas.Sandberg@ARM.com %(postacc_code)s; 1329428SAndreas.Sandberg@ARM.com 1339428SAndreas.Sandberg@ARM.com if (fault == NoFault) { 1349428SAndreas.Sandberg@ARM.com %(op_wb)s; 1359428SAndreas.Sandberg@ARM.com } 1369428SAndreas.Sandberg@ARM.com } 1379428SAndreas.Sandberg@ARM.com 1389428SAndreas.Sandberg@ARM.com if (fault == NoFault && machInst.itstateMask != 0) { 1399428SAndreas.Sandberg@ARM.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1409428SAndreas.Sandberg@ARM.com } 1419428SAndreas.Sandberg@ARM.com 1429428SAndreas.Sandberg@ARM.com return fault; 1439428SAndreas.Sandberg@ARM.com } 1449428SAndreas.Sandberg@ARM.com}}; 1459428SAndreas.Sandberg@ARM.com 1469428SAndreas.Sandberg@ARM.comdef template LoadExecute {{ 1479428SAndreas.Sandberg@ARM.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1489428SAndreas.Sandberg@ARM.com Trace::InstRecord *traceData) const 1499428SAndreas.Sandberg@ARM.com { 1509428SAndreas.Sandberg@ARM.com Addr EA; 1519428SAndreas.Sandberg@ARM.com Fault fault = NoFault; 1529920Syasuko.eckert@amd.com 1539920Syasuko.eckert@amd.com %(op_decl)s; 1549920Syasuko.eckert@amd.com %(op_rd)s; 1559920Syasuko.eckert@amd.com %(ea_code)s; 1569920Syasuko.eckert@amd.com 1579920Syasuko.eckert@amd.com if (%(predicate_test)s) 1589920Syasuko.eckert@amd.com { 1599428SAndreas.Sandberg@ARM.com if (fault == NoFault) { 1609428SAndreas.Sandberg@ARM.com fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1619428SAndreas.Sandberg@ARM.com %(memacc_code)s; 1629428SAndreas.Sandberg@ARM.com } 1639428SAndreas.Sandberg@ARM.com 1649428SAndreas.Sandberg@ARM.com if (fault == NoFault) { 1659441SAndreas.Sandberg@ARM.com %(op_wb)s; 1669441SAndreas.Sandberg@ARM.com } 1679441SAndreas.Sandberg@ARM.com } 1689441SAndreas.Sandberg@ARM.com 1699441SAndreas.Sandberg@ARM.com if (fault == NoFault && machInst.itstateMask != 0) { 1709441SAndreas.Sandberg@ARM.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1719441SAndreas.Sandberg@ARM.com } 1729441SAndreas.Sandberg@ARM.com 1739441SAndreas.Sandberg@ARM.com return fault; 1749441SAndreas.Sandberg@ARM.com } 1759441SAndreas.Sandberg@ARM.com}}; 1769441SAndreas.Sandberg@ARM.com 1779441SAndreas.Sandberg@ARM.comdef template StoreExecute {{ 1789441SAndreas.Sandberg@ARM.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1799441SAndreas.Sandberg@ARM.com Trace::InstRecord *traceData) const 1809441SAndreas.Sandberg@ARM.com { 1819441SAndreas.Sandberg@ARM.com Addr EA; 1829441SAndreas.Sandberg@ARM.com Fault fault = NoFault; 1839441SAndreas.Sandberg@ARM.com 1849441SAndreas.Sandberg@ARM.com %(op_decl)s; 1859441SAndreas.Sandberg@ARM.com %(op_rd)s; 1869441SAndreas.Sandberg@ARM.com %(ea_code)s; 1879441SAndreas.Sandberg@ARM.com 1889441SAndreas.Sandberg@ARM.com if (%(predicate_test)s) 1899441SAndreas.Sandberg@ARM.com { 1909441SAndreas.Sandberg@ARM.com if (fault == NoFault) { 1919441SAndreas.Sandberg@ARM.com %(memacc_code)s; 1929441SAndreas.Sandberg@ARM.com } 1939441SAndreas.Sandberg@ARM.com 1949441SAndreas.Sandberg@ARM.com if (fault == NoFault) { 1959441SAndreas.Sandberg@ARM.com fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1969441SAndreas.Sandberg@ARM.com memAccessFlags, NULL); 1979441SAndreas.Sandberg@ARM.com if (traceData) { traceData->setData(Mem); } 1989441SAndreas.Sandberg@ARM.com } 199 200 if (fault == NoFault) { 201 %(op_wb)s; 202 } 203 } 204 205 if (fault == NoFault && machInst.itstateMask != 0) { 206 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 207 } 208 209 return fault; 210 } 211}}; 212 213def template StoreExExecute {{ 214 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 215 Trace::InstRecord *traceData) const 216 { 217 Addr EA; 218 Fault fault = NoFault; 219 220 %(op_decl)s; 221 %(op_rd)s; 222 %(ea_code)s; 223 224 if (%(predicate_test)s) 225 { 226 if (fault == NoFault) { 227 %(memacc_code)s; 228 } 229 230 uint64_t writeResult; 231 232 if (fault == NoFault) { 233 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 234 memAccessFlags, &writeResult); 235 if (traceData) { traceData->setData(Mem); } 236 } 237 238 if (fault == NoFault) { 239 %(postacc_code)s; 240 } 241 242 if (fault == NoFault) { 243 %(op_wb)s; 244 } 245 } 246 247 if (fault == NoFault && machInst.itstateMask != 0) { 248 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 249 } 250 251 return fault; 252 } 253}}; 254 255def template StoreExInitiateAcc {{ 256 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 257 Trace::InstRecord *traceData) const 258 { 259 Addr EA; 260 Fault fault = NoFault; 261 262 %(op_decl)s; 263 %(op_rd)s; 264 %(ea_code)s; 265 266 if (%(predicate_test)s) 267 { 268 if (fault == NoFault) { 269 %(memacc_code)s; 270 } 271 272 if (fault == NoFault) { 273 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 274 memAccessFlags, NULL); 275 if (traceData) { traceData->setData(Mem); } 276 } 277 278 // Need to write back any potential address register update 279 if (fault == NoFault) { 280 %(op_wb)s; 281 } 282 } 283 284 if (fault == NoFault && machInst.itstateMask != 0) { 285 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 286 } 287 288 return fault; 289 } 290}}; 291 292def template StoreInitiateAcc {{ 293 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 294 Trace::InstRecord *traceData) const 295 { 296 Addr EA; 297 Fault fault = NoFault; 298 299 %(op_decl)s; 300 %(op_rd)s; 301 %(ea_code)s; 302 303 if (%(predicate_test)s) 304 { 305 if (fault == NoFault) { 306 %(memacc_code)s; 307 } 308 309 if (fault == NoFault) { 310 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 311 memAccessFlags, NULL); 312 if (traceData) { traceData->setData(Mem); } 313 } 314 315 // Need to write back any potential address register update 316 if (fault == NoFault) { 317 %(op_wb)s; 318 } 319 } 320 321 if (fault == NoFault && machInst.itstateMask != 0) { 322 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 323 } 324 325 return fault; 326 } 327}}; 328 329def template LoadInitiateAcc {{ 330 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 331 Trace::InstRecord *traceData) const 332 { 333 Addr EA; 334 Fault fault = NoFault; 335 336 %(op_src_decl)s; 337 %(op_rd)s; 338 %(ea_code)s; 339 340 if (%(predicate_test)s) 341 { 342 if (fault == NoFault) { 343 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 344 } 345 } 346 347 return fault; 348 } 349}}; 350 351def template LoadCompleteAcc {{ 352 Fault %(class_name)s::completeAcc(PacketPtr pkt, 353 %(CPU_exec_context)s *xc, 354 Trace::InstRecord *traceData) const 355 { 356 Fault fault = NoFault; 357 358 %(op_decl)s; 359 %(op_rd)s; 360 361 if (%(predicate_test)s) 362 { 363 // ARM instructions will not have a pkt if the predicate is false 364 Mem = pkt->get<typeof(Mem)>(); 365 366 if (fault == NoFault) { 367 %(memacc_code)s; 368 } 369 370 if (fault == NoFault) { 371 %(op_wb)s; 372 } 373 } 374 375 if (fault == NoFault && machInst.itstateMask != 0) { 376 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 377 } 378 379 return fault; 380 } 381}}; 382 383def template StoreCompleteAcc {{ 384 Fault %(class_name)s::completeAcc(PacketPtr pkt, 385 %(CPU_exec_context)s *xc, 386 Trace::InstRecord *traceData) const 387 { 388 Fault fault = NoFault; 389 390 %(op_decl)s; 391 %(op_rd)s; 392 393 if (%(predicate_test)s) 394 { 395 if (fault == NoFault) { 396 %(op_wb)s; 397 } 398 } 399 400 if (fault == NoFault && machInst.itstateMask != 0) { 401 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 402 } 403 404 return fault; 405 } 406}}; 407 408def template StoreExCompleteAcc {{ 409 Fault %(class_name)s::completeAcc(PacketPtr pkt, 410 %(CPU_exec_context)s *xc, 411 Trace::InstRecord *traceData) const 412 { 413 Fault fault = NoFault; 414 415 %(op_decl)s; 416 %(op_rd)s; 417 418 if (%(predicate_test)s) 419 { 420 uint64_t writeResult = pkt->req->getExtraData(); 421 %(postacc_code)s; 422 423 if (fault == NoFault) { 424 %(op_wb)s; 425 } 426 } 427 428 if (fault == NoFault && machInst.itstateMask != 0) { 429 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 430 } 431 432 return fault; 433 } 434}}; 435 436def template RfeDeclare {{ 437 /** 438 * Static instruction class for "%(mnemonic)s". 439 */ 440 class %(class_name)s : public %(base_class)s 441 { 442 public: 443 444 /// Constructor. 445 %(class_name)s(ExtMachInst machInst, 446 uint32_t _base, int _mode, bool _wb); 447 448 %(BasicExecDeclare)s 449 450 %(InitiateAccDeclare)s 451 452 %(CompleteAccDeclare)s 453 }; 454}}; 455 456def template SrsDeclare {{ 457 /** 458 * Static instruction class for "%(mnemonic)s". 459 */ 460 class %(class_name)s : public %(base_class)s 461 { 462 public: 463 464 /// Constructor. 465 %(class_name)s(ExtMachInst machInst, 466 uint32_t _regMode, int _mode, bool _wb); 467 468 %(BasicExecDeclare)s 469 470 %(InitiateAccDeclare)s 471 472 %(CompleteAccDeclare)s 473 }; 474}}; 475 476def template SwapDeclare {{ 477 /** 478 * Static instruction class for "%(mnemonic)s". 479 */ 480 class %(class_name)s : public %(base_class)s 481 { 482 public: 483 484 /// Constructor. 485 %(class_name)s(ExtMachInst machInst, 486 uint32_t _dest, uint32_t _op1, uint32_t _base); 487 488 %(BasicExecDeclare)s 489 490 %(InitiateAccDeclare)s 491 492 %(CompleteAccDeclare)s 493 }; 494}}; 495 496def template LoadStoreDImmDeclare {{ 497 /** 498 * Static instruction class for "%(mnemonic)s". 499 */ 500 class %(class_name)s : public %(base_class)s 501 { 502 public: 503 504 /// Constructor. 505 %(class_name)s(ExtMachInst machInst, 506 uint32_t _dest, uint32_t _dest2, 507 uint32_t _base, bool _add, int32_t _imm); 508 509 %(BasicExecDeclare)s 510 511 %(InitiateAccDeclare)s 512 513 %(CompleteAccDeclare)s 514 }; 515}}; 516 517def template StoreExDImmDeclare {{ 518 /** 519 * Static instruction class for "%(mnemonic)s". 520 */ 521 class %(class_name)s : public %(base_class)s 522 { 523 public: 524 525 /// Constructor. 526 %(class_name)s(ExtMachInst machInst, 527 uint32_t _result, uint32_t _dest, uint32_t _dest2, 528 uint32_t _base, bool _add, int32_t _imm); 529 530 %(BasicExecDeclare)s 531 532 %(InitiateAccDeclare)s 533 534 %(CompleteAccDeclare)s 535 }; 536}}; 537 538def template LoadStoreImmDeclare {{ 539 /** 540 * Static instruction class for "%(mnemonic)s". 541 */ 542 class %(class_name)s : public %(base_class)s 543 { 544 public: 545 546 /// Constructor. 547 %(class_name)s(ExtMachInst machInst, 548 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 549 550 %(BasicExecDeclare)s 551 552 %(InitiateAccDeclare)s 553 554 %(CompleteAccDeclare)s 555 }; 556}}; 557 558def template StoreExImmDeclare {{ 559 /** 560 * Static instruction class for "%(mnemonic)s". 561 */ 562 class %(class_name)s : public %(base_class)s 563 { 564 public: 565 566 /// Constructor. 567 %(class_name)s(ExtMachInst machInst, 568 uint32_t _result, uint32_t _dest, uint32_t _base, 569 bool _add, int32_t _imm); 570 571 %(BasicExecDeclare)s 572 573 %(InitiateAccDeclare)s 574 575 %(CompleteAccDeclare)s 576 }; 577}}; 578 579def template LoadStoreDRegDeclare {{ 580 /** 581 * Static instruction class for "%(mnemonic)s". 582 */ 583 class %(class_name)s : public %(base_class)s 584 { 585 public: 586 587 /// Constructor. 588 %(class_name)s(ExtMachInst machInst, 589 uint32_t _dest, uint32_t _dest2, 590 uint32_t _base, bool _add, 591 int32_t _shiftAmt, uint32_t _shiftType, 592 uint32_t _index); 593 594 %(BasicExecDeclare)s 595 596 %(InitiateAccDeclare)s 597 598 %(CompleteAccDeclare)s 599 }; 600}}; 601 602def template LoadStoreRegDeclare {{ 603 /** 604 * Static instruction class for "%(mnemonic)s". 605 */ 606 class %(class_name)s : public %(base_class)s 607 { 608 public: 609 610 /// Constructor. 611 %(class_name)s(ExtMachInst machInst, 612 uint32_t _dest, uint32_t _base, bool _add, 613 int32_t _shiftAmt, uint32_t _shiftType, 614 uint32_t _index); 615 616 %(BasicExecDeclare)s 617 618 %(InitiateAccDeclare)s 619 620 %(CompleteAccDeclare)s 621 }; 622}}; 623 624def template InitiateAccDeclare {{ 625 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 626}}; 627 628def template CompleteAccDeclare {{ 629 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 630}}; 631 632def template RfeConstructor {{ 633 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 634 uint32_t _base, int _mode, bool _wb) 635 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 636 (IntRegIndex)_base, (AddrMode)_mode, _wb) 637 { 638 %(constructor)s; 639 } 640}}; 641 642def template SrsConstructor {{ 643 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 644 uint32_t _regMode, int _mode, bool _wb) 645 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 646 (OperatingMode)_regMode, (AddrMode)_mode, _wb) 647 { 648 %(constructor)s; 649 } 650}}; 651 652def template SwapConstructor {{ 653 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 654 uint32_t _dest, uint32_t _op1, uint32_t _base) 655 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 656 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 657 { 658 %(constructor)s; 659 } 660}}; 661 662def template LoadStoreDImmConstructor {{ 663 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 664 uint32_t _dest, uint32_t _dest2, 665 uint32_t _base, bool _add, int32_t _imm) 666 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 667 (IntRegIndex)_dest, (IntRegIndex)_dest2, 668 (IntRegIndex)_base, _add, _imm) 669 { 670 %(constructor)s; 671 } 672}}; 673 674def template StoreExDImmConstructor {{ 675 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 676 uint32_t _result, uint32_t _dest, uint32_t _dest2, 677 uint32_t _base, bool _add, int32_t _imm) 678 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 679 (IntRegIndex)_result, 680 (IntRegIndex)_dest, (IntRegIndex)_dest2, 681 (IntRegIndex)_base, _add, _imm) 682 { 683 %(constructor)s; 684 } 685}}; 686 687def template LoadStoreImmConstructor {{ 688 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 689 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 690 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 691 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 692 { 693 %(constructor)s; 694 } 695}}; 696 697def template StoreExImmConstructor {{ 698 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 699 uint32_t _result, uint32_t _dest, uint32_t _base, 700 bool _add, int32_t _imm) 701 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 702 (IntRegIndex)_result, (IntRegIndex)_dest, 703 (IntRegIndex)_base, _add, _imm) 704 { 705 %(constructor)s; 706 } 707}}; 708 709def template LoadStoreDRegConstructor {{ 710 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 711 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 712 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 713 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 714 (IntRegIndex)_dest, (IntRegIndex)_dest2, 715 (IntRegIndex)_base, _add, 716 _shiftAmt, (ArmShiftType)_shiftType, 717 (IntRegIndex)_index) 718 { 719 %(constructor)s; 720 } 721}}; 722 723def template LoadStoreRegConstructor {{ 724 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 725 uint32_t _dest, uint32_t _base, bool _add, 726 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 727 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 728 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 729 _shiftAmt, (ArmShiftType)_shiftType, 730 (IntRegIndex)_index) 731 { 732 %(constructor)s; 733 } 734}}; 735