mem.isa revision 7120:d630089169f3 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
44def template LoadExecute {{
45    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46                                  Trace::InstRecord *traceData) const
47    {
48        Addr EA;
49        Fault fault = NoFault;
50
51        %(op_decl)s;
52        %(op_rd)s;
53        %(ea_code)s;
54
55        if (%(predicate_test)s)
56        {
57            if (fault == NoFault) {
58                fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
59                %(memacc_code)s;
60            }
61
62            if (fault == NoFault) {
63                %(op_wb)s;
64            }
65        }
66
67        return fault;
68    }
69}};
70
71def template StoreExecute {{
72    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
73                                  Trace::InstRecord *traceData) const
74    {
75        Addr EA;
76        Fault fault = NoFault;
77
78        %(op_decl)s;
79        %(op_rd)s;
80        %(ea_code)s;
81
82        if (%(predicate_test)s)
83        {
84            if (fault == NoFault) {
85                %(memacc_code)s;
86            }
87
88            if (fault == NoFault) {
89                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
90                                  memAccessFlags, NULL);
91                if (traceData) { traceData->setData(Mem); }
92            }
93
94            if (fault == NoFault) {
95                %(op_wb)s;
96            }
97        }
98
99        return fault;
100    }
101}};
102
103def template StoreInitiateAcc {{
104    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
105                                      Trace::InstRecord *traceData) const
106    {
107        Addr EA;
108        Fault fault = NoFault;
109
110        %(op_decl)s;
111        %(op_rd)s;
112        %(ea_code)s;
113
114        if (%(predicate_test)s)
115        {
116            if (fault == NoFault) {
117                %(memacc_code)s;
118            }
119
120            if (fault == NoFault) {
121                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
122                                  memAccessFlags, NULL);
123                if (traceData) { traceData->setData(Mem); }
124            }
125
126            // Need to write back any potential address register update
127            if (fault == NoFault) {
128                %(op_wb)s;
129            }
130        }
131
132        return fault;
133    }
134}};
135
136def template LoadInitiateAcc {{
137    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
138                                      Trace::InstRecord *traceData) const
139    {
140        Addr EA;
141        Fault fault = NoFault;
142
143        %(op_src_decl)s;
144        %(op_rd)s;
145        %(ea_code)s;
146
147        if (%(predicate_test)s)
148        {
149            if (fault == NoFault) {
150                fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
151            }
152        }
153
154        return fault;
155    }
156}};
157
158def template LoadCompleteAcc {{
159    Fault %(class_name)s::completeAcc(PacketPtr pkt,
160                                      %(CPU_exec_context)s *xc,
161                                      Trace::InstRecord *traceData) const
162    {
163        Fault fault = NoFault;
164
165        %(op_decl)s;
166        %(op_rd)s;
167
168        if (%(predicate_test)s)
169        {
170            // ARM instructions will not have a pkt if the predicate is false
171            Mem = pkt->get<typeof(Mem)>();
172
173            if (fault == NoFault) {
174                %(memacc_code)s;
175            }
176
177            if (fault == NoFault) {
178                %(op_wb)s;
179            }
180        }
181
182        return fault;
183    }
184}};
185
186def template StoreCompleteAcc {{
187    Fault %(class_name)s::completeAcc(PacketPtr pkt,
188                                      %(CPU_exec_context)s *xc,
189                                      Trace::InstRecord *traceData) const
190    {
191        Fault fault = NoFault;
192
193        %(op_decl)s;
194        %(op_rd)s;
195
196        if (%(predicate_test)s)
197        {
198            if (fault == NoFault) {
199                %(op_wb)s;
200            }
201        }
202
203        return fault;
204    }
205}};
206
207def template LoadStoreImmDeclare {{
208    /**
209     * Static instruction class for "%(mnemonic)s".
210     */
211    class %(class_name)s : public %(base_class)s
212    {
213      public:
214
215        /// Constructor.
216        %(class_name)s(ExtMachInst machInst,
217                uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
218
219        %(BasicExecDeclare)s
220
221        %(InitiateAccDeclare)s
222
223        %(CompleteAccDeclare)s
224    };
225}};
226
227def template LoadStoreRegDeclare {{
228    /**
229     * Static instruction class for "%(mnemonic)s".
230     */
231    class %(class_name)s : public %(base_class)s
232    {
233      public:
234
235        /// Constructor.
236        %(class_name)s(ExtMachInst machInst,
237                uint32_t _dest, uint32_t _base, bool _add,
238                int32_t _shiftAmt, uint32_t _shiftType,
239                uint32_t _index);
240
241        %(BasicExecDeclare)s
242
243        %(InitiateAccDeclare)s
244
245        %(CompleteAccDeclare)s
246    };
247}};
248
249def template InitiateAccDeclare {{
250    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
251}};
252
253def template CompleteAccDeclare {{
254    Fault completeAcc(PacketPtr,  %(CPU_exec_context)s *, Trace::InstRecord *) const;
255}};
256
257def template LoadStoreImmConstructor {{
258    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
259            uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
260         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
261                 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
262    {
263        %(constructor)s;
264    }
265}};
266
267def template LoadStoreRegConstructor {{
268    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
269            uint32_t _dest, uint32_t _base, bool _add,
270            int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
271         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
272                 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
273                 _shiftAmt, (ArmShiftType)_shiftType,
274                 (IntRegIndex)_index)
275    {
276        %(constructor)s;
277    }
278}};
279