mem.isa revision 8207
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37120Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447646Sgene.wu@arm.comdef template PanicExecute {{ 457646Sgene.wu@arm.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 467646Sgene.wu@arm.com Trace::InstRecord *traceData) const 477646Sgene.wu@arm.com { 487646Sgene.wu@arm.com panic("Execute function executed when it shouldn't be!\n"); 497646Sgene.wu@arm.com return NoFault; 507646Sgene.wu@arm.com } 517646Sgene.wu@arm.com}}; 527646Sgene.wu@arm.com 537646Sgene.wu@arm.comdef template PanicInitiateAcc {{ 547646Sgene.wu@arm.com Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 557646Sgene.wu@arm.com Trace::InstRecord *traceData) const 567646Sgene.wu@arm.com { 577646Sgene.wu@arm.com panic("InitiateAcc function executed when it shouldn't be!\n"); 587646Sgene.wu@arm.com return NoFault; 597646Sgene.wu@arm.com } 607646Sgene.wu@arm.com}}; 617646Sgene.wu@arm.com 627646Sgene.wu@arm.comdef template PanicCompleteAcc {{ 637646Sgene.wu@arm.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 647646Sgene.wu@arm.com %(CPU_exec_context)s *xc, 657646Sgene.wu@arm.com Trace::InstRecord *traceData) const 667646Sgene.wu@arm.com { 677646Sgene.wu@arm.com panic("CompleteAcc function executed when it shouldn't be!\n"); 687646Sgene.wu@arm.com return NoFault; 697646Sgene.wu@arm.com } 707646Sgene.wu@arm.com}}; 717646Sgene.wu@arm.com 727646Sgene.wu@arm.com 737205Sgblack@eecs.umich.edudef template SwapExecute {{ 747205Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 757205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 767205Sgblack@eecs.umich.edu { 777205Sgblack@eecs.umich.edu Addr EA; 787205Sgblack@eecs.umich.edu Fault fault = NoFault; 797205Sgblack@eecs.umich.edu 807205Sgblack@eecs.umich.edu %(op_decl)s; 817205Sgblack@eecs.umich.edu uint64_t memData = 0; 827205Sgblack@eecs.umich.edu %(op_rd)s; 837205Sgblack@eecs.umich.edu %(ea_code)s; 847205Sgblack@eecs.umich.edu 857205Sgblack@eecs.umich.edu if (%(predicate_test)s) 867205Sgblack@eecs.umich.edu { 877205Sgblack@eecs.umich.edu %(preacc_code)s; 887205Sgblack@eecs.umich.edu 897205Sgblack@eecs.umich.edu if (fault == NoFault) { 907205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 917205Sgblack@eecs.umich.edu EA, memAccessFlags, &memData); 927205Sgblack@eecs.umich.edu } 937205Sgblack@eecs.umich.edu 947205Sgblack@eecs.umich.edu if (fault == NoFault) { 957205Sgblack@eecs.umich.edu %(postacc_code)s; 967205Sgblack@eecs.umich.edu } 977205Sgblack@eecs.umich.edu 987205Sgblack@eecs.umich.edu if (fault == NoFault) { 997205Sgblack@eecs.umich.edu %(op_wb)s; 1007205Sgblack@eecs.umich.edu } 1017597Sminkyu.jeong@arm.com } else { 1027597Sminkyu.jeong@arm.com xc->setPredicate(false); 1037205Sgblack@eecs.umich.edu } 1047205Sgblack@eecs.umich.edu 1057205Sgblack@eecs.umich.edu return fault; 1067205Sgblack@eecs.umich.edu } 1077205Sgblack@eecs.umich.edu}}; 1087205Sgblack@eecs.umich.edu 1097205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 1107205Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1117205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1127205Sgblack@eecs.umich.edu { 1137205Sgblack@eecs.umich.edu Addr EA; 1147205Sgblack@eecs.umich.edu Fault fault = NoFault; 1157205Sgblack@eecs.umich.edu 1167205Sgblack@eecs.umich.edu %(op_decl)s; 1177205Sgblack@eecs.umich.edu uint64_t memData = 0; 1187205Sgblack@eecs.umich.edu %(op_rd)s; 1197205Sgblack@eecs.umich.edu %(ea_code)s; 1207205Sgblack@eecs.umich.edu 1217205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1227205Sgblack@eecs.umich.edu { 1237205Sgblack@eecs.umich.edu %(preacc_code)s; 1247205Sgblack@eecs.umich.edu 1257205Sgblack@eecs.umich.edu if (fault == NoFault) { 1267205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1277205Sgblack@eecs.umich.edu memAccessFlags, &memData); 1287205Sgblack@eecs.umich.edu } 1297597Sminkyu.jeong@arm.com } else { 1307597Sminkyu.jeong@arm.com xc->setPredicate(false); 1317205Sgblack@eecs.umich.edu } 1327205Sgblack@eecs.umich.edu 1337205Sgblack@eecs.umich.edu return fault; 1347205Sgblack@eecs.umich.edu } 1357205Sgblack@eecs.umich.edu}}; 1367205Sgblack@eecs.umich.edu 1377205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1387205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1397205Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1407205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1417205Sgblack@eecs.umich.edu { 1427205Sgblack@eecs.umich.edu Fault fault = NoFault; 1437205Sgblack@eecs.umich.edu 1447205Sgblack@eecs.umich.edu %(op_decl)s; 1457205Sgblack@eecs.umich.edu %(op_rd)s; 1467205Sgblack@eecs.umich.edu 1477205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1487205Sgblack@eecs.umich.edu { 1497205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1507205Sgblack@eecs.umich.edu uint64_t memData = pkt->get<typeof(Mem)>(); 1517205Sgblack@eecs.umich.edu 1527205Sgblack@eecs.umich.edu %(postacc_code)s; 1537205Sgblack@eecs.umich.edu 1547205Sgblack@eecs.umich.edu if (fault == NoFault) { 1557205Sgblack@eecs.umich.edu %(op_wb)s; 1567205Sgblack@eecs.umich.edu } 1577205Sgblack@eecs.umich.edu } 1587205Sgblack@eecs.umich.edu 1597205Sgblack@eecs.umich.edu return fault; 1607205Sgblack@eecs.umich.edu } 1617205Sgblack@eecs.umich.edu}}; 1627205Sgblack@eecs.umich.edu 1637119Sgblack@eecs.umich.edudef template LoadExecute {{ 1647119Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1657119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1667119Sgblack@eecs.umich.edu { 1677119Sgblack@eecs.umich.edu Addr EA; 1687119Sgblack@eecs.umich.edu Fault fault = NoFault; 1697119Sgblack@eecs.umich.edu 1707119Sgblack@eecs.umich.edu %(op_decl)s; 1717119Sgblack@eecs.umich.edu %(op_rd)s; 1727119Sgblack@eecs.umich.edu %(ea_code)s; 1737119Sgblack@eecs.umich.edu 1747119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1757119Sgblack@eecs.umich.edu { 1767119Sgblack@eecs.umich.edu if (fault == NoFault) { 1777119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1787119Sgblack@eecs.umich.edu %(memacc_code)s; 1797119Sgblack@eecs.umich.edu } 1807119Sgblack@eecs.umich.edu 1817119Sgblack@eecs.umich.edu if (fault == NoFault) { 1827119Sgblack@eecs.umich.edu %(op_wb)s; 1837119Sgblack@eecs.umich.edu } 1847597Sminkyu.jeong@arm.com } else { 1857597Sminkyu.jeong@arm.com xc->setPredicate(false); 1867119Sgblack@eecs.umich.edu } 1877119Sgblack@eecs.umich.edu 1887119Sgblack@eecs.umich.edu return fault; 1897119Sgblack@eecs.umich.edu } 1907119Sgblack@eecs.umich.edu}}; 1917119Sgblack@eecs.umich.edu 1927639Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 1937639Sgblack@eecs.umich.edu template <class Element> 1947639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 1957639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1967639Sgblack@eecs.umich.edu { 1977639Sgblack@eecs.umich.edu Addr EA; 1987639Sgblack@eecs.umich.edu Fault fault = NoFault; 1997639Sgblack@eecs.umich.edu 2007639Sgblack@eecs.umich.edu %(op_decl)s; 2017639Sgblack@eecs.umich.edu %(mem_decl)s; 2027639Sgblack@eecs.umich.edu %(op_rd)s; 2037639Sgblack@eecs.umich.edu %(ea_code)s; 2047639Sgblack@eecs.umich.edu 2057639Sgblack@eecs.umich.edu MemUnion memUnion; 2067639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2077639Sgblack@eecs.umich.edu 2087639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2097639Sgblack@eecs.umich.edu { 2107639Sgblack@eecs.umich.edu if (fault == NoFault) { 2117639Sgblack@eecs.umich.edu fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 2127639Sgblack@eecs.umich.edu %(memacc_code)s; 2137639Sgblack@eecs.umich.edu } 2147639Sgblack@eecs.umich.edu 2157639Sgblack@eecs.umich.edu if (fault == NoFault) { 2167639Sgblack@eecs.umich.edu %(op_wb)s; 2177639Sgblack@eecs.umich.edu } 2188072SGiacomo.Gabrielli@arm.com } else { 2198072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2207639Sgblack@eecs.umich.edu } 2217639Sgblack@eecs.umich.edu 2227639Sgblack@eecs.umich.edu return fault; 2237639Sgblack@eecs.umich.edu } 2247639Sgblack@eecs.umich.edu}}; 2257639Sgblack@eecs.umich.edu 2267120Sgblack@eecs.umich.edudef template StoreExecute {{ 2277120Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2287120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2297120Sgblack@eecs.umich.edu { 2307120Sgblack@eecs.umich.edu Addr EA; 2317120Sgblack@eecs.umich.edu Fault fault = NoFault; 2327120Sgblack@eecs.umich.edu 2337120Sgblack@eecs.umich.edu %(op_decl)s; 2347120Sgblack@eecs.umich.edu %(op_rd)s; 2357120Sgblack@eecs.umich.edu %(ea_code)s; 2367120Sgblack@eecs.umich.edu 2377120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2387120Sgblack@eecs.umich.edu { 2397120Sgblack@eecs.umich.edu if (fault == NoFault) { 2407120Sgblack@eecs.umich.edu %(memacc_code)s; 2417120Sgblack@eecs.umich.edu } 2427120Sgblack@eecs.umich.edu 2437120Sgblack@eecs.umich.edu if (fault == NoFault) { 2447120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2457120Sgblack@eecs.umich.edu memAccessFlags, NULL); 2467120Sgblack@eecs.umich.edu } 2477120Sgblack@eecs.umich.edu 2487120Sgblack@eecs.umich.edu if (fault == NoFault) { 2497120Sgblack@eecs.umich.edu %(op_wb)s; 2507120Sgblack@eecs.umich.edu } 2517597Sminkyu.jeong@arm.com } else { 2527597Sminkyu.jeong@arm.com xc->setPredicate(false); 2537120Sgblack@eecs.umich.edu } 2547120Sgblack@eecs.umich.edu 2557120Sgblack@eecs.umich.edu return fault; 2567120Sgblack@eecs.umich.edu } 2577120Sgblack@eecs.umich.edu}}; 2587120Sgblack@eecs.umich.edu 2597639Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2607639Sgblack@eecs.umich.edu template <class Element> 2617639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2627639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2637639Sgblack@eecs.umich.edu { 2647639Sgblack@eecs.umich.edu Addr EA; 2657639Sgblack@eecs.umich.edu Fault fault = NoFault; 2667639Sgblack@eecs.umich.edu 2677639Sgblack@eecs.umich.edu %(op_decl)s; 2687639Sgblack@eecs.umich.edu %(mem_decl)s; 2697639Sgblack@eecs.umich.edu %(op_rd)s; 2707639Sgblack@eecs.umich.edu %(ea_code)s; 2717639Sgblack@eecs.umich.edu 2727639Sgblack@eecs.umich.edu MemUnion memUnion; 2737639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2747639Sgblack@eecs.umich.edu 2757639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2767639Sgblack@eecs.umich.edu { 2777639Sgblack@eecs.umich.edu if (fault == NoFault) { 2787639Sgblack@eecs.umich.edu %(memacc_code)s; 2797639Sgblack@eecs.umich.edu } 2807639Sgblack@eecs.umich.edu 2817639Sgblack@eecs.umich.edu if (fault == NoFault) { 2827639Sgblack@eecs.umich.edu fault = xc->writeBytes(dataPtr, %(size)d, EA, 2837639Sgblack@eecs.umich.edu memAccessFlags, NULL); 2847639Sgblack@eecs.umich.edu } 2857639Sgblack@eecs.umich.edu 2867639Sgblack@eecs.umich.edu if (fault == NoFault) { 2877639Sgblack@eecs.umich.edu %(op_wb)s; 2887639Sgblack@eecs.umich.edu } 2898072SGiacomo.Gabrielli@arm.com } else { 2908072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2917639Sgblack@eecs.umich.edu } 2927639Sgblack@eecs.umich.edu 2937639Sgblack@eecs.umich.edu return fault; 2947639Sgblack@eecs.umich.edu } 2957639Sgblack@eecs.umich.edu}}; 2967639Sgblack@eecs.umich.edu 2977303Sgblack@eecs.umich.edudef template StoreExExecute {{ 2987303Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2997303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3007303Sgblack@eecs.umich.edu { 3017303Sgblack@eecs.umich.edu Addr EA; 3027303Sgblack@eecs.umich.edu Fault fault = NoFault; 3037303Sgblack@eecs.umich.edu 3047303Sgblack@eecs.umich.edu %(op_decl)s; 3057303Sgblack@eecs.umich.edu %(op_rd)s; 3067303Sgblack@eecs.umich.edu %(ea_code)s; 3077303Sgblack@eecs.umich.edu 3087303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3097303Sgblack@eecs.umich.edu { 3107303Sgblack@eecs.umich.edu if (fault == NoFault) { 3117303Sgblack@eecs.umich.edu %(memacc_code)s; 3127303Sgblack@eecs.umich.edu } 3137303Sgblack@eecs.umich.edu 3147303Sgblack@eecs.umich.edu uint64_t writeResult; 3157303Sgblack@eecs.umich.edu 3167303Sgblack@eecs.umich.edu if (fault == NoFault) { 3177303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3187303Sgblack@eecs.umich.edu memAccessFlags, &writeResult); 3197303Sgblack@eecs.umich.edu } 3207303Sgblack@eecs.umich.edu 3217303Sgblack@eecs.umich.edu if (fault == NoFault) { 3227303Sgblack@eecs.umich.edu %(postacc_code)s; 3237303Sgblack@eecs.umich.edu } 3247303Sgblack@eecs.umich.edu 3257303Sgblack@eecs.umich.edu if (fault == NoFault) { 3267303Sgblack@eecs.umich.edu %(op_wb)s; 3277303Sgblack@eecs.umich.edu } 3287597Sminkyu.jeong@arm.com } else { 3297597Sminkyu.jeong@arm.com xc->setPredicate(false); 3307303Sgblack@eecs.umich.edu } 3317303Sgblack@eecs.umich.edu 3327303Sgblack@eecs.umich.edu return fault; 3337303Sgblack@eecs.umich.edu } 3347303Sgblack@eecs.umich.edu}}; 3357303Sgblack@eecs.umich.edu 3367303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 3377303Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3387303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3397303Sgblack@eecs.umich.edu { 3407303Sgblack@eecs.umich.edu Addr EA; 3417303Sgblack@eecs.umich.edu Fault fault = NoFault; 3427303Sgblack@eecs.umich.edu 3437303Sgblack@eecs.umich.edu %(op_decl)s; 3447303Sgblack@eecs.umich.edu %(op_rd)s; 3457303Sgblack@eecs.umich.edu %(ea_code)s; 3467303Sgblack@eecs.umich.edu 3477303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3487303Sgblack@eecs.umich.edu { 3497303Sgblack@eecs.umich.edu if (fault == NoFault) { 3507303Sgblack@eecs.umich.edu %(memacc_code)s; 3517303Sgblack@eecs.umich.edu } 3527303Sgblack@eecs.umich.edu 3537303Sgblack@eecs.umich.edu if (fault == NoFault) { 3547303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3557303Sgblack@eecs.umich.edu memAccessFlags, NULL); 3567303Sgblack@eecs.umich.edu } 3577597Sminkyu.jeong@arm.com } else { 3587597Sminkyu.jeong@arm.com xc->setPredicate(false); 3597303Sgblack@eecs.umich.edu } 3607408Sgblack@eecs.umich.edu 3617303Sgblack@eecs.umich.edu return fault; 3627303Sgblack@eecs.umich.edu } 3637303Sgblack@eecs.umich.edu}}; 3647303Sgblack@eecs.umich.edu 3657120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 3667120Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3677120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3687120Sgblack@eecs.umich.edu { 3697120Sgblack@eecs.umich.edu Addr EA; 3707120Sgblack@eecs.umich.edu Fault fault = NoFault; 3717120Sgblack@eecs.umich.edu 3727120Sgblack@eecs.umich.edu %(op_decl)s; 3737120Sgblack@eecs.umich.edu %(op_rd)s; 3747120Sgblack@eecs.umich.edu %(ea_code)s; 3757120Sgblack@eecs.umich.edu 3767120Sgblack@eecs.umich.edu if (%(predicate_test)s) 3777120Sgblack@eecs.umich.edu { 3787120Sgblack@eecs.umich.edu if (fault == NoFault) { 3797120Sgblack@eecs.umich.edu %(memacc_code)s; 3807120Sgblack@eecs.umich.edu } 3817120Sgblack@eecs.umich.edu 3827120Sgblack@eecs.umich.edu if (fault == NoFault) { 3837120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3847120Sgblack@eecs.umich.edu memAccessFlags, NULL); 3857120Sgblack@eecs.umich.edu } 3867597Sminkyu.jeong@arm.com } else { 3877597Sminkyu.jeong@arm.com xc->setPredicate(false); 3887120Sgblack@eecs.umich.edu } 3897120Sgblack@eecs.umich.edu 3907120Sgblack@eecs.umich.edu return fault; 3917120Sgblack@eecs.umich.edu } 3927120Sgblack@eecs.umich.edu}}; 3937120Sgblack@eecs.umich.edu 3947639Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 3957639Sgblack@eecs.umich.edu template <class Element> 3967639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 3977639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 3987639Sgblack@eecs.umich.edu { 3997639Sgblack@eecs.umich.edu Addr EA; 4007639Sgblack@eecs.umich.edu Fault fault = NoFault; 4017639Sgblack@eecs.umich.edu 4027639Sgblack@eecs.umich.edu %(op_decl)s; 4037639Sgblack@eecs.umich.edu %(mem_decl)s; 4047639Sgblack@eecs.umich.edu %(op_rd)s; 4057639Sgblack@eecs.umich.edu %(ea_code)s; 4067639Sgblack@eecs.umich.edu 4077639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4087639Sgblack@eecs.umich.edu { 4097639Sgblack@eecs.umich.edu MemUnion memUnion; 4107639Sgblack@eecs.umich.edu if (fault == NoFault) { 4117639Sgblack@eecs.umich.edu %(memacc_code)s; 4127639Sgblack@eecs.umich.edu } 4137639Sgblack@eecs.umich.edu 4147639Sgblack@eecs.umich.edu if (fault == NoFault) { 4157639Sgblack@eecs.umich.edu fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 4167639Sgblack@eecs.umich.edu memAccessFlags, NULL); 4177639Sgblack@eecs.umich.edu } 4188072SGiacomo.Gabrielli@arm.com } else { 4198072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4207639Sgblack@eecs.umich.edu } 4217639Sgblack@eecs.umich.edu 4227639Sgblack@eecs.umich.edu return fault; 4237639Sgblack@eecs.umich.edu } 4247639Sgblack@eecs.umich.edu}}; 4257639Sgblack@eecs.umich.edu 4267119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 4277119Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4287119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4297119Sgblack@eecs.umich.edu { 4307119Sgblack@eecs.umich.edu Addr EA; 4317119Sgblack@eecs.umich.edu Fault fault = NoFault; 4327119Sgblack@eecs.umich.edu 4337119Sgblack@eecs.umich.edu %(op_src_decl)s; 4347119Sgblack@eecs.umich.edu %(op_rd)s; 4357119Sgblack@eecs.umich.edu %(ea_code)s; 4367119Sgblack@eecs.umich.edu 4377119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4387119Sgblack@eecs.umich.edu { 4397119Sgblack@eecs.umich.edu if (fault == NoFault) { 4407119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 4417119Sgblack@eecs.umich.edu } 4427597Sminkyu.jeong@arm.com } else { 4437597Sminkyu.jeong@arm.com xc->setPredicate(false); 4447119Sgblack@eecs.umich.edu } 4457119Sgblack@eecs.umich.edu 4467119Sgblack@eecs.umich.edu return fault; 4477119Sgblack@eecs.umich.edu } 4487119Sgblack@eecs.umich.edu}}; 4497119Sgblack@eecs.umich.edu 4507639Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 4517639Sgblack@eecs.umich.edu template <class Element> 4527639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 4537639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 4547639Sgblack@eecs.umich.edu { 4557639Sgblack@eecs.umich.edu Addr EA; 4567639Sgblack@eecs.umich.edu Fault fault = NoFault; 4577639Sgblack@eecs.umich.edu 4588207SAli.Saidi@ARM.com %(op_decl)s; 4598207SAli.Saidi@ARM.com %(mem_decl)s; 4607639Sgblack@eecs.umich.edu %(op_rd)s; 4617639Sgblack@eecs.umich.edu %(ea_code)s; 4627639Sgblack@eecs.umich.edu 4638207SAli.Saidi@ARM.com MemUnion memUnion; 4648207SAli.Saidi@ARM.com uint8_t *dataPtr = memUnion.bytes; 4658207SAli.Saidi@ARM.com 4667639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4677639Sgblack@eecs.umich.edu { 4687639Sgblack@eecs.umich.edu if (fault == NoFault) { 4698207SAli.Saidi@ARM.com fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 4707639Sgblack@eecs.umich.edu } 4718072SGiacomo.Gabrielli@arm.com } else { 4728072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4737639Sgblack@eecs.umich.edu } 4747639Sgblack@eecs.umich.edu 4757639Sgblack@eecs.umich.edu return fault; 4767639Sgblack@eecs.umich.edu } 4777639Sgblack@eecs.umich.edu}}; 4787639Sgblack@eecs.umich.edu 4797119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 4807119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 4817119Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 4827119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4837119Sgblack@eecs.umich.edu { 4847119Sgblack@eecs.umich.edu Fault fault = NoFault; 4857119Sgblack@eecs.umich.edu 4867119Sgblack@eecs.umich.edu %(op_decl)s; 4877119Sgblack@eecs.umich.edu %(op_rd)s; 4887119Sgblack@eecs.umich.edu 4897119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4907119Sgblack@eecs.umich.edu { 4917119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 4927119Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 4937119Sgblack@eecs.umich.edu 4947119Sgblack@eecs.umich.edu if (fault == NoFault) { 4957119Sgblack@eecs.umich.edu %(memacc_code)s; 4967119Sgblack@eecs.umich.edu } 4977119Sgblack@eecs.umich.edu 4987119Sgblack@eecs.umich.edu if (fault == NoFault) { 4997119Sgblack@eecs.umich.edu %(op_wb)s; 5007119Sgblack@eecs.umich.edu } 5017119Sgblack@eecs.umich.edu } 5027119Sgblack@eecs.umich.edu 5037119Sgblack@eecs.umich.edu return fault; 5047119Sgblack@eecs.umich.edu } 5057119Sgblack@eecs.umich.edu}}; 5067119Sgblack@eecs.umich.edu 5077639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5087639Sgblack@eecs.umich.edu template <class Element> 5097639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5107639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 5117639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5127639Sgblack@eecs.umich.edu { 5137639Sgblack@eecs.umich.edu Fault fault = NoFault; 5147639Sgblack@eecs.umich.edu 5157639Sgblack@eecs.umich.edu %(mem_decl)s; 5167639Sgblack@eecs.umich.edu %(op_decl)s; 5177639Sgblack@eecs.umich.edu %(op_rd)s; 5187639Sgblack@eecs.umich.edu 5197639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5207639Sgblack@eecs.umich.edu { 5217639Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5227639Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5237639Sgblack@eecs.umich.edu 5247639Sgblack@eecs.umich.edu if (fault == NoFault) { 5257639Sgblack@eecs.umich.edu %(memacc_code)s; 5267639Sgblack@eecs.umich.edu } 5277639Sgblack@eecs.umich.edu 5287639Sgblack@eecs.umich.edu if (fault == NoFault) { 5297639Sgblack@eecs.umich.edu %(op_wb)s; 5307639Sgblack@eecs.umich.edu } 5317639Sgblack@eecs.umich.edu } 5327639Sgblack@eecs.umich.edu 5337639Sgblack@eecs.umich.edu return fault; 5347639Sgblack@eecs.umich.edu } 5357639Sgblack@eecs.umich.edu}}; 5367639Sgblack@eecs.umich.edu 5377120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 5387120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5397120Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5407120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5417120Sgblack@eecs.umich.edu { 5427712Sgblack@eecs.umich.edu return NoFault; 5437120Sgblack@eecs.umich.edu } 5447120Sgblack@eecs.umich.edu}}; 5457120Sgblack@eecs.umich.edu 5467639Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 5477639Sgblack@eecs.umich.edu template <class Element> 5487639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5497639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 5507639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5517639Sgblack@eecs.umich.edu { 5527712Sgblack@eecs.umich.edu return NoFault; 5537639Sgblack@eecs.umich.edu } 5547639Sgblack@eecs.umich.edu}}; 5557639Sgblack@eecs.umich.edu 5567303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 5577303Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5587303Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5597303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5607303Sgblack@eecs.umich.edu { 5617303Sgblack@eecs.umich.edu Fault fault = NoFault; 5627303Sgblack@eecs.umich.edu 5637303Sgblack@eecs.umich.edu %(op_decl)s; 5647303Sgblack@eecs.umich.edu %(op_rd)s; 5657303Sgblack@eecs.umich.edu 5667303Sgblack@eecs.umich.edu if (%(predicate_test)s) 5677303Sgblack@eecs.umich.edu { 5687303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 5697303Sgblack@eecs.umich.edu %(postacc_code)s; 5707303Sgblack@eecs.umich.edu 5717303Sgblack@eecs.umich.edu if (fault == NoFault) { 5727303Sgblack@eecs.umich.edu %(op_wb)s; 5737303Sgblack@eecs.umich.edu } 5747303Sgblack@eecs.umich.edu } 5757303Sgblack@eecs.umich.edu 5767303Sgblack@eecs.umich.edu return fault; 5777303Sgblack@eecs.umich.edu } 5787303Sgblack@eecs.umich.edu}}; 5797303Sgblack@eecs.umich.edu 5807291Sgblack@eecs.umich.edudef template RfeDeclare {{ 5817291Sgblack@eecs.umich.edu /** 5827291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5837291Sgblack@eecs.umich.edu */ 5847291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5857291Sgblack@eecs.umich.edu { 5867291Sgblack@eecs.umich.edu public: 5877291Sgblack@eecs.umich.edu 5887291Sgblack@eecs.umich.edu /// Constructor. 5897291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5907291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 5917291Sgblack@eecs.umich.edu 5927291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5937291Sgblack@eecs.umich.edu 5947291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5957291Sgblack@eecs.umich.edu 5967291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5977291Sgblack@eecs.umich.edu }; 5987291Sgblack@eecs.umich.edu}}; 5997291Sgblack@eecs.umich.edu 6007312Sgblack@eecs.umich.edudef template SrsDeclare {{ 6017312Sgblack@eecs.umich.edu /** 6027312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6037312Sgblack@eecs.umich.edu */ 6047312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6057312Sgblack@eecs.umich.edu { 6067312Sgblack@eecs.umich.edu public: 6077312Sgblack@eecs.umich.edu 6087312Sgblack@eecs.umich.edu /// Constructor. 6097312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6107312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6117312Sgblack@eecs.umich.edu 6127312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6137312Sgblack@eecs.umich.edu 6147312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6157312Sgblack@eecs.umich.edu 6167312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6177312Sgblack@eecs.umich.edu }; 6187312Sgblack@eecs.umich.edu}}; 6197312Sgblack@eecs.umich.edu 6207205Sgblack@eecs.umich.edudef template SwapDeclare {{ 6217205Sgblack@eecs.umich.edu /** 6227205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6237205Sgblack@eecs.umich.edu */ 6247205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6257205Sgblack@eecs.umich.edu { 6267205Sgblack@eecs.umich.edu public: 6277205Sgblack@eecs.umich.edu 6287205Sgblack@eecs.umich.edu /// Constructor. 6297205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6307205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 6317205Sgblack@eecs.umich.edu 6327205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6337205Sgblack@eecs.umich.edu 6347205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6357205Sgblack@eecs.umich.edu 6367205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6377205Sgblack@eecs.umich.edu }; 6387205Sgblack@eecs.umich.edu}}; 6397205Sgblack@eecs.umich.edu 6407279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 6417279Sgblack@eecs.umich.edu /** 6427279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6437279Sgblack@eecs.umich.edu */ 6447279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6457279Sgblack@eecs.umich.edu { 6467279Sgblack@eecs.umich.edu public: 6477279Sgblack@eecs.umich.edu 6487279Sgblack@eecs.umich.edu /// Constructor. 6497279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6507279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6517279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6527279Sgblack@eecs.umich.edu 6537279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6547279Sgblack@eecs.umich.edu 6557279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6567279Sgblack@eecs.umich.edu 6577279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6587279Sgblack@eecs.umich.edu }; 6597279Sgblack@eecs.umich.edu}}; 6607279Sgblack@eecs.umich.edu 6617303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 6627303Sgblack@eecs.umich.edu /** 6637303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6647303Sgblack@eecs.umich.edu */ 6657303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6667303Sgblack@eecs.umich.edu { 6677303Sgblack@eecs.umich.edu public: 6687303Sgblack@eecs.umich.edu 6697303Sgblack@eecs.umich.edu /// Constructor. 6707303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6717303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 6727303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6737303Sgblack@eecs.umich.edu 6747303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6757303Sgblack@eecs.umich.edu 6767303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6777303Sgblack@eecs.umich.edu 6787303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6797303Sgblack@eecs.umich.edu }; 6807303Sgblack@eecs.umich.edu}}; 6817303Sgblack@eecs.umich.edu 6827119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 6837119Sgblack@eecs.umich.edu /** 6847119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6857119Sgblack@eecs.umich.edu */ 6867119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6877119Sgblack@eecs.umich.edu { 6887119Sgblack@eecs.umich.edu public: 6897119Sgblack@eecs.umich.edu 6907119Sgblack@eecs.umich.edu /// Constructor. 6917119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6927119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 6937119Sgblack@eecs.umich.edu 6947119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6957119Sgblack@eecs.umich.edu 6967119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6977119Sgblack@eecs.umich.edu 6987119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6997119Sgblack@eecs.umich.edu }; 7007119Sgblack@eecs.umich.edu}}; 7017119Sgblack@eecs.umich.edu 7027303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 7037303Sgblack@eecs.umich.edu /** 7047303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7057303Sgblack@eecs.umich.edu */ 7067303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7077303Sgblack@eecs.umich.edu { 7087303Sgblack@eecs.umich.edu public: 7097303Sgblack@eecs.umich.edu 7107303Sgblack@eecs.umich.edu /// Constructor. 7117303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7127303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7137303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7147303Sgblack@eecs.umich.edu 7157303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7167303Sgblack@eecs.umich.edu 7177303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7187303Sgblack@eecs.umich.edu 7197303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7207303Sgblack@eecs.umich.edu }; 7217303Sgblack@eecs.umich.edu}}; 7227303Sgblack@eecs.umich.edu 7237646Sgene.wu@arm.comdef template StoreDRegDeclare {{ 7247279Sgblack@eecs.umich.edu /** 7257279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7267279Sgblack@eecs.umich.edu */ 7277279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7287279Sgblack@eecs.umich.edu { 7297279Sgblack@eecs.umich.edu public: 7307279Sgblack@eecs.umich.edu 7317279Sgblack@eecs.umich.edu /// Constructor. 7327279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7337279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7347279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 7357279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7367279Sgblack@eecs.umich.edu uint32_t _index); 7377279Sgblack@eecs.umich.edu 7387279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7397279Sgblack@eecs.umich.edu 7407279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7417279Sgblack@eecs.umich.edu 7427279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7437279Sgblack@eecs.umich.edu }; 7447279Sgblack@eecs.umich.edu}}; 7457279Sgblack@eecs.umich.edu 7467646Sgene.wu@arm.comdef template StoreRegDeclare {{ 7477119Sgblack@eecs.umich.edu /** 7487119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7497119Sgblack@eecs.umich.edu */ 7507119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7517119Sgblack@eecs.umich.edu { 7527119Sgblack@eecs.umich.edu public: 7537119Sgblack@eecs.umich.edu 7547119Sgblack@eecs.umich.edu /// Constructor. 7557119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7567119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 7577119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7587119Sgblack@eecs.umich.edu uint32_t _index); 7597119Sgblack@eecs.umich.edu 7607119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7617119Sgblack@eecs.umich.edu 7627119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7637119Sgblack@eecs.umich.edu 7647119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7657119Sgblack@eecs.umich.edu }; 7667119Sgblack@eecs.umich.edu}}; 7677119Sgblack@eecs.umich.edu 7687646Sgene.wu@arm.comdef template LoadDRegDeclare {{ 7697646Sgene.wu@arm.com /** 7707646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 7717646Sgene.wu@arm.com */ 7727646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 7737646Sgene.wu@arm.com { 7747646Sgene.wu@arm.com public: 7757646Sgene.wu@arm.com 7767646Sgene.wu@arm.com /// Constructor. 7777646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 7787646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, 7797646Sgene.wu@arm.com uint32_t _base, bool _add, 7807646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 7817646Sgene.wu@arm.com uint32_t _index); 7827646Sgene.wu@arm.com 7837646Sgene.wu@arm.com %(BasicExecDeclare)s 7847646Sgene.wu@arm.com 7857646Sgene.wu@arm.com %(InitiateAccDeclare)s 7867646Sgene.wu@arm.com 7877646Sgene.wu@arm.com %(CompleteAccDeclare)s 7887646Sgene.wu@arm.com }; 7897646Sgene.wu@arm.com}}; 7907646Sgene.wu@arm.com 7917646Sgene.wu@arm.comdef template LoadRegDeclare {{ 7927646Sgene.wu@arm.com /** 7937646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 7947646Sgene.wu@arm.com */ 7957646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 7967646Sgene.wu@arm.com { 7977646Sgene.wu@arm.com public: 7987646Sgene.wu@arm.com 7997646Sgene.wu@arm.com /// Constructor. 8007646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8017646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 8027646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 8037646Sgene.wu@arm.com uint32_t _index); 8047646Sgene.wu@arm.com 8057646Sgene.wu@arm.com %(BasicExecDeclare)s 8067646Sgene.wu@arm.com 8077646Sgene.wu@arm.com %(InitiateAccDeclare)s 8087646Sgene.wu@arm.com 8097646Sgene.wu@arm.com %(CompleteAccDeclare)s 8107646Sgene.wu@arm.com }; 8117646Sgene.wu@arm.com}}; 8127646Sgene.wu@arm.com 8137646Sgene.wu@arm.comdef template LoadImmDeclare {{ 8147646Sgene.wu@arm.com /** 8157646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8167646Sgene.wu@arm.com */ 8177646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8187646Sgene.wu@arm.com { 8197646Sgene.wu@arm.com public: 8207646Sgene.wu@arm.com 8217646Sgene.wu@arm.com /// Constructor. 8227646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8237646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8247646Sgene.wu@arm.com 8257646Sgene.wu@arm.com %(BasicExecDeclare)s 8267646Sgene.wu@arm.com 8277646Sgene.wu@arm.com %(InitiateAccDeclare)s 8287646Sgene.wu@arm.com 8297646Sgene.wu@arm.com %(CompleteAccDeclare)s 8307646Sgene.wu@arm.com }; 8317646Sgene.wu@arm.com}}; 8327646Sgene.wu@arm.com 8337119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 8347119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 8357119Sgblack@eecs.umich.edu}}; 8367119Sgblack@eecs.umich.edu 8377119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 8387119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 8397119Sgblack@eecs.umich.edu}}; 8407119Sgblack@eecs.umich.edu 8417291Sgblack@eecs.umich.edudef template RfeConstructor {{ 8427291Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8438140SMatt.Horsnell@arm.com uint32_t _base, int _mode, bool _wb) 8448140SMatt.Horsnell@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8458140SMatt.Horsnell@arm.com (IntRegIndex)_base, (AddrMode)_mode, _wb) 8467291Sgblack@eecs.umich.edu { 8477291Sgblack@eecs.umich.edu %(constructor)s; 8487848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8497848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 8507848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8517848SAli.Saidi@ARM.com } 8527848SAli.Saidi@ARM.com } 8537646Sgene.wu@arm.com#if %(use_uops)d 8548140SMatt.Horsnell@arm.com uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d]; 8558140SMatt.Horsnell@arm.com int uopIdx = 0; 8568140SMatt.Horsnell@arm.com uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb); 8578140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8588140SMatt.Horsnell@arm.com#if %(use_wb)d 8598140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(wb_decl)s; 8608140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8618140SMatt.Horsnell@arm.com#endif 8628140SMatt.Horsnell@arm.com#if %(use_pc)d 8638140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(pc_decl)s; 8648140SMatt.Horsnell@arm.com#endif 8658140SMatt.Horsnell@arm.com uops[uopIdx]->setLastMicroop(); 8667646Sgene.wu@arm.com#endif 8677291Sgblack@eecs.umich.edu } 8687291Sgblack@eecs.umich.edu}}; 8697291Sgblack@eecs.umich.edu 8707312Sgblack@eecs.umich.edudef template SrsConstructor {{ 8717312Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8727312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 8737312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8747312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 8757312Sgblack@eecs.umich.edu { 8767312Sgblack@eecs.umich.edu %(constructor)s; 8777848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8787848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 8797848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8807848SAli.Saidi@ARM.com } 8817848SAli.Saidi@ARM.com } 8827646Sgene.wu@arm.com#if %(use_uops)d 8837646Sgene.wu@arm.com assert(numMicroops >= 2); 8847646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 8857646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 8867724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 8877646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 8887646Sgene.wu@arm.com uops[1]->setLastMicroop(); 8897646Sgene.wu@arm.com#endif 8907312Sgblack@eecs.umich.edu } 8917312Sgblack@eecs.umich.edu}}; 8927312Sgblack@eecs.umich.edu 8937205Sgblack@eecs.umich.edudef template SwapConstructor {{ 8947205Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8957205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 8967205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8977205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 8987205Sgblack@eecs.umich.edu { 8997205Sgblack@eecs.umich.edu %(constructor)s; 9007848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9017848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9027848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9037848SAli.Saidi@ARM.com } 9047848SAli.Saidi@ARM.com } 9057205Sgblack@eecs.umich.edu } 9067205Sgblack@eecs.umich.edu}}; 9077205Sgblack@eecs.umich.edu 9087279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 9097279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9107279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9117279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9127279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9137279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9147279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9157279Sgblack@eecs.umich.edu { 9167279Sgblack@eecs.umich.edu %(constructor)s; 9177848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9187848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9197848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9207848SAli.Saidi@ARM.com } 9217848SAli.Saidi@ARM.com } 9227646Sgene.wu@arm.com#if %(use_uops)d 9237646Sgene.wu@arm.com assert(numMicroops >= 2); 9247646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9257646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 9267724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9277646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9287646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9297646Sgene.wu@arm.com#endif 9307279Sgblack@eecs.umich.edu } 9317279Sgblack@eecs.umich.edu}}; 9327279Sgblack@eecs.umich.edu 9337303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 9347303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9357303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 9367303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9377303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9387303Sgblack@eecs.umich.edu (IntRegIndex)_result, 9397303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9407303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9417303Sgblack@eecs.umich.edu { 9427303Sgblack@eecs.umich.edu %(constructor)s; 9437848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9447848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9457848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9467848SAli.Saidi@ARM.com } 9477848SAli.Saidi@ARM.com } 9487646Sgene.wu@arm.com#if %(use_uops)d 9497646Sgene.wu@arm.com assert(numMicroops >= 2); 9507646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9517646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 9527646Sgene.wu@arm.com _base, _add, _imm); 9537724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9547646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9557646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9567646Sgene.wu@arm.com#endif 9577303Sgblack@eecs.umich.edu } 9587303Sgblack@eecs.umich.edu}}; 9597303Sgblack@eecs.umich.edu 9607119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 9617119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9627119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 9637119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9647119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 9657119Sgblack@eecs.umich.edu { 9667119Sgblack@eecs.umich.edu %(constructor)s; 9677848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9687848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9697848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9707848SAli.Saidi@ARM.com } 9717848SAli.Saidi@ARM.com } 9727646Sgene.wu@arm.com#if %(use_uops)d 9737646Sgene.wu@arm.com assert(numMicroops >= 2); 9747646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9757646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 9767724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9777646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9787646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9797646Sgene.wu@arm.com#endif 9807119Sgblack@eecs.umich.edu } 9817119Sgblack@eecs.umich.edu}}; 9827119Sgblack@eecs.umich.edu 9837303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 9847303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9857303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 9867303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 9877303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9887303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 9897303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9907303Sgblack@eecs.umich.edu { 9917303Sgblack@eecs.umich.edu %(constructor)s; 9927848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9937848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9947848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9957848SAli.Saidi@ARM.com } 9967848SAli.Saidi@ARM.com } 9977646Sgene.wu@arm.com#if %(use_uops)d 9987646Sgene.wu@arm.com assert(numMicroops >= 2); 9997646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10007646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, 10017646Sgene.wu@arm.com _base, _add, _imm); 10027724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10037646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10047646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10057646Sgene.wu@arm.com#endif 10067303Sgblack@eecs.umich.edu } 10077303Sgblack@eecs.umich.edu}}; 10087303Sgblack@eecs.umich.edu 10097646Sgene.wu@arm.comdef template StoreDRegConstructor {{ 10107279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10117279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10127279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10137279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10147279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10157279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10167279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10177279Sgblack@eecs.umich.edu (IntRegIndex)_index) 10187279Sgblack@eecs.umich.edu { 10197279Sgblack@eecs.umich.edu %(constructor)s; 10207848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10217848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10227848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10237848SAli.Saidi@ARM.com } 10247848SAli.Saidi@ARM.com } 10257646Sgene.wu@arm.com#if %(use_uops)d 10267646Sgene.wu@arm.com assert(numMicroops >= 2); 10277646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10287646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10297646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10307724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10317646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10327646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10337646Sgene.wu@arm.com#endif 10347279Sgblack@eecs.umich.edu } 10357279Sgblack@eecs.umich.edu}}; 10367279Sgblack@eecs.umich.edu 10377646Sgene.wu@arm.comdef template StoreRegConstructor {{ 10387119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10397119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 10407119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10417119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10427119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 10437119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10447119Sgblack@eecs.umich.edu (IntRegIndex)_index) 10457119Sgblack@eecs.umich.edu { 10467119Sgblack@eecs.umich.edu %(constructor)s; 10477848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10487848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10497848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10507848SAli.Saidi@ARM.com } 10517848SAli.Saidi@ARM.com } 10527646Sgene.wu@arm.com#if %(use_uops)d 10537646Sgene.wu@arm.com assert(numMicroops >= 2); 10547646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10557646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 10567646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10577724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10587646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10597646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10607646Sgene.wu@arm.com#endif 10617119Sgblack@eecs.umich.edu } 10627119Sgblack@eecs.umich.edu}}; 10637646Sgene.wu@arm.com 10647646Sgene.wu@arm.comdef template LoadDRegConstructor {{ 10657646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10667646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10677646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10687646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10697646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_dest2, 10707646Sgene.wu@arm.com (IntRegIndex)_base, _add, 10717646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 10727646Sgene.wu@arm.com (IntRegIndex)_index) 10737646Sgene.wu@arm.com { 10747646Sgene.wu@arm.com %(constructor)s; 10757848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10767848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10777848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10787848SAli.Saidi@ARM.com } 10797848SAli.Saidi@ARM.com } 10807646Sgene.wu@arm.com#if %(use_uops)d 10817646Sgene.wu@arm.com assert(numMicroops >= 2); 10827646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10837646Sgene.wu@arm.com if ((_dest == _index) || (_dest2 == _index)) { 10847646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 10857646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 10867724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10877646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10887646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10897724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 10907646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 10917646Sgene.wu@arm.com uops[2]->setLastMicroop(); 10927646Sgene.wu@arm.com } else { 10937646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 10947646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10957646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10967724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10977646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10987646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10997646Sgene.wu@arm.com } 11007646Sgene.wu@arm.com#endif 11017646Sgene.wu@arm.com } 11027646Sgene.wu@arm.com}}; 11037646Sgene.wu@arm.com 11047646Sgene.wu@arm.comdef template LoadRegConstructor {{ 11057646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11067646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 11077646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11087646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11097646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11107646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11117646Sgene.wu@arm.com (IntRegIndex)_index) 11127646Sgene.wu@arm.com { 11137646Sgene.wu@arm.com %(constructor)s; 11148203SAli.Saidi@ARM.com bool conditional = false; 11157848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11168203SAli.Saidi@ARM.com conditional = true; 11177848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11187848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11197848SAli.Saidi@ARM.com } 11207848SAli.Saidi@ARM.com } 11217646Sgene.wu@arm.com#if %(use_uops)d 11227646Sgene.wu@arm.com assert(numMicroops >= 2); 11237646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11247646Sgene.wu@arm.com if (_dest == INTREG_PC) { 11257646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11267646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11277646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11287724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11297646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11307724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11317646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11328203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 11338203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 11348203SAli.Saidi@ARM.com if (conditional) 11358203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 11368203SAli.Saidi@ARM.com else 11378203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 11387646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11397646Sgene.wu@arm.com } else if(_dest == _index) { 11407646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11417646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11427724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11437646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 11447646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11457724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11467646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11477646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11487646Sgene.wu@arm.com } else { 11497646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11507646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11517646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11527724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11537646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11547646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11557646Sgene.wu@arm.com 11567646Sgene.wu@arm.com } 11577646Sgene.wu@arm.com#endif 11587646Sgene.wu@arm.com } 11597646Sgene.wu@arm.com}}; 11607646Sgene.wu@arm.com 11617646Sgene.wu@arm.comdef template LoadImmConstructor {{ 11627646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11637646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 11647646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11657646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 11667646Sgene.wu@arm.com { 11677646Sgene.wu@arm.com %(constructor)s; 11688203SAli.Saidi@ARM.com bool conditional = false; 11697848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11708203SAli.Saidi@ARM.com conditional = true; 11717848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11727848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11737848SAli.Saidi@ARM.com } 11747848SAli.Saidi@ARM.com } 11757646Sgene.wu@arm.com#if %(use_uops)d 11767646Sgene.wu@arm.com assert(numMicroops >= 2); 11777646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11787646Sgene.wu@arm.com if (_dest == INTREG_PC) { 11797646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11807646Sgene.wu@arm.com _imm); 11817724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11827646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11837724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11847646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11858203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 11868203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 11878203SAli.Saidi@ARM.com if (conditional) 11888203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 11898203SAli.Saidi@ARM.com else 11908203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 11918203SAli.Saidi@ARM.com if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s) 11928203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsReturn); 11937646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11947646Sgene.wu@arm.com } else { 11957646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 11967724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11977646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11987646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11997646Sgene.wu@arm.com } 12007646Sgene.wu@arm.com#endif 12017646Sgene.wu@arm.com } 12027646Sgene.wu@arm.com}}; 12037646Sgene.wu@arm.com 1204