mem.isa revision 7848
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37120Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447646Sgene.wu@arm.comdef template PanicExecute {{ 457646Sgene.wu@arm.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 467646Sgene.wu@arm.com Trace::InstRecord *traceData) const 477646Sgene.wu@arm.com { 487646Sgene.wu@arm.com panic("Execute function executed when it shouldn't be!\n"); 497646Sgene.wu@arm.com return NoFault; 507646Sgene.wu@arm.com } 517646Sgene.wu@arm.com}}; 527646Sgene.wu@arm.com 537646Sgene.wu@arm.comdef template PanicInitiateAcc {{ 547646Sgene.wu@arm.com Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 557646Sgene.wu@arm.com Trace::InstRecord *traceData) const 567646Sgene.wu@arm.com { 577646Sgene.wu@arm.com panic("InitiateAcc function executed when it shouldn't be!\n"); 587646Sgene.wu@arm.com return NoFault; 597646Sgene.wu@arm.com } 607646Sgene.wu@arm.com}}; 617646Sgene.wu@arm.com 627646Sgene.wu@arm.comdef template PanicCompleteAcc {{ 637646Sgene.wu@arm.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 647646Sgene.wu@arm.com %(CPU_exec_context)s *xc, 657646Sgene.wu@arm.com Trace::InstRecord *traceData) const 667646Sgene.wu@arm.com { 677646Sgene.wu@arm.com panic("CompleteAcc function executed when it shouldn't be!\n"); 687646Sgene.wu@arm.com return NoFault; 697646Sgene.wu@arm.com } 707646Sgene.wu@arm.com}}; 717646Sgene.wu@arm.com 727646Sgene.wu@arm.com 737205Sgblack@eecs.umich.edudef template SwapExecute {{ 747205Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 757205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 767205Sgblack@eecs.umich.edu { 777205Sgblack@eecs.umich.edu Addr EA; 787205Sgblack@eecs.umich.edu Fault fault = NoFault; 797205Sgblack@eecs.umich.edu 807205Sgblack@eecs.umich.edu %(op_decl)s; 817205Sgblack@eecs.umich.edu uint64_t memData = 0; 827205Sgblack@eecs.umich.edu %(op_rd)s; 837205Sgblack@eecs.umich.edu %(ea_code)s; 847205Sgblack@eecs.umich.edu 857205Sgblack@eecs.umich.edu if (%(predicate_test)s) 867205Sgblack@eecs.umich.edu { 877205Sgblack@eecs.umich.edu %(preacc_code)s; 887205Sgblack@eecs.umich.edu 897205Sgblack@eecs.umich.edu if (fault == NoFault) { 907205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 917205Sgblack@eecs.umich.edu EA, memAccessFlags, &memData); 927205Sgblack@eecs.umich.edu } 937205Sgblack@eecs.umich.edu 947205Sgblack@eecs.umich.edu if (fault == NoFault) { 957205Sgblack@eecs.umich.edu %(postacc_code)s; 967205Sgblack@eecs.umich.edu } 977205Sgblack@eecs.umich.edu 987205Sgblack@eecs.umich.edu if (fault == NoFault) { 997205Sgblack@eecs.umich.edu %(op_wb)s; 1007205Sgblack@eecs.umich.edu } 1017597Sminkyu.jeong@arm.com } else { 1027597Sminkyu.jeong@arm.com xc->setPredicate(false); 1037205Sgblack@eecs.umich.edu } 1047205Sgblack@eecs.umich.edu 1057646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 1067646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 1077408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1087408Sgblack@eecs.umich.edu } 1097408Sgblack@eecs.umich.edu 1107205Sgblack@eecs.umich.edu return fault; 1117205Sgblack@eecs.umich.edu } 1127205Sgblack@eecs.umich.edu}}; 1137205Sgblack@eecs.umich.edu 1147205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 1157205Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1167205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1177205Sgblack@eecs.umich.edu { 1187205Sgblack@eecs.umich.edu Addr EA; 1197205Sgblack@eecs.umich.edu Fault fault = NoFault; 1207205Sgblack@eecs.umich.edu 1217205Sgblack@eecs.umich.edu %(op_decl)s; 1227205Sgblack@eecs.umich.edu uint64_t memData = 0; 1237205Sgblack@eecs.umich.edu %(op_rd)s; 1247205Sgblack@eecs.umich.edu %(ea_code)s; 1257205Sgblack@eecs.umich.edu 1267205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1277205Sgblack@eecs.umich.edu { 1287205Sgblack@eecs.umich.edu %(preacc_code)s; 1297205Sgblack@eecs.umich.edu 1307205Sgblack@eecs.umich.edu if (fault == NoFault) { 1317205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1327205Sgblack@eecs.umich.edu memAccessFlags, &memData); 1337205Sgblack@eecs.umich.edu } 1347597Sminkyu.jeong@arm.com } else { 1357597Sminkyu.jeong@arm.com xc->setPredicate(false); 1367205Sgblack@eecs.umich.edu } 1377205Sgblack@eecs.umich.edu 1387646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 1397646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 1407408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1417408Sgblack@eecs.umich.edu } 1427408Sgblack@eecs.umich.edu 1437205Sgblack@eecs.umich.edu return fault; 1447205Sgblack@eecs.umich.edu } 1457205Sgblack@eecs.umich.edu}}; 1467205Sgblack@eecs.umich.edu 1477205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1487205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1497205Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1507205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1517205Sgblack@eecs.umich.edu { 1527205Sgblack@eecs.umich.edu Fault fault = NoFault; 1537205Sgblack@eecs.umich.edu 1547205Sgblack@eecs.umich.edu %(op_decl)s; 1557205Sgblack@eecs.umich.edu %(op_rd)s; 1567205Sgblack@eecs.umich.edu 1577205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1587205Sgblack@eecs.umich.edu { 1597205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1607205Sgblack@eecs.umich.edu uint64_t memData = pkt->get<typeof(Mem)>(); 1617205Sgblack@eecs.umich.edu 1627205Sgblack@eecs.umich.edu %(postacc_code)s; 1637205Sgblack@eecs.umich.edu 1647205Sgblack@eecs.umich.edu if (fault == NoFault) { 1657205Sgblack@eecs.umich.edu %(op_wb)s; 1667205Sgblack@eecs.umich.edu } 1677205Sgblack@eecs.umich.edu } 1687205Sgblack@eecs.umich.edu 1697408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1707408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1717408Sgblack@eecs.umich.edu } 1727408Sgblack@eecs.umich.edu 1737205Sgblack@eecs.umich.edu return fault; 1747205Sgblack@eecs.umich.edu } 1757205Sgblack@eecs.umich.edu}}; 1767205Sgblack@eecs.umich.edu 1777119Sgblack@eecs.umich.edudef template LoadExecute {{ 1787119Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1797119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1807119Sgblack@eecs.umich.edu { 1817119Sgblack@eecs.umich.edu Addr EA; 1827119Sgblack@eecs.umich.edu Fault fault = NoFault; 1837119Sgblack@eecs.umich.edu 1847119Sgblack@eecs.umich.edu %(op_decl)s; 1857119Sgblack@eecs.umich.edu %(op_rd)s; 1867119Sgblack@eecs.umich.edu %(ea_code)s; 1877119Sgblack@eecs.umich.edu 1887119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1897119Sgblack@eecs.umich.edu { 1907119Sgblack@eecs.umich.edu if (fault == NoFault) { 1917119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1927119Sgblack@eecs.umich.edu %(memacc_code)s; 1937119Sgblack@eecs.umich.edu } 1947119Sgblack@eecs.umich.edu 1957119Sgblack@eecs.umich.edu if (fault == NoFault) { 1967119Sgblack@eecs.umich.edu %(op_wb)s; 1977119Sgblack@eecs.umich.edu } 1987597Sminkyu.jeong@arm.com } else { 1997597Sminkyu.jeong@arm.com xc->setPredicate(false); 2007119Sgblack@eecs.umich.edu } 2017119Sgblack@eecs.umich.edu 2027646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 2037646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 2047408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2057408Sgblack@eecs.umich.edu } 2067408Sgblack@eecs.umich.edu 2077119Sgblack@eecs.umich.edu return fault; 2087119Sgblack@eecs.umich.edu } 2097119Sgblack@eecs.umich.edu}}; 2107119Sgblack@eecs.umich.edu 2117639Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 2127639Sgblack@eecs.umich.edu template <class Element> 2137639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2147639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2157639Sgblack@eecs.umich.edu { 2167639Sgblack@eecs.umich.edu Addr EA; 2177639Sgblack@eecs.umich.edu Fault fault = NoFault; 2187639Sgblack@eecs.umich.edu 2197639Sgblack@eecs.umich.edu %(op_decl)s; 2207639Sgblack@eecs.umich.edu %(mem_decl)s; 2217639Sgblack@eecs.umich.edu %(op_rd)s; 2227639Sgblack@eecs.umich.edu %(ea_code)s; 2237639Sgblack@eecs.umich.edu 2247639Sgblack@eecs.umich.edu MemUnion memUnion; 2257639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2267639Sgblack@eecs.umich.edu 2277639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2287639Sgblack@eecs.umich.edu { 2297639Sgblack@eecs.umich.edu if (fault == NoFault) { 2307639Sgblack@eecs.umich.edu fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 2317639Sgblack@eecs.umich.edu %(memacc_code)s; 2327639Sgblack@eecs.umich.edu } 2337639Sgblack@eecs.umich.edu 2347639Sgblack@eecs.umich.edu if (fault == NoFault) { 2357639Sgblack@eecs.umich.edu %(op_wb)s; 2367639Sgblack@eecs.umich.edu } 2377639Sgblack@eecs.umich.edu } 2387639Sgblack@eecs.umich.edu 2397646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 2407646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 2417639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2427639Sgblack@eecs.umich.edu } 2437639Sgblack@eecs.umich.edu 2447639Sgblack@eecs.umich.edu return fault; 2457639Sgblack@eecs.umich.edu } 2467639Sgblack@eecs.umich.edu}}; 2477639Sgblack@eecs.umich.edu 2487120Sgblack@eecs.umich.edudef template StoreExecute {{ 2497120Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2507120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2517120Sgblack@eecs.umich.edu { 2527120Sgblack@eecs.umich.edu Addr EA; 2537120Sgblack@eecs.umich.edu Fault fault = NoFault; 2547120Sgblack@eecs.umich.edu 2557120Sgblack@eecs.umich.edu %(op_decl)s; 2567120Sgblack@eecs.umich.edu %(op_rd)s; 2577120Sgblack@eecs.umich.edu %(ea_code)s; 2587120Sgblack@eecs.umich.edu 2597120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2607120Sgblack@eecs.umich.edu { 2617120Sgblack@eecs.umich.edu if (fault == NoFault) { 2627120Sgblack@eecs.umich.edu %(memacc_code)s; 2637120Sgblack@eecs.umich.edu } 2647120Sgblack@eecs.umich.edu 2657120Sgblack@eecs.umich.edu if (fault == NoFault) { 2667120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2677120Sgblack@eecs.umich.edu memAccessFlags, NULL); 2687120Sgblack@eecs.umich.edu } 2697120Sgblack@eecs.umich.edu 2707120Sgblack@eecs.umich.edu if (fault == NoFault) { 2717120Sgblack@eecs.umich.edu %(op_wb)s; 2727120Sgblack@eecs.umich.edu } 2737597Sminkyu.jeong@arm.com } else { 2747597Sminkyu.jeong@arm.com xc->setPredicate(false); 2757120Sgblack@eecs.umich.edu } 2767120Sgblack@eecs.umich.edu 2777646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 2787646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 2797408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2807408Sgblack@eecs.umich.edu } 2817408Sgblack@eecs.umich.edu 2827120Sgblack@eecs.umich.edu return fault; 2837120Sgblack@eecs.umich.edu } 2847120Sgblack@eecs.umich.edu}}; 2857120Sgblack@eecs.umich.edu 2867639Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2877639Sgblack@eecs.umich.edu template <class Element> 2887639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2897639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2907639Sgblack@eecs.umich.edu { 2917639Sgblack@eecs.umich.edu Addr EA; 2927639Sgblack@eecs.umich.edu Fault fault = NoFault; 2937639Sgblack@eecs.umich.edu 2947639Sgblack@eecs.umich.edu %(op_decl)s; 2957639Sgblack@eecs.umich.edu %(mem_decl)s; 2967639Sgblack@eecs.umich.edu %(op_rd)s; 2977639Sgblack@eecs.umich.edu %(ea_code)s; 2987639Sgblack@eecs.umich.edu 2997639Sgblack@eecs.umich.edu MemUnion memUnion; 3007639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 3017639Sgblack@eecs.umich.edu 3027639Sgblack@eecs.umich.edu if (%(predicate_test)s) 3037639Sgblack@eecs.umich.edu { 3047639Sgblack@eecs.umich.edu if (fault == NoFault) { 3057639Sgblack@eecs.umich.edu %(memacc_code)s; 3067639Sgblack@eecs.umich.edu } 3077639Sgblack@eecs.umich.edu 3087639Sgblack@eecs.umich.edu if (fault == NoFault) { 3097639Sgblack@eecs.umich.edu fault = xc->writeBytes(dataPtr, %(size)d, EA, 3107639Sgblack@eecs.umich.edu memAccessFlags, NULL); 3117639Sgblack@eecs.umich.edu } 3127639Sgblack@eecs.umich.edu 3137639Sgblack@eecs.umich.edu if (fault == NoFault) { 3147639Sgblack@eecs.umich.edu %(op_wb)s; 3157639Sgblack@eecs.umich.edu } 3167639Sgblack@eecs.umich.edu } 3177639Sgblack@eecs.umich.edu 3187646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 3197646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 3207639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3217639Sgblack@eecs.umich.edu } 3227639Sgblack@eecs.umich.edu 3237639Sgblack@eecs.umich.edu return fault; 3247639Sgblack@eecs.umich.edu } 3257639Sgblack@eecs.umich.edu}}; 3267639Sgblack@eecs.umich.edu 3277303Sgblack@eecs.umich.edudef template StoreExExecute {{ 3287303Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3297303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3307303Sgblack@eecs.umich.edu { 3317303Sgblack@eecs.umich.edu Addr EA; 3327303Sgblack@eecs.umich.edu Fault fault = NoFault; 3337303Sgblack@eecs.umich.edu 3347303Sgblack@eecs.umich.edu %(op_decl)s; 3357303Sgblack@eecs.umich.edu %(op_rd)s; 3367303Sgblack@eecs.umich.edu %(ea_code)s; 3377303Sgblack@eecs.umich.edu 3387303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3397303Sgblack@eecs.umich.edu { 3407303Sgblack@eecs.umich.edu if (fault == NoFault) { 3417303Sgblack@eecs.umich.edu %(memacc_code)s; 3427303Sgblack@eecs.umich.edu } 3437303Sgblack@eecs.umich.edu 3447303Sgblack@eecs.umich.edu uint64_t writeResult; 3457303Sgblack@eecs.umich.edu 3467303Sgblack@eecs.umich.edu if (fault == NoFault) { 3477303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3487303Sgblack@eecs.umich.edu memAccessFlags, &writeResult); 3497303Sgblack@eecs.umich.edu } 3507303Sgblack@eecs.umich.edu 3517303Sgblack@eecs.umich.edu if (fault == NoFault) { 3527303Sgblack@eecs.umich.edu %(postacc_code)s; 3537303Sgblack@eecs.umich.edu } 3547303Sgblack@eecs.umich.edu 3557303Sgblack@eecs.umich.edu if (fault == NoFault) { 3567303Sgblack@eecs.umich.edu %(op_wb)s; 3577303Sgblack@eecs.umich.edu } 3587597Sminkyu.jeong@arm.com } else { 3597597Sminkyu.jeong@arm.com xc->setPredicate(false); 3607303Sgblack@eecs.umich.edu } 3617303Sgblack@eecs.umich.edu 3627646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 3637646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 3647408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3657408Sgblack@eecs.umich.edu } 3667408Sgblack@eecs.umich.edu 3677303Sgblack@eecs.umich.edu return fault; 3687303Sgblack@eecs.umich.edu } 3697303Sgblack@eecs.umich.edu}}; 3707303Sgblack@eecs.umich.edu 3717303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 3727303Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3737303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3747303Sgblack@eecs.umich.edu { 3757303Sgblack@eecs.umich.edu Addr EA; 3767303Sgblack@eecs.umich.edu Fault fault = NoFault; 3777303Sgblack@eecs.umich.edu 3787303Sgblack@eecs.umich.edu %(op_decl)s; 3797303Sgblack@eecs.umich.edu %(op_rd)s; 3807303Sgblack@eecs.umich.edu %(ea_code)s; 3817303Sgblack@eecs.umich.edu 3827303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3837303Sgblack@eecs.umich.edu { 3847303Sgblack@eecs.umich.edu if (fault == NoFault) { 3857303Sgblack@eecs.umich.edu %(memacc_code)s; 3867303Sgblack@eecs.umich.edu } 3877303Sgblack@eecs.umich.edu 3887303Sgblack@eecs.umich.edu if (fault == NoFault) { 3897303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3907303Sgblack@eecs.umich.edu memAccessFlags, NULL); 3917303Sgblack@eecs.umich.edu } 3927597Sminkyu.jeong@arm.com } else { 3937597Sminkyu.jeong@arm.com xc->setPredicate(false); 3947303Sgblack@eecs.umich.edu } 3957646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 3967646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 3977408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3987408Sgblack@eecs.umich.edu } 3997408Sgblack@eecs.umich.edu 4007303Sgblack@eecs.umich.edu return fault; 4017303Sgblack@eecs.umich.edu } 4027303Sgblack@eecs.umich.edu}}; 4037303Sgblack@eecs.umich.edu 4047120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 4057120Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4067120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4077120Sgblack@eecs.umich.edu { 4087120Sgblack@eecs.umich.edu Addr EA; 4097120Sgblack@eecs.umich.edu Fault fault = NoFault; 4107120Sgblack@eecs.umich.edu 4117120Sgblack@eecs.umich.edu %(op_decl)s; 4127120Sgblack@eecs.umich.edu %(op_rd)s; 4137120Sgblack@eecs.umich.edu %(ea_code)s; 4147120Sgblack@eecs.umich.edu 4157120Sgblack@eecs.umich.edu if (%(predicate_test)s) 4167120Sgblack@eecs.umich.edu { 4177120Sgblack@eecs.umich.edu if (fault == NoFault) { 4187120Sgblack@eecs.umich.edu %(memacc_code)s; 4197120Sgblack@eecs.umich.edu } 4207120Sgblack@eecs.umich.edu 4217120Sgblack@eecs.umich.edu if (fault == NoFault) { 4227120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 4237120Sgblack@eecs.umich.edu memAccessFlags, NULL); 4247120Sgblack@eecs.umich.edu } 4257597Sminkyu.jeong@arm.com } else { 4267597Sminkyu.jeong@arm.com xc->setPredicate(false); 4277120Sgblack@eecs.umich.edu } 4287120Sgblack@eecs.umich.edu 4297646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4307646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4317408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4327408Sgblack@eecs.umich.edu } 4337408Sgblack@eecs.umich.edu 4347120Sgblack@eecs.umich.edu return fault; 4357120Sgblack@eecs.umich.edu } 4367120Sgblack@eecs.umich.edu}}; 4377120Sgblack@eecs.umich.edu 4387639Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 4397639Sgblack@eecs.umich.edu template <class Element> 4407639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 4417639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 4427639Sgblack@eecs.umich.edu { 4437639Sgblack@eecs.umich.edu Addr EA; 4447639Sgblack@eecs.umich.edu Fault fault = NoFault; 4457639Sgblack@eecs.umich.edu 4467639Sgblack@eecs.umich.edu %(op_decl)s; 4477639Sgblack@eecs.umich.edu %(mem_decl)s; 4487639Sgblack@eecs.umich.edu %(op_rd)s; 4497639Sgblack@eecs.umich.edu %(ea_code)s; 4507639Sgblack@eecs.umich.edu 4517639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4527639Sgblack@eecs.umich.edu { 4537639Sgblack@eecs.umich.edu MemUnion memUnion; 4547639Sgblack@eecs.umich.edu if (fault == NoFault) { 4557639Sgblack@eecs.umich.edu %(memacc_code)s; 4567639Sgblack@eecs.umich.edu } 4577639Sgblack@eecs.umich.edu 4587639Sgblack@eecs.umich.edu if (fault == NoFault) { 4597639Sgblack@eecs.umich.edu fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 4607639Sgblack@eecs.umich.edu memAccessFlags, NULL); 4617639Sgblack@eecs.umich.edu } 4627639Sgblack@eecs.umich.edu } 4637639Sgblack@eecs.umich.edu 4647646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4657646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4667639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4677639Sgblack@eecs.umich.edu } 4687639Sgblack@eecs.umich.edu 4697639Sgblack@eecs.umich.edu return fault; 4707639Sgblack@eecs.umich.edu } 4717639Sgblack@eecs.umich.edu}}; 4727639Sgblack@eecs.umich.edu 4737119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 4747119Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4757119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4767119Sgblack@eecs.umich.edu { 4777119Sgblack@eecs.umich.edu Addr EA; 4787119Sgblack@eecs.umich.edu Fault fault = NoFault; 4797119Sgblack@eecs.umich.edu 4807119Sgblack@eecs.umich.edu %(op_src_decl)s; 4817119Sgblack@eecs.umich.edu %(op_rd)s; 4827119Sgblack@eecs.umich.edu %(ea_code)s; 4837119Sgblack@eecs.umich.edu 4847119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4857119Sgblack@eecs.umich.edu { 4867119Sgblack@eecs.umich.edu if (fault == NoFault) { 4877119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 4887119Sgblack@eecs.umich.edu } 4897597Sminkyu.jeong@arm.com } else { 4907597Sminkyu.jeong@arm.com xc->setPredicate(false); 4917646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4927646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4937597Sminkyu.jeong@arm.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4947597Sminkyu.jeong@arm.com } 4957119Sgblack@eecs.umich.edu } 4967119Sgblack@eecs.umich.edu 4977119Sgblack@eecs.umich.edu return fault; 4987119Sgblack@eecs.umich.edu } 4997119Sgblack@eecs.umich.edu}}; 5007119Sgblack@eecs.umich.edu 5017639Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 5027639Sgblack@eecs.umich.edu template <class Element> 5037639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 5047639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 5057639Sgblack@eecs.umich.edu { 5067639Sgblack@eecs.umich.edu Addr EA; 5077639Sgblack@eecs.umich.edu Fault fault = NoFault; 5087639Sgblack@eecs.umich.edu 5097639Sgblack@eecs.umich.edu %(op_src_decl)s; 5107639Sgblack@eecs.umich.edu %(op_rd)s; 5117639Sgblack@eecs.umich.edu %(ea_code)s; 5127639Sgblack@eecs.umich.edu 5137639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5147639Sgblack@eecs.umich.edu { 5157639Sgblack@eecs.umich.edu if (fault == NoFault) { 5167639Sgblack@eecs.umich.edu fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags); 5177639Sgblack@eecs.umich.edu } 5187646Sgene.wu@arm.com } else if (fault == NoFault && machInst.itstateMask != 0 && 5197646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 5207639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5217639Sgblack@eecs.umich.edu } 5227639Sgblack@eecs.umich.edu 5237639Sgblack@eecs.umich.edu return fault; 5247639Sgblack@eecs.umich.edu } 5257639Sgblack@eecs.umich.edu}}; 5267639Sgblack@eecs.umich.edu 5277119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 5287119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5297119Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5307119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5317119Sgblack@eecs.umich.edu { 5327119Sgblack@eecs.umich.edu Fault fault = NoFault; 5337119Sgblack@eecs.umich.edu 5347119Sgblack@eecs.umich.edu %(op_decl)s; 5357119Sgblack@eecs.umich.edu %(op_rd)s; 5367119Sgblack@eecs.umich.edu 5377119Sgblack@eecs.umich.edu if (%(predicate_test)s) 5387119Sgblack@eecs.umich.edu { 5397119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5407119Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 5417119Sgblack@eecs.umich.edu 5427119Sgblack@eecs.umich.edu if (fault == NoFault) { 5437119Sgblack@eecs.umich.edu %(memacc_code)s; 5447119Sgblack@eecs.umich.edu } 5457119Sgblack@eecs.umich.edu 5467119Sgblack@eecs.umich.edu if (fault == NoFault) { 5477119Sgblack@eecs.umich.edu %(op_wb)s; 5487119Sgblack@eecs.umich.edu } 5497119Sgblack@eecs.umich.edu } 5507119Sgblack@eecs.umich.edu 5517408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 5527408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5537408Sgblack@eecs.umich.edu } 5547408Sgblack@eecs.umich.edu 5557119Sgblack@eecs.umich.edu return fault; 5567119Sgblack@eecs.umich.edu } 5577119Sgblack@eecs.umich.edu}}; 5587119Sgblack@eecs.umich.edu 5597639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5607639Sgblack@eecs.umich.edu template <class Element> 5617639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5627639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 5637639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5647639Sgblack@eecs.umich.edu { 5657639Sgblack@eecs.umich.edu Fault fault = NoFault; 5667639Sgblack@eecs.umich.edu 5677639Sgblack@eecs.umich.edu %(mem_decl)s; 5687639Sgblack@eecs.umich.edu %(op_decl)s; 5697639Sgblack@eecs.umich.edu %(op_rd)s; 5707639Sgblack@eecs.umich.edu 5717639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5727639Sgblack@eecs.umich.edu { 5737639Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5747639Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5757639Sgblack@eecs.umich.edu 5767639Sgblack@eecs.umich.edu if (fault == NoFault) { 5777639Sgblack@eecs.umich.edu %(memacc_code)s; 5787639Sgblack@eecs.umich.edu } 5797639Sgblack@eecs.umich.edu 5807639Sgblack@eecs.umich.edu if (fault == NoFault) { 5817639Sgblack@eecs.umich.edu %(op_wb)s; 5827639Sgblack@eecs.umich.edu } 5837639Sgblack@eecs.umich.edu } 5847639Sgblack@eecs.umich.edu 5857639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 5867639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5877639Sgblack@eecs.umich.edu } 5887639Sgblack@eecs.umich.edu 5897639Sgblack@eecs.umich.edu return fault; 5907639Sgblack@eecs.umich.edu } 5917639Sgblack@eecs.umich.edu}}; 5927639Sgblack@eecs.umich.edu 5937120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 5947120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5957120Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5967120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5977120Sgblack@eecs.umich.edu { 5987712Sgblack@eecs.umich.edu if (machInst.itstateMask != 0) { 5997712Sgblack@eecs.umich.edu warn_once("Complete acc isn't called on normal stores in O3."); 6007408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6017408Sgblack@eecs.umich.edu } 6027712Sgblack@eecs.umich.edu return NoFault; 6037120Sgblack@eecs.umich.edu } 6047120Sgblack@eecs.umich.edu}}; 6057120Sgblack@eecs.umich.edu 6067639Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 6077639Sgblack@eecs.umich.edu template <class Element> 6087639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 6097639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 6107639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6117639Sgblack@eecs.umich.edu { 6127712Sgblack@eecs.umich.edu if (machInst.itstateMask != 0) { 6137712Sgblack@eecs.umich.edu warn_once("Complete acc isn't called on normal stores in O3."); 6147639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6157639Sgblack@eecs.umich.edu } 6167712Sgblack@eecs.umich.edu return NoFault; 6177639Sgblack@eecs.umich.edu } 6187639Sgblack@eecs.umich.edu}}; 6197639Sgblack@eecs.umich.edu 6207303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 6217303Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 6227303Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 6237303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6247303Sgblack@eecs.umich.edu { 6257303Sgblack@eecs.umich.edu Fault fault = NoFault; 6267303Sgblack@eecs.umich.edu 6277303Sgblack@eecs.umich.edu %(op_decl)s; 6287303Sgblack@eecs.umich.edu %(op_rd)s; 6297303Sgblack@eecs.umich.edu 6307303Sgblack@eecs.umich.edu if (%(predicate_test)s) 6317303Sgblack@eecs.umich.edu { 6327303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 6337303Sgblack@eecs.umich.edu %(postacc_code)s; 6347303Sgblack@eecs.umich.edu 6357303Sgblack@eecs.umich.edu if (fault == NoFault) { 6367303Sgblack@eecs.umich.edu %(op_wb)s; 6377303Sgblack@eecs.umich.edu } 6387303Sgblack@eecs.umich.edu } 6397303Sgblack@eecs.umich.edu 6407408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 6417408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6427408Sgblack@eecs.umich.edu } 6437408Sgblack@eecs.umich.edu 6447303Sgblack@eecs.umich.edu return fault; 6457303Sgblack@eecs.umich.edu } 6467303Sgblack@eecs.umich.edu}}; 6477303Sgblack@eecs.umich.edu 6487291Sgblack@eecs.umich.edudef template RfeDeclare {{ 6497291Sgblack@eecs.umich.edu /** 6507291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6517291Sgblack@eecs.umich.edu */ 6527291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6537291Sgblack@eecs.umich.edu { 6547291Sgblack@eecs.umich.edu public: 6557291Sgblack@eecs.umich.edu 6567291Sgblack@eecs.umich.edu /// Constructor. 6577291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6587291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 6597291Sgblack@eecs.umich.edu 6607291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6617291Sgblack@eecs.umich.edu 6627291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6637291Sgblack@eecs.umich.edu 6647291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6657291Sgblack@eecs.umich.edu }; 6667291Sgblack@eecs.umich.edu}}; 6677291Sgblack@eecs.umich.edu 6687312Sgblack@eecs.umich.edudef template SrsDeclare {{ 6697312Sgblack@eecs.umich.edu /** 6707312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6717312Sgblack@eecs.umich.edu */ 6727312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6737312Sgblack@eecs.umich.edu { 6747312Sgblack@eecs.umich.edu public: 6757312Sgblack@eecs.umich.edu 6767312Sgblack@eecs.umich.edu /// Constructor. 6777312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6787312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6797312Sgblack@eecs.umich.edu 6807312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6817312Sgblack@eecs.umich.edu 6827312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6837312Sgblack@eecs.umich.edu 6847312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6857312Sgblack@eecs.umich.edu }; 6867312Sgblack@eecs.umich.edu}}; 6877312Sgblack@eecs.umich.edu 6887205Sgblack@eecs.umich.edudef template SwapDeclare {{ 6897205Sgblack@eecs.umich.edu /** 6907205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6917205Sgblack@eecs.umich.edu */ 6927205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6937205Sgblack@eecs.umich.edu { 6947205Sgblack@eecs.umich.edu public: 6957205Sgblack@eecs.umich.edu 6967205Sgblack@eecs.umich.edu /// Constructor. 6977205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6987205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 6997205Sgblack@eecs.umich.edu 7007205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7017205Sgblack@eecs.umich.edu 7027205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7037205Sgblack@eecs.umich.edu 7047205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7057205Sgblack@eecs.umich.edu }; 7067205Sgblack@eecs.umich.edu}}; 7077205Sgblack@eecs.umich.edu 7087279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 7097279Sgblack@eecs.umich.edu /** 7107279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7117279Sgblack@eecs.umich.edu */ 7127279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7137279Sgblack@eecs.umich.edu { 7147279Sgblack@eecs.umich.edu public: 7157279Sgblack@eecs.umich.edu 7167279Sgblack@eecs.umich.edu /// Constructor. 7177279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7187279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7197279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 7207279Sgblack@eecs.umich.edu 7217279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7227279Sgblack@eecs.umich.edu 7237279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7247279Sgblack@eecs.umich.edu 7257279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7267279Sgblack@eecs.umich.edu }; 7277279Sgblack@eecs.umich.edu}}; 7287279Sgblack@eecs.umich.edu 7297303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 7307303Sgblack@eecs.umich.edu /** 7317303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7327303Sgblack@eecs.umich.edu */ 7337303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7347303Sgblack@eecs.umich.edu { 7357303Sgblack@eecs.umich.edu public: 7367303Sgblack@eecs.umich.edu 7377303Sgblack@eecs.umich.edu /// Constructor. 7387303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7397303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 7407303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 7417303Sgblack@eecs.umich.edu 7427303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7437303Sgblack@eecs.umich.edu 7447303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7457303Sgblack@eecs.umich.edu 7467303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7477303Sgblack@eecs.umich.edu }; 7487303Sgblack@eecs.umich.edu}}; 7497303Sgblack@eecs.umich.edu 7507119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 7517119Sgblack@eecs.umich.edu /** 7527119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7537119Sgblack@eecs.umich.edu */ 7547119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7557119Sgblack@eecs.umich.edu { 7567119Sgblack@eecs.umich.edu public: 7577119Sgblack@eecs.umich.edu 7587119Sgblack@eecs.umich.edu /// Constructor. 7597119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7607119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 7617119Sgblack@eecs.umich.edu 7627119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7637119Sgblack@eecs.umich.edu 7647119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7657119Sgblack@eecs.umich.edu 7667119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7677119Sgblack@eecs.umich.edu }; 7687119Sgblack@eecs.umich.edu}}; 7697119Sgblack@eecs.umich.edu 7707303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 7717303Sgblack@eecs.umich.edu /** 7727303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7737303Sgblack@eecs.umich.edu */ 7747303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7757303Sgblack@eecs.umich.edu { 7767303Sgblack@eecs.umich.edu public: 7777303Sgblack@eecs.umich.edu 7787303Sgblack@eecs.umich.edu /// Constructor. 7797303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7807303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7817303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7827303Sgblack@eecs.umich.edu 7837303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7847303Sgblack@eecs.umich.edu 7857303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7867303Sgblack@eecs.umich.edu 7877303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7887303Sgblack@eecs.umich.edu }; 7897303Sgblack@eecs.umich.edu}}; 7907303Sgblack@eecs.umich.edu 7917646Sgene.wu@arm.comdef template StoreDRegDeclare {{ 7927279Sgblack@eecs.umich.edu /** 7937279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7947279Sgblack@eecs.umich.edu */ 7957279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7967279Sgblack@eecs.umich.edu { 7977279Sgblack@eecs.umich.edu public: 7987279Sgblack@eecs.umich.edu 7997279Sgblack@eecs.umich.edu /// Constructor. 8007279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8017279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 8027279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 8037279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8047279Sgblack@eecs.umich.edu uint32_t _index); 8057279Sgblack@eecs.umich.edu 8067279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8077279Sgblack@eecs.umich.edu 8087279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8097279Sgblack@eecs.umich.edu 8107279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8117279Sgblack@eecs.umich.edu }; 8127279Sgblack@eecs.umich.edu}}; 8137279Sgblack@eecs.umich.edu 8147646Sgene.wu@arm.comdef template StoreRegDeclare {{ 8157119Sgblack@eecs.umich.edu /** 8167119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8177119Sgblack@eecs.umich.edu */ 8187119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8197119Sgblack@eecs.umich.edu { 8207119Sgblack@eecs.umich.edu public: 8217119Sgblack@eecs.umich.edu 8227119Sgblack@eecs.umich.edu /// Constructor. 8237119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8247119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 8257119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8267119Sgblack@eecs.umich.edu uint32_t _index); 8277119Sgblack@eecs.umich.edu 8287119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8297119Sgblack@eecs.umich.edu 8307119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8317119Sgblack@eecs.umich.edu 8327119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8337119Sgblack@eecs.umich.edu }; 8347119Sgblack@eecs.umich.edu}}; 8357119Sgblack@eecs.umich.edu 8367646Sgene.wu@arm.comdef template LoadDRegDeclare {{ 8377646Sgene.wu@arm.com /** 8387646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8397646Sgene.wu@arm.com */ 8407646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8417646Sgene.wu@arm.com { 8427646Sgene.wu@arm.com public: 8437646Sgene.wu@arm.com 8447646Sgene.wu@arm.com /// Constructor. 8457646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8467646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, 8477646Sgene.wu@arm.com uint32_t _base, bool _add, 8487646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 8497646Sgene.wu@arm.com uint32_t _index); 8507646Sgene.wu@arm.com 8517646Sgene.wu@arm.com %(BasicExecDeclare)s 8527646Sgene.wu@arm.com 8537646Sgene.wu@arm.com %(InitiateAccDeclare)s 8547646Sgene.wu@arm.com 8557646Sgene.wu@arm.com %(CompleteAccDeclare)s 8567646Sgene.wu@arm.com }; 8577646Sgene.wu@arm.com}}; 8587646Sgene.wu@arm.com 8597646Sgene.wu@arm.comdef template LoadRegDeclare {{ 8607646Sgene.wu@arm.com /** 8617646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8627646Sgene.wu@arm.com */ 8637646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8647646Sgene.wu@arm.com { 8657646Sgene.wu@arm.com public: 8667646Sgene.wu@arm.com 8677646Sgene.wu@arm.com /// Constructor. 8687646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8697646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 8707646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 8717646Sgene.wu@arm.com uint32_t _index); 8727646Sgene.wu@arm.com 8737646Sgene.wu@arm.com %(BasicExecDeclare)s 8747646Sgene.wu@arm.com 8757646Sgene.wu@arm.com %(InitiateAccDeclare)s 8767646Sgene.wu@arm.com 8777646Sgene.wu@arm.com %(CompleteAccDeclare)s 8787646Sgene.wu@arm.com }; 8797646Sgene.wu@arm.com}}; 8807646Sgene.wu@arm.com 8817646Sgene.wu@arm.comdef template LoadImmDeclare {{ 8827646Sgene.wu@arm.com /** 8837646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8847646Sgene.wu@arm.com */ 8857646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8867646Sgene.wu@arm.com { 8877646Sgene.wu@arm.com public: 8887646Sgene.wu@arm.com 8897646Sgene.wu@arm.com /// Constructor. 8907646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8917646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8927646Sgene.wu@arm.com 8937646Sgene.wu@arm.com %(BasicExecDeclare)s 8947646Sgene.wu@arm.com 8957646Sgene.wu@arm.com %(InitiateAccDeclare)s 8967646Sgene.wu@arm.com 8977646Sgene.wu@arm.com %(CompleteAccDeclare)s 8987646Sgene.wu@arm.com }; 8997646Sgene.wu@arm.com}}; 9007646Sgene.wu@arm.com 9017119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 9027119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 9037119Sgblack@eecs.umich.edu}}; 9047119Sgblack@eecs.umich.edu 9057119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 9067119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 9077119Sgblack@eecs.umich.edu}}; 9087119Sgblack@eecs.umich.edu 9097291Sgblack@eecs.umich.edudef template RfeConstructor {{ 9107291Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9117291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb) 9127291Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9137291Sgblack@eecs.umich.edu (IntRegIndex)_base, (AddrMode)_mode, _wb) 9147291Sgblack@eecs.umich.edu { 9157291Sgblack@eecs.umich.edu %(constructor)s; 9167848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9177848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9187848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9197848SAli.Saidi@ARM.com } 9207848SAli.Saidi@ARM.com } 9217646Sgene.wu@arm.com#if %(use_uops)d 9227646Sgene.wu@arm.com assert(numMicroops >= 2); 9237646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9247646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb); 9257724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9267646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9277646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9287646Sgene.wu@arm.com#endif 9297291Sgblack@eecs.umich.edu } 9307291Sgblack@eecs.umich.edu}}; 9317291Sgblack@eecs.umich.edu 9327312Sgblack@eecs.umich.edudef template SrsConstructor {{ 9337312Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9347312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 9357312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9367312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 9377312Sgblack@eecs.umich.edu { 9387312Sgblack@eecs.umich.edu %(constructor)s; 9397848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9407848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9417848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9427848SAli.Saidi@ARM.com } 9437848SAli.Saidi@ARM.com } 9447646Sgene.wu@arm.com#if %(use_uops)d 9457646Sgene.wu@arm.com assert(numMicroops >= 2); 9467646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9477646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 9487724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9497646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9507646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9517646Sgene.wu@arm.com#endif 9527312Sgblack@eecs.umich.edu } 9537312Sgblack@eecs.umich.edu}}; 9547312Sgblack@eecs.umich.edu 9557205Sgblack@eecs.umich.edudef template SwapConstructor {{ 9567205Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9577205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 9587205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9597205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 9607205Sgblack@eecs.umich.edu { 9617205Sgblack@eecs.umich.edu %(constructor)s; 9627848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9637848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9647848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9657848SAli.Saidi@ARM.com } 9667848SAli.Saidi@ARM.com } 9677205Sgblack@eecs.umich.edu } 9687205Sgblack@eecs.umich.edu}}; 9697205Sgblack@eecs.umich.edu 9707279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 9717279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9727279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9737279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9747279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9757279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9767279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9777279Sgblack@eecs.umich.edu { 9787279Sgblack@eecs.umich.edu %(constructor)s; 9797848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9807848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9817848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9827848SAli.Saidi@ARM.com } 9837848SAli.Saidi@ARM.com } 9847646Sgene.wu@arm.com#if %(use_uops)d 9857646Sgene.wu@arm.com assert(numMicroops >= 2); 9867646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9877646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 9887724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9897646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9907646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9917646Sgene.wu@arm.com#endif 9927279Sgblack@eecs.umich.edu } 9937279Sgblack@eecs.umich.edu}}; 9947279Sgblack@eecs.umich.edu 9957303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 9967303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9977303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 9987303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9997303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10007303Sgblack@eecs.umich.edu (IntRegIndex)_result, 10017303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10027303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10037303Sgblack@eecs.umich.edu { 10047303Sgblack@eecs.umich.edu %(constructor)s; 10057848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10067848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10077848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10087848SAli.Saidi@ARM.com } 10097848SAli.Saidi@ARM.com } 10107646Sgene.wu@arm.com#if %(use_uops)d 10117646Sgene.wu@arm.com assert(numMicroops >= 2); 10127646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10137646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 10147646Sgene.wu@arm.com _base, _add, _imm); 10157724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10167646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10177646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10187646Sgene.wu@arm.com#endif 10197303Sgblack@eecs.umich.edu } 10207303Sgblack@eecs.umich.edu}}; 10217303Sgblack@eecs.umich.edu 10227119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 10237119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10247119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 10257119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10267119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 10277119Sgblack@eecs.umich.edu { 10287119Sgblack@eecs.umich.edu %(constructor)s; 10297848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10307848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10317848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10327848SAli.Saidi@ARM.com } 10337848SAli.Saidi@ARM.com } 10347646Sgene.wu@arm.com#if %(use_uops)d 10357646Sgene.wu@arm.com assert(numMicroops >= 2); 10367646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10377646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 10387724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10397646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10407646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10417646Sgene.wu@arm.com#endif 10427119Sgblack@eecs.umich.edu } 10437119Sgblack@eecs.umich.edu}}; 10447119Sgblack@eecs.umich.edu 10457303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 10467303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10477303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 10487303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 10497303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10507303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 10517303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10527303Sgblack@eecs.umich.edu { 10537303Sgblack@eecs.umich.edu %(constructor)s; 10547848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10557848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10567848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10577848SAli.Saidi@ARM.com } 10587848SAli.Saidi@ARM.com } 10597646Sgene.wu@arm.com#if %(use_uops)d 10607646Sgene.wu@arm.com assert(numMicroops >= 2); 10617646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10627646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, 10637646Sgene.wu@arm.com _base, _add, _imm); 10647724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10657646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10667646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10677646Sgene.wu@arm.com#endif 10687303Sgblack@eecs.umich.edu } 10697303Sgblack@eecs.umich.edu}}; 10707303Sgblack@eecs.umich.edu 10717646Sgene.wu@arm.comdef template StoreDRegConstructor {{ 10727279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10737279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10747279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10757279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10767279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10777279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10787279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10797279Sgblack@eecs.umich.edu (IntRegIndex)_index) 10807279Sgblack@eecs.umich.edu { 10817279Sgblack@eecs.umich.edu %(constructor)s; 10827848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10837848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10847848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10857848SAli.Saidi@ARM.com } 10867848SAli.Saidi@ARM.com } 10877646Sgene.wu@arm.com#if %(use_uops)d 10887646Sgene.wu@arm.com assert(numMicroops >= 2); 10897646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10907646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10917646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10927724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10937646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10947646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10957646Sgene.wu@arm.com#endif 10967279Sgblack@eecs.umich.edu } 10977279Sgblack@eecs.umich.edu}}; 10987279Sgblack@eecs.umich.edu 10997646Sgene.wu@arm.comdef template StoreRegConstructor {{ 11007119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11017119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 11027119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11037119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11047119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11057119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 11067119Sgblack@eecs.umich.edu (IntRegIndex)_index) 11077119Sgblack@eecs.umich.edu { 11087119Sgblack@eecs.umich.edu %(constructor)s; 11097848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11107848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11117848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11127848SAli.Saidi@ARM.com } 11137848SAli.Saidi@ARM.com } 11147646Sgene.wu@arm.com#if %(use_uops)d 11157646Sgene.wu@arm.com assert(numMicroops >= 2); 11167646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11177646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11187646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11197724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11207646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11217646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11227646Sgene.wu@arm.com#endif 11237119Sgblack@eecs.umich.edu } 11247119Sgblack@eecs.umich.edu}}; 11257646Sgene.wu@arm.com 11267646Sgene.wu@arm.comdef template LoadDRegConstructor {{ 11277646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11287646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 11297646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11307646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11317646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_dest2, 11327646Sgene.wu@arm.com (IntRegIndex)_base, _add, 11337646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11347646Sgene.wu@arm.com (IntRegIndex)_index) 11357646Sgene.wu@arm.com { 11367646Sgene.wu@arm.com %(constructor)s; 11377848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11387848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11397848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11407848SAli.Saidi@ARM.com } 11417848SAli.Saidi@ARM.com } 11427646Sgene.wu@arm.com#if %(use_uops)d 11437646Sgene.wu@arm.com assert(numMicroops >= 2); 11447646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11457646Sgene.wu@arm.com if ((_dest == _index) || (_dest2 == _index)) { 11467646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11477646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11487724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11497646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11507646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11517724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11527646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11537646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11547646Sgene.wu@arm.com } else { 11557646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11567646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11577646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11587724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11597646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11607646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11617646Sgene.wu@arm.com } 11627646Sgene.wu@arm.com#endif 11637646Sgene.wu@arm.com } 11647646Sgene.wu@arm.com}}; 11657646Sgene.wu@arm.com 11667646Sgene.wu@arm.comdef template LoadRegConstructor {{ 11677646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11687646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 11697646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11707646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11717646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11727646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11737646Sgene.wu@arm.com (IntRegIndex)_index) 11747646Sgene.wu@arm.com { 11757646Sgene.wu@arm.com %(constructor)s; 11767848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11777848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11787848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11797848SAli.Saidi@ARM.com } 11807848SAli.Saidi@ARM.com } 11817646Sgene.wu@arm.com#if %(use_uops)d 11827646Sgene.wu@arm.com assert(numMicroops >= 2); 11837646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11847646Sgene.wu@arm.com if (_dest == INTREG_PC) { 11857646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11867646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11877646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11887724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11897646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11907724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11917646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11927646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11937646Sgene.wu@arm.com } else if(_dest == _index) { 11947646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11957646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11967724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11977646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 11987646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11997724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 12007646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 12017646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12027646Sgene.wu@arm.com } else { 12037646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 12047646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 12057646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 12067724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 12077646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12087646Sgene.wu@arm.com uops[1]->setLastMicroop(); 12097646Sgene.wu@arm.com 12107646Sgene.wu@arm.com } 12117646Sgene.wu@arm.com#endif 12127646Sgene.wu@arm.com } 12137646Sgene.wu@arm.com}}; 12147646Sgene.wu@arm.com 12157646Sgene.wu@arm.comdef template LoadImmConstructor {{ 12167646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 12177646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 12187646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 12197646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 12207646Sgene.wu@arm.com { 12217646Sgene.wu@arm.com %(constructor)s; 12227848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 12237848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 12247848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 12257848SAli.Saidi@ARM.com } 12267848SAli.Saidi@ARM.com } 12277646Sgene.wu@arm.com#if %(use_uops)d 12287646Sgene.wu@arm.com assert(numMicroops >= 2); 12297646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 12307646Sgene.wu@arm.com if (_dest == INTREG_PC) { 12317646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 12327646Sgene.wu@arm.com _imm); 12337724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 12347646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12357724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 12367646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 12377646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12387646Sgene.wu@arm.com } else { 12397646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 12407724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 12417646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12427646Sgene.wu@arm.com uops[1]->setLastMicroop(); 12437646Sgene.wu@arm.com } 12447646Sgene.wu@arm.com#endif 12457646Sgene.wu@arm.com } 12467646Sgene.wu@arm.com}}; 12477646Sgene.wu@arm.com 1248