mem.isa revision 7597
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37120Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447205Sgblack@eecs.umich.edudef template SwapExecute {{ 457205Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 467205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 477205Sgblack@eecs.umich.edu { 487205Sgblack@eecs.umich.edu Addr EA; 497205Sgblack@eecs.umich.edu Fault fault = NoFault; 507205Sgblack@eecs.umich.edu 517205Sgblack@eecs.umich.edu %(op_decl)s; 527205Sgblack@eecs.umich.edu uint64_t memData = 0; 537205Sgblack@eecs.umich.edu %(op_rd)s; 547205Sgblack@eecs.umich.edu %(ea_code)s; 557205Sgblack@eecs.umich.edu 567205Sgblack@eecs.umich.edu if (%(predicate_test)s) 577205Sgblack@eecs.umich.edu { 587205Sgblack@eecs.umich.edu %(preacc_code)s; 597205Sgblack@eecs.umich.edu 607205Sgblack@eecs.umich.edu if (fault == NoFault) { 617205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 627205Sgblack@eecs.umich.edu EA, memAccessFlags, &memData); 637205Sgblack@eecs.umich.edu } 647205Sgblack@eecs.umich.edu 657205Sgblack@eecs.umich.edu if (fault == NoFault) { 667205Sgblack@eecs.umich.edu %(postacc_code)s; 677205Sgblack@eecs.umich.edu } 687205Sgblack@eecs.umich.edu 697205Sgblack@eecs.umich.edu if (fault == NoFault) { 707205Sgblack@eecs.umich.edu %(op_wb)s; 717205Sgblack@eecs.umich.edu } 727597Sminkyu.jeong@arm.com } else { 737597Sminkyu.jeong@arm.com xc->setPredicate(false); 747205Sgblack@eecs.umich.edu } 757205Sgblack@eecs.umich.edu 767408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 777408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 787408Sgblack@eecs.umich.edu } 797408Sgblack@eecs.umich.edu 807205Sgblack@eecs.umich.edu return fault; 817205Sgblack@eecs.umich.edu } 827205Sgblack@eecs.umich.edu}}; 837205Sgblack@eecs.umich.edu 847205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 857205Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 867205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 877205Sgblack@eecs.umich.edu { 887205Sgblack@eecs.umich.edu Addr EA; 897205Sgblack@eecs.umich.edu Fault fault = NoFault; 907205Sgblack@eecs.umich.edu 917205Sgblack@eecs.umich.edu %(op_decl)s; 927205Sgblack@eecs.umich.edu uint64_t memData = 0; 937205Sgblack@eecs.umich.edu %(op_rd)s; 947205Sgblack@eecs.umich.edu %(ea_code)s; 957205Sgblack@eecs.umich.edu 967205Sgblack@eecs.umich.edu if (%(predicate_test)s) 977205Sgblack@eecs.umich.edu { 987205Sgblack@eecs.umich.edu %(preacc_code)s; 997205Sgblack@eecs.umich.edu 1007205Sgblack@eecs.umich.edu if (fault == NoFault) { 1017205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1027205Sgblack@eecs.umich.edu memAccessFlags, &memData); 1037205Sgblack@eecs.umich.edu } 1047205Sgblack@eecs.umich.edu 1057205Sgblack@eecs.umich.edu if (fault == NoFault) { 1067205Sgblack@eecs.umich.edu %(op_wb)s; 1077205Sgblack@eecs.umich.edu } 1087597Sminkyu.jeong@arm.com } else { 1097597Sminkyu.jeong@arm.com xc->setPredicate(false); 1107205Sgblack@eecs.umich.edu } 1117205Sgblack@eecs.umich.edu 1127408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1137408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1147408Sgblack@eecs.umich.edu } 1157408Sgblack@eecs.umich.edu 1167205Sgblack@eecs.umich.edu return fault; 1177205Sgblack@eecs.umich.edu } 1187205Sgblack@eecs.umich.edu}}; 1197205Sgblack@eecs.umich.edu 1207205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1217205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1227205Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1237205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1247205Sgblack@eecs.umich.edu { 1257205Sgblack@eecs.umich.edu Fault fault = NoFault; 1267205Sgblack@eecs.umich.edu 1277205Sgblack@eecs.umich.edu %(op_decl)s; 1287205Sgblack@eecs.umich.edu %(op_rd)s; 1297205Sgblack@eecs.umich.edu 1307205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1317205Sgblack@eecs.umich.edu { 1327205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1337205Sgblack@eecs.umich.edu uint64_t memData = pkt->get<typeof(Mem)>(); 1347205Sgblack@eecs.umich.edu 1357205Sgblack@eecs.umich.edu %(postacc_code)s; 1367205Sgblack@eecs.umich.edu 1377205Sgblack@eecs.umich.edu if (fault == NoFault) { 1387205Sgblack@eecs.umich.edu %(op_wb)s; 1397205Sgblack@eecs.umich.edu } 1407205Sgblack@eecs.umich.edu } 1417205Sgblack@eecs.umich.edu 1427408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1437408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1447408Sgblack@eecs.umich.edu } 1457408Sgblack@eecs.umich.edu 1467205Sgblack@eecs.umich.edu return fault; 1477205Sgblack@eecs.umich.edu } 1487205Sgblack@eecs.umich.edu}}; 1497205Sgblack@eecs.umich.edu 1507119Sgblack@eecs.umich.edudef template LoadExecute {{ 1517119Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1527119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1537119Sgblack@eecs.umich.edu { 1547119Sgblack@eecs.umich.edu Addr EA; 1557119Sgblack@eecs.umich.edu Fault fault = NoFault; 1567119Sgblack@eecs.umich.edu 1577119Sgblack@eecs.umich.edu %(op_decl)s; 1587119Sgblack@eecs.umich.edu %(op_rd)s; 1597119Sgblack@eecs.umich.edu %(ea_code)s; 1607119Sgblack@eecs.umich.edu 1617119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1627119Sgblack@eecs.umich.edu { 1637119Sgblack@eecs.umich.edu if (fault == NoFault) { 1647119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1657119Sgblack@eecs.umich.edu %(memacc_code)s; 1667119Sgblack@eecs.umich.edu } 1677119Sgblack@eecs.umich.edu 1687119Sgblack@eecs.umich.edu if (fault == NoFault) { 1697119Sgblack@eecs.umich.edu %(op_wb)s; 1707119Sgblack@eecs.umich.edu } 1717597Sminkyu.jeong@arm.com } else { 1727597Sminkyu.jeong@arm.com xc->setPredicate(false); 1737119Sgblack@eecs.umich.edu } 1747119Sgblack@eecs.umich.edu 1757408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1767408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1777408Sgblack@eecs.umich.edu } 1787408Sgblack@eecs.umich.edu 1797119Sgblack@eecs.umich.edu return fault; 1807119Sgblack@eecs.umich.edu } 1817119Sgblack@eecs.umich.edu}}; 1827119Sgblack@eecs.umich.edu 1837120Sgblack@eecs.umich.edudef template StoreExecute {{ 1847120Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1857120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1867120Sgblack@eecs.umich.edu { 1877120Sgblack@eecs.umich.edu Addr EA; 1887120Sgblack@eecs.umich.edu Fault fault = NoFault; 1897120Sgblack@eecs.umich.edu 1907120Sgblack@eecs.umich.edu %(op_decl)s; 1917120Sgblack@eecs.umich.edu %(op_rd)s; 1927120Sgblack@eecs.umich.edu %(ea_code)s; 1937120Sgblack@eecs.umich.edu 1947120Sgblack@eecs.umich.edu if (%(predicate_test)s) 1957120Sgblack@eecs.umich.edu { 1967120Sgblack@eecs.umich.edu if (fault == NoFault) { 1977120Sgblack@eecs.umich.edu %(memacc_code)s; 1987120Sgblack@eecs.umich.edu } 1997120Sgblack@eecs.umich.edu 2007120Sgblack@eecs.umich.edu if (fault == NoFault) { 2017120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2027120Sgblack@eecs.umich.edu memAccessFlags, NULL); 2037120Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 2047120Sgblack@eecs.umich.edu } 2057120Sgblack@eecs.umich.edu 2067120Sgblack@eecs.umich.edu if (fault == NoFault) { 2077120Sgblack@eecs.umich.edu %(op_wb)s; 2087120Sgblack@eecs.umich.edu } 2097597Sminkyu.jeong@arm.com } else { 2107597Sminkyu.jeong@arm.com xc->setPredicate(false); 2117120Sgblack@eecs.umich.edu } 2127120Sgblack@eecs.umich.edu 2137408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2147408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2157408Sgblack@eecs.umich.edu } 2167408Sgblack@eecs.umich.edu 2177120Sgblack@eecs.umich.edu return fault; 2187120Sgblack@eecs.umich.edu } 2197120Sgblack@eecs.umich.edu}}; 2207120Sgblack@eecs.umich.edu 2217303Sgblack@eecs.umich.edudef template StoreExExecute {{ 2227303Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2237303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2247303Sgblack@eecs.umich.edu { 2257303Sgblack@eecs.umich.edu Addr EA; 2267303Sgblack@eecs.umich.edu Fault fault = NoFault; 2277303Sgblack@eecs.umich.edu 2287303Sgblack@eecs.umich.edu %(op_decl)s; 2297303Sgblack@eecs.umich.edu %(op_rd)s; 2307303Sgblack@eecs.umich.edu %(ea_code)s; 2317303Sgblack@eecs.umich.edu 2327303Sgblack@eecs.umich.edu if (%(predicate_test)s) 2337303Sgblack@eecs.umich.edu { 2347303Sgblack@eecs.umich.edu if (fault == NoFault) { 2357303Sgblack@eecs.umich.edu %(memacc_code)s; 2367303Sgblack@eecs.umich.edu } 2377303Sgblack@eecs.umich.edu 2387303Sgblack@eecs.umich.edu uint64_t writeResult; 2397303Sgblack@eecs.umich.edu 2407303Sgblack@eecs.umich.edu if (fault == NoFault) { 2417303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2427303Sgblack@eecs.umich.edu memAccessFlags, &writeResult); 2437303Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 2447303Sgblack@eecs.umich.edu } 2457303Sgblack@eecs.umich.edu 2467303Sgblack@eecs.umich.edu if (fault == NoFault) { 2477303Sgblack@eecs.umich.edu %(postacc_code)s; 2487303Sgblack@eecs.umich.edu } 2497303Sgblack@eecs.umich.edu 2507303Sgblack@eecs.umich.edu if (fault == NoFault) { 2517303Sgblack@eecs.umich.edu %(op_wb)s; 2527303Sgblack@eecs.umich.edu } 2537597Sminkyu.jeong@arm.com } else { 2547597Sminkyu.jeong@arm.com xc->setPredicate(false); 2557303Sgblack@eecs.umich.edu } 2567303Sgblack@eecs.umich.edu 2577408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2587408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2597408Sgblack@eecs.umich.edu } 2607408Sgblack@eecs.umich.edu 2617303Sgblack@eecs.umich.edu return fault; 2627303Sgblack@eecs.umich.edu } 2637303Sgblack@eecs.umich.edu}}; 2647303Sgblack@eecs.umich.edu 2657303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 2667303Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2677303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2687303Sgblack@eecs.umich.edu { 2697303Sgblack@eecs.umich.edu Addr EA; 2707303Sgblack@eecs.umich.edu Fault fault = NoFault; 2717303Sgblack@eecs.umich.edu 2727303Sgblack@eecs.umich.edu %(op_decl)s; 2737303Sgblack@eecs.umich.edu %(op_rd)s; 2747303Sgblack@eecs.umich.edu %(ea_code)s; 2757303Sgblack@eecs.umich.edu 2767303Sgblack@eecs.umich.edu if (%(predicate_test)s) 2777303Sgblack@eecs.umich.edu { 2787303Sgblack@eecs.umich.edu if (fault == NoFault) { 2797303Sgblack@eecs.umich.edu %(memacc_code)s; 2807303Sgblack@eecs.umich.edu } 2817303Sgblack@eecs.umich.edu 2827303Sgblack@eecs.umich.edu if (fault == NoFault) { 2837303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2847303Sgblack@eecs.umich.edu memAccessFlags, NULL); 2857303Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 2867303Sgblack@eecs.umich.edu } 2877303Sgblack@eecs.umich.edu 2887303Sgblack@eecs.umich.edu // Need to write back any potential address register update 2897303Sgblack@eecs.umich.edu if (fault == NoFault) { 2907303Sgblack@eecs.umich.edu %(op_wb)s; 2917303Sgblack@eecs.umich.edu } 2927597Sminkyu.jeong@arm.com } else { 2937597Sminkyu.jeong@arm.com xc->setPredicate(false); 2947303Sgblack@eecs.umich.edu } 2957303Sgblack@eecs.umich.edu 2967408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2977408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2987408Sgblack@eecs.umich.edu } 2997408Sgblack@eecs.umich.edu 3007303Sgblack@eecs.umich.edu return fault; 3017303Sgblack@eecs.umich.edu } 3027303Sgblack@eecs.umich.edu}}; 3037303Sgblack@eecs.umich.edu 3047120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 3057120Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3067120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3077120Sgblack@eecs.umich.edu { 3087120Sgblack@eecs.umich.edu Addr EA; 3097120Sgblack@eecs.umich.edu Fault fault = NoFault; 3107120Sgblack@eecs.umich.edu 3117120Sgblack@eecs.umich.edu %(op_decl)s; 3127120Sgblack@eecs.umich.edu %(op_rd)s; 3137120Sgblack@eecs.umich.edu %(ea_code)s; 3147120Sgblack@eecs.umich.edu 3157120Sgblack@eecs.umich.edu if (%(predicate_test)s) 3167120Sgblack@eecs.umich.edu { 3177120Sgblack@eecs.umich.edu if (fault == NoFault) { 3187120Sgblack@eecs.umich.edu %(memacc_code)s; 3197120Sgblack@eecs.umich.edu } 3207120Sgblack@eecs.umich.edu 3217120Sgblack@eecs.umich.edu if (fault == NoFault) { 3227120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3237120Sgblack@eecs.umich.edu memAccessFlags, NULL); 3247120Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 3257120Sgblack@eecs.umich.edu } 3267120Sgblack@eecs.umich.edu 3277120Sgblack@eecs.umich.edu // Need to write back any potential address register update 3287120Sgblack@eecs.umich.edu if (fault == NoFault) { 3297120Sgblack@eecs.umich.edu %(op_wb)s; 3307120Sgblack@eecs.umich.edu } 3317597Sminkyu.jeong@arm.com } else { 3327597Sminkyu.jeong@arm.com xc->setPredicate(false); 3337120Sgblack@eecs.umich.edu } 3347120Sgblack@eecs.umich.edu 3357408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 3367408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3377408Sgblack@eecs.umich.edu } 3387408Sgblack@eecs.umich.edu 3397120Sgblack@eecs.umich.edu return fault; 3407120Sgblack@eecs.umich.edu } 3417120Sgblack@eecs.umich.edu}}; 3427120Sgblack@eecs.umich.edu 3437119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 3447119Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3457119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3467119Sgblack@eecs.umich.edu { 3477119Sgblack@eecs.umich.edu Addr EA; 3487119Sgblack@eecs.umich.edu Fault fault = NoFault; 3497119Sgblack@eecs.umich.edu 3507119Sgblack@eecs.umich.edu %(op_src_decl)s; 3517119Sgblack@eecs.umich.edu %(op_rd)s; 3527119Sgblack@eecs.umich.edu %(ea_code)s; 3537119Sgblack@eecs.umich.edu 3547119Sgblack@eecs.umich.edu if (%(predicate_test)s) 3557119Sgblack@eecs.umich.edu { 3567119Sgblack@eecs.umich.edu if (fault == NoFault) { 3577119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 3587119Sgblack@eecs.umich.edu } 3597597Sminkyu.jeong@arm.com } else { 3607597Sminkyu.jeong@arm.com xc->setPredicate(false); 3617597Sminkyu.jeong@arm.com if (fault == NoFault && machInst.itstateMask != 0) { 3627597Sminkyu.jeong@arm.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3637597Sminkyu.jeong@arm.com } 3647119Sgblack@eecs.umich.edu } 3657119Sgblack@eecs.umich.edu 3667119Sgblack@eecs.umich.edu return fault; 3677119Sgblack@eecs.umich.edu } 3687119Sgblack@eecs.umich.edu}}; 3697119Sgblack@eecs.umich.edu 3707119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 3717119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 3727119Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 3737119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3747119Sgblack@eecs.umich.edu { 3757119Sgblack@eecs.umich.edu Fault fault = NoFault; 3767119Sgblack@eecs.umich.edu 3777119Sgblack@eecs.umich.edu %(op_decl)s; 3787119Sgblack@eecs.umich.edu %(op_rd)s; 3797119Sgblack@eecs.umich.edu 3807119Sgblack@eecs.umich.edu if (%(predicate_test)s) 3817119Sgblack@eecs.umich.edu { 3827119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 3837119Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 3847119Sgblack@eecs.umich.edu 3857119Sgblack@eecs.umich.edu if (fault == NoFault) { 3867119Sgblack@eecs.umich.edu %(memacc_code)s; 3877119Sgblack@eecs.umich.edu } 3887119Sgblack@eecs.umich.edu 3897119Sgblack@eecs.umich.edu if (fault == NoFault) { 3907119Sgblack@eecs.umich.edu %(op_wb)s; 3917119Sgblack@eecs.umich.edu } 3927119Sgblack@eecs.umich.edu } 3937119Sgblack@eecs.umich.edu 3947408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 3957408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3967408Sgblack@eecs.umich.edu } 3977408Sgblack@eecs.umich.edu 3987119Sgblack@eecs.umich.edu return fault; 3997119Sgblack@eecs.umich.edu } 4007119Sgblack@eecs.umich.edu}}; 4017119Sgblack@eecs.umich.edu 4027120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 4037120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 4047120Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 4057120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4067120Sgblack@eecs.umich.edu { 4077120Sgblack@eecs.umich.edu Fault fault = NoFault; 4087120Sgblack@eecs.umich.edu 4097120Sgblack@eecs.umich.edu %(op_decl)s; 4107120Sgblack@eecs.umich.edu %(op_rd)s; 4117120Sgblack@eecs.umich.edu 4127120Sgblack@eecs.umich.edu if (%(predicate_test)s) 4137120Sgblack@eecs.umich.edu { 4147120Sgblack@eecs.umich.edu if (fault == NoFault) { 4157120Sgblack@eecs.umich.edu %(op_wb)s; 4167120Sgblack@eecs.umich.edu } 4177120Sgblack@eecs.umich.edu } 4187120Sgblack@eecs.umich.edu 4197408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 4207408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4217408Sgblack@eecs.umich.edu } 4227408Sgblack@eecs.umich.edu 4237120Sgblack@eecs.umich.edu return fault; 4247120Sgblack@eecs.umich.edu } 4257120Sgblack@eecs.umich.edu}}; 4267120Sgblack@eecs.umich.edu 4277303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 4287303Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 4297303Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 4307303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4317303Sgblack@eecs.umich.edu { 4327303Sgblack@eecs.umich.edu Fault fault = NoFault; 4337303Sgblack@eecs.umich.edu 4347303Sgblack@eecs.umich.edu %(op_decl)s; 4357303Sgblack@eecs.umich.edu %(op_rd)s; 4367303Sgblack@eecs.umich.edu 4377303Sgblack@eecs.umich.edu if (%(predicate_test)s) 4387303Sgblack@eecs.umich.edu { 4397303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 4407303Sgblack@eecs.umich.edu %(postacc_code)s; 4417303Sgblack@eecs.umich.edu 4427303Sgblack@eecs.umich.edu if (fault == NoFault) { 4437303Sgblack@eecs.umich.edu %(op_wb)s; 4447303Sgblack@eecs.umich.edu } 4457303Sgblack@eecs.umich.edu } 4467303Sgblack@eecs.umich.edu 4477408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 4487408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4497408Sgblack@eecs.umich.edu } 4507408Sgblack@eecs.umich.edu 4517303Sgblack@eecs.umich.edu return fault; 4527303Sgblack@eecs.umich.edu } 4537303Sgblack@eecs.umich.edu}}; 4547303Sgblack@eecs.umich.edu 4557291Sgblack@eecs.umich.edudef template RfeDeclare {{ 4567291Sgblack@eecs.umich.edu /** 4577291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 4587291Sgblack@eecs.umich.edu */ 4597291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 4607291Sgblack@eecs.umich.edu { 4617291Sgblack@eecs.umich.edu public: 4627291Sgblack@eecs.umich.edu 4637291Sgblack@eecs.umich.edu /// Constructor. 4647291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 4657291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 4667291Sgblack@eecs.umich.edu 4677291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 4687291Sgblack@eecs.umich.edu 4697291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 4707291Sgblack@eecs.umich.edu 4717291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 4727291Sgblack@eecs.umich.edu }; 4737291Sgblack@eecs.umich.edu}}; 4747291Sgblack@eecs.umich.edu 4757312Sgblack@eecs.umich.edudef template SrsDeclare {{ 4767312Sgblack@eecs.umich.edu /** 4777312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 4787312Sgblack@eecs.umich.edu */ 4797312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 4807312Sgblack@eecs.umich.edu { 4817312Sgblack@eecs.umich.edu public: 4827312Sgblack@eecs.umich.edu 4837312Sgblack@eecs.umich.edu /// Constructor. 4847312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 4857312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 4867312Sgblack@eecs.umich.edu 4877312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 4887312Sgblack@eecs.umich.edu 4897312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 4907312Sgblack@eecs.umich.edu 4917312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 4927312Sgblack@eecs.umich.edu }; 4937312Sgblack@eecs.umich.edu}}; 4947312Sgblack@eecs.umich.edu 4957205Sgblack@eecs.umich.edudef template SwapDeclare {{ 4967205Sgblack@eecs.umich.edu /** 4977205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 4987205Sgblack@eecs.umich.edu */ 4997205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5007205Sgblack@eecs.umich.edu { 5017205Sgblack@eecs.umich.edu public: 5027205Sgblack@eecs.umich.edu 5037205Sgblack@eecs.umich.edu /// Constructor. 5047205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5057205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 5067205Sgblack@eecs.umich.edu 5077205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5087205Sgblack@eecs.umich.edu 5097205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5107205Sgblack@eecs.umich.edu 5117205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5127205Sgblack@eecs.umich.edu }; 5137205Sgblack@eecs.umich.edu}}; 5147205Sgblack@eecs.umich.edu 5157279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 5167279Sgblack@eecs.umich.edu /** 5177279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5187279Sgblack@eecs.umich.edu */ 5197279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5207279Sgblack@eecs.umich.edu { 5217279Sgblack@eecs.umich.edu public: 5227279Sgblack@eecs.umich.edu 5237279Sgblack@eecs.umich.edu /// Constructor. 5247279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5257279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 5267279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 5277279Sgblack@eecs.umich.edu 5287279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5297279Sgblack@eecs.umich.edu 5307279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5317279Sgblack@eecs.umich.edu 5327279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5337279Sgblack@eecs.umich.edu }; 5347279Sgblack@eecs.umich.edu}}; 5357279Sgblack@eecs.umich.edu 5367303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 5377303Sgblack@eecs.umich.edu /** 5387303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5397303Sgblack@eecs.umich.edu */ 5407303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5417303Sgblack@eecs.umich.edu { 5427303Sgblack@eecs.umich.edu public: 5437303Sgblack@eecs.umich.edu 5447303Sgblack@eecs.umich.edu /// Constructor. 5457303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5467303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 5477303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 5487303Sgblack@eecs.umich.edu 5497303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5507303Sgblack@eecs.umich.edu 5517303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5527303Sgblack@eecs.umich.edu 5537303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5547303Sgblack@eecs.umich.edu }; 5557303Sgblack@eecs.umich.edu}}; 5567303Sgblack@eecs.umich.edu 5577119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 5587119Sgblack@eecs.umich.edu /** 5597119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5607119Sgblack@eecs.umich.edu */ 5617119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5627119Sgblack@eecs.umich.edu { 5637119Sgblack@eecs.umich.edu public: 5647119Sgblack@eecs.umich.edu 5657119Sgblack@eecs.umich.edu /// Constructor. 5667119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5677119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 5687119Sgblack@eecs.umich.edu 5697119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5707119Sgblack@eecs.umich.edu 5717119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5727119Sgblack@eecs.umich.edu 5737119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5747119Sgblack@eecs.umich.edu }; 5757119Sgblack@eecs.umich.edu}}; 5767119Sgblack@eecs.umich.edu 5777303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 5787303Sgblack@eecs.umich.edu /** 5797303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5807303Sgblack@eecs.umich.edu */ 5817303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5827303Sgblack@eecs.umich.edu { 5837303Sgblack@eecs.umich.edu public: 5847303Sgblack@eecs.umich.edu 5857303Sgblack@eecs.umich.edu /// Constructor. 5867303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5877303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 5887303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 5897303Sgblack@eecs.umich.edu 5907303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5917303Sgblack@eecs.umich.edu 5927303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5937303Sgblack@eecs.umich.edu 5947303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5957303Sgblack@eecs.umich.edu }; 5967303Sgblack@eecs.umich.edu}}; 5977303Sgblack@eecs.umich.edu 5987279Sgblack@eecs.umich.edudef template LoadStoreDRegDeclare {{ 5997279Sgblack@eecs.umich.edu /** 6007279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6017279Sgblack@eecs.umich.edu */ 6027279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6037279Sgblack@eecs.umich.edu { 6047279Sgblack@eecs.umich.edu public: 6057279Sgblack@eecs.umich.edu 6067279Sgblack@eecs.umich.edu /// Constructor. 6077279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6087279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6097279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 6107279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 6117279Sgblack@eecs.umich.edu uint32_t _index); 6127279Sgblack@eecs.umich.edu 6137279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6147279Sgblack@eecs.umich.edu 6157279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6167279Sgblack@eecs.umich.edu 6177279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6187279Sgblack@eecs.umich.edu }; 6197279Sgblack@eecs.umich.edu}}; 6207279Sgblack@eecs.umich.edu 6217119Sgblack@eecs.umich.edudef template LoadStoreRegDeclare {{ 6227119Sgblack@eecs.umich.edu /** 6237119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6247119Sgblack@eecs.umich.edu */ 6257119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6267119Sgblack@eecs.umich.edu { 6277119Sgblack@eecs.umich.edu public: 6287119Sgblack@eecs.umich.edu 6297119Sgblack@eecs.umich.edu /// Constructor. 6307119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6317119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 6327119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 6337119Sgblack@eecs.umich.edu uint32_t _index); 6347119Sgblack@eecs.umich.edu 6357119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6367119Sgblack@eecs.umich.edu 6377119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6387119Sgblack@eecs.umich.edu 6397119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6407119Sgblack@eecs.umich.edu }; 6417119Sgblack@eecs.umich.edu}}; 6427119Sgblack@eecs.umich.edu 6437119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 6447119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 6457119Sgblack@eecs.umich.edu}}; 6467119Sgblack@eecs.umich.edu 6477119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 6487119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 6497119Sgblack@eecs.umich.edu}}; 6507119Sgblack@eecs.umich.edu 6517291Sgblack@eecs.umich.edudef template RfeConstructor {{ 6527291Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6537291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb) 6547291Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6557291Sgblack@eecs.umich.edu (IntRegIndex)_base, (AddrMode)_mode, _wb) 6567291Sgblack@eecs.umich.edu { 6577291Sgblack@eecs.umich.edu %(constructor)s; 6587291Sgblack@eecs.umich.edu } 6597291Sgblack@eecs.umich.edu}}; 6607291Sgblack@eecs.umich.edu 6617312Sgblack@eecs.umich.edudef template SrsConstructor {{ 6627312Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6637312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 6647312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6657312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 6667312Sgblack@eecs.umich.edu { 6677312Sgblack@eecs.umich.edu %(constructor)s; 6687312Sgblack@eecs.umich.edu } 6697312Sgblack@eecs.umich.edu}}; 6707312Sgblack@eecs.umich.edu 6717205Sgblack@eecs.umich.edudef template SwapConstructor {{ 6727205Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6737205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 6747205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6757205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 6767205Sgblack@eecs.umich.edu { 6777205Sgblack@eecs.umich.edu %(constructor)s; 6787205Sgblack@eecs.umich.edu } 6797205Sgblack@eecs.umich.edu}}; 6807205Sgblack@eecs.umich.edu 6817279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 6827279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6837279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6847279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 6857279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6867279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 6877279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 6887279Sgblack@eecs.umich.edu { 6897279Sgblack@eecs.umich.edu %(constructor)s; 6907279Sgblack@eecs.umich.edu } 6917279Sgblack@eecs.umich.edu}}; 6927279Sgblack@eecs.umich.edu 6937303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 6947303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6957303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 6967303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 6977303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6987303Sgblack@eecs.umich.edu (IntRegIndex)_result, 6997303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 7007303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 7017303Sgblack@eecs.umich.edu { 7027303Sgblack@eecs.umich.edu %(constructor)s; 7037303Sgblack@eecs.umich.edu } 7047303Sgblack@eecs.umich.edu}}; 7057303Sgblack@eecs.umich.edu 7067119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 7077119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 7087119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 7097119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 7107119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 7117119Sgblack@eecs.umich.edu { 7127119Sgblack@eecs.umich.edu %(constructor)s; 7137119Sgblack@eecs.umich.edu } 7147119Sgblack@eecs.umich.edu}}; 7157119Sgblack@eecs.umich.edu 7167303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 7177303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 7187303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7197303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 7207303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 7217303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 7227303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 7237303Sgblack@eecs.umich.edu { 7247303Sgblack@eecs.umich.edu %(constructor)s; 7257303Sgblack@eecs.umich.edu } 7267303Sgblack@eecs.umich.edu}}; 7277303Sgblack@eecs.umich.edu 7287279Sgblack@eecs.umich.edudef template LoadStoreDRegConstructor {{ 7297279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 7307279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 7317279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 7327279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 7337279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 7347279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 7357279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 7367279Sgblack@eecs.umich.edu (IntRegIndex)_index) 7377279Sgblack@eecs.umich.edu { 7387279Sgblack@eecs.umich.edu %(constructor)s; 7397279Sgblack@eecs.umich.edu } 7407279Sgblack@eecs.umich.edu}}; 7417279Sgblack@eecs.umich.edu 7427119Sgblack@eecs.umich.edudef template LoadStoreRegConstructor {{ 7437119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 7447119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 7457119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 7467119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 7477119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 7487119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 7497119Sgblack@eecs.umich.edu (IntRegIndex)_index) 7507119Sgblack@eecs.umich.edu { 7517119Sgblack@eecs.umich.edu %(constructor)s; 7527119Sgblack@eecs.umich.edu } 7537119Sgblack@eecs.umich.edu}}; 754