mem.isa revision 7279
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37120Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447205Sgblack@eecs.umich.edudef template SwapExecute {{ 457205Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 467205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 477205Sgblack@eecs.umich.edu { 487205Sgblack@eecs.umich.edu Addr EA; 497205Sgblack@eecs.umich.edu Fault fault = NoFault; 507205Sgblack@eecs.umich.edu 517205Sgblack@eecs.umich.edu %(op_decl)s; 527205Sgblack@eecs.umich.edu uint64_t memData = 0; 537205Sgblack@eecs.umich.edu %(op_rd)s; 547205Sgblack@eecs.umich.edu %(ea_code)s; 557205Sgblack@eecs.umich.edu 567205Sgblack@eecs.umich.edu if (%(predicate_test)s) 577205Sgblack@eecs.umich.edu { 587205Sgblack@eecs.umich.edu %(preacc_code)s; 597205Sgblack@eecs.umich.edu 607205Sgblack@eecs.umich.edu if (fault == NoFault) { 617205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 627205Sgblack@eecs.umich.edu EA, memAccessFlags, &memData); 637205Sgblack@eecs.umich.edu } 647205Sgblack@eecs.umich.edu 657205Sgblack@eecs.umich.edu if (fault == NoFault) { 667205Sgblack@eecs.umich.edu %(postacc_code)s; 677205Sgblack@eecs.umich.edu } 687205Sgblack@eecs.umich.edu 697205Sgblack@eecs.umich.edu if (fault == NoFault) { 707205Sgblack@eecs.umich.edu %(op_wb)s; 717205Sgblack@eecs.umich.edu } 727205Sgblack@eecs.umich.edu } 737205Sgblack@eecs.umich.edu 747205Sgblack@eecs.umich.edu return fault; 757205Sgblack@eecs.umich.edu } 767205Sgblack@eecs.umich.edu}}; 777205Sgblack@eecs.umich.edu 787205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 797205Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 807205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 817205Sgblack@eecs.umich.edu { 827205Sgblack@eecs.umich.edu Addr EA; 837205Sgblack@eecs.umich.edu Fault fault = NoFault; 847205Sgblack@eecs.umich.edu 857205Sgblack@eecs.umich.edu %(op_decl)s; 867205Sgblack@eecs.umich.edu uint64_t memData = 0; 877205Sgblack@eecs.umich.edu %(op_rd)s; 887205Sgblack@eecs.umich.edu %(ea_code)s; 897205Sgblack@eecs.umich.edu 907205Sgblack@eecs.umich.edu if (%(predicate_test)s) 917205Sgblack@eecs.umich.edu { 927205Sgblack@eecs.umich.edu %(preacc_code)s; 937205Sgblack@eecs.umich.edu 947205Sgblack@eecs.umich.edu if (fault == NoFault) { 957205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 967205Sgblack@eecs.umich.edu memAccessFlags, &memData); 977205Sgblack@eecs.umich.edu } 987205Sgblack@eecs.umich.edu 997205Sgblack@eecs.umich.edu if (fault == NoFault) { 1007205Sgblack@eecs.umich.edu %(op_wb)s; 1017205Sgblack@eecs.umich.edu } 1027205Sgblack@eecs.umich.edu } 1037205Sgblack@eecs.umich.edu 1047205Sgblack@eecs.umich.edu return fault; 1057205Sgblack@eecs.umich.edu } 1067205Sgblack@eecs.umich.edu}}; 1077205Sgblack@eecs.umich.edu 1087205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1097205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1107205Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1117205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1127205Sgblack@eecs.umich.edu { 1137205Sgblack@eecs.umich.edu Fault fault = NoFault; 1147205Sgblack@eecs.umich.edu 1157205Sgblack@eecs.umich.edu %(op_decl)s; 1167205Sgblack@eecs.umich.edu %(op_rd)s; 1177205Sgblack@eecs.umich.edu 1187205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1197205Sgblack@eecs.umich.edu { 1207205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1217205Sgblack@eecs.umich.edu uint64_t memData = pkt->get<typeof(Mem)>(); 1227205Sgblack@eecs.umich.edu 1237205Sgblack@eecs.umich.edu %(postacc_code)s; 1247205Sgblack@eecs.umich.edu 1257205Sgblack@eecs.umich.edu if (fault == NoFault) { 1267205Sgblack@eecs.umich.edu %(op_wb)s; 1277205Sgblack@eecs.umich.edu } 1287205Sgblack@eecs.umich.edu } 1297205Sgblack@eecs.umich.edu 1307205Sgblack@eecs.umich.edu return fault; 1317205Sgblack@eecs.umich.edu } 1327205Sgblack@eecs.umich.edu}}; 1337205Sgblack@eecs.umich.edu 1347119Sgblack@eecs.umich.edudef template LoadExecute {{ 1357119Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1367119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1377119Sgblack@eecs.umich.edu { 1387119Sgblack@eecs.umich.edu Addr EA; 1397119Sgblack@eecs.umich.edu Fault fault = NoFault; 1407119Sgblack@eecs.umich.edu 1417119Sgblack@eecs.umich.edu %(op_decl)s; 1427119Sgblack@eecs.umich.edu %(op_rd)s; 1437119Sgblack@eecs.umich.edu %(ea_code)s; 1447119Sgblack@eecs.umich.edu 1457119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1467119Sgblack@eecs.umich.edu { 1477119Sgblack@eecs.umich.edu if (fault == NoFault) { 1487119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1497119Sgblack@eecs.umich.edu %(memacc_code)s; 1507119Sgblack@eecs.umich.edu } 1517119Sgblack@eecs.umich.edu 1527119Sgblack@eecs.umich.edu if (fault == NoFault) { 1537119Sgblack@eecs.umich.edu %(op_wb)s; 1547119Sgblack@eecs.umich.edu } 1557119Sgblack@eecs.umich.edu } 1567119Sgblack@eecs.umich.edu 1577119Sgblack@eecs.umich.edu return fault; 1587119Sgblack@eecs.umich.edu } 1597119Sgblack@eecs.umich.edu}}; 1607119Sgblack@eecs.umich.edu 1617120Sgblack@eecs.umich.edudef template StoreExecute {{ 1627120Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1637120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1647120Sgblack@eecs.umich.edu { 1657120Sgblack@eecs.umich.edu Addr EA; 1667120Sgblack@eecs.umich.edu Fault fault = NoFault; 1677120Sgblack@eecs.umich.edu 1687120Sgblack@eecs.umich.edu %(op_decl)s; 1697120Sgblack@eecs.umich.edu %(op_rd)s; 1707120Sgblack@eecs.umich.edu %(ea_code)s; 1717120Sgblack@eecs.umich.edu 1727120Sgblack@eecs.umich.edu if (%(predicate_test)s) 1737120Sgblack@eecs.umich.edu { 1747120Sgblack@eecs.umich.edu if (fault == NoFault) { 1757120Sgblack@eecs.umich.edu %(memacc_code)s; 1767120Sgblack@eecs.umich.edu } 1777120Sgblack@eecs.umich.edu 1787120Sgblack@eecs.umich.edu if (fault == NoFault) { 1797120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1807120Sgblack@eecs.umich.edu memAccessFlags, NULL); 1817120Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 1827120Sgblack@eecs.umich.edu } 1837120Sgblack@eecs.umich.edu 1847120Sgblack@eecs.umich.edu if (fault == NoFault) { 1857120Sgblack@eecs.umich.edu %(op_wb)s; 1867120Sgblack@eecs.umich.edu } 1877120Sgblack@eecs.umich.edu } 1887120Sgblack@eecs.umich.edu 1897120Sgblack@eecs.umich.edu return fault; 1907120Sgblack@eecs.umich.edu } 1917120Sgblack@eecs.umich.edu}}; 1927120Sgblack@eecs.umich.edu 1937120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 1947120Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1957120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1967120Sgblack@eecs.umich.edu { 1977120Sgblack@eecs.umich.edu Addr EA; 1987120Sgblack@eecs.umich.edu Fault fault = NoFault; 1997120Sgblack@eecs.umich.edu 2007120Sgblack@eecs.umich.edu %(op_decl)s; 2017120Sgblack@eecs.umich.edu %(op_rd)s; 2027120Sgblack@eecs.umich.edu %(ea_code)s; 2037120Sgblack@eecs.umich.edu 2047120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2057120Sgblack@eecs.umich.edu { 2067120Sgblack@eecs.umich.edu if (fault == NoFault) { 2077120Sgblack@eecs.umich.edu %(memacc_code)s; 2087120Sgblack@eecs.umich.edu } 2097120Sgblack@eecs.umich.edu 2107120Sgblack@eecs.umich.edu if (fault == NoFault) { 2117120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2127120Sgblack@eecs.umich.edu memAccessFlags, NULL); 2137120Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 2147120Sgblack@eecs.umich.edu } 2157120Sgblack@eecs.umich.edu 2167120Sgblack@eecs.umich.edu // Need to write back any potential address register update 2177120Sgblack@eecs.umich.edu if (fault == NoFault) { 2187120Sgblack@eecs.umich.edu %(op_wb)s; 2197120Sgblack@eecs.umich.edu } 2207120Sgblack@eecs.umich.edu } 2217120Sgblack@eecs.umich.edu 2227120Sgblack@eecs.umich.edu return fault; 2237120Sgblack@eecs.umich.edu } 2247120Sgblack@eecs.umich.edu}}; 2257120Sgblack@eecs.umich.edu 2267119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 2277119Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2287119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2297119Sgblack@eecs.umich.edu { 2307119Sgblack@eecs.umich.edu Addr EA; 2317119Sgblack@eecs.umich.edu Fault fault = NoFault; 2327119Sgblack@eecs.umich.edu 2337119Sgblack@eecs.umich.edu %(op_src_decl)s; 2347119Sgblack@eecs.umich.edu %(op_rd)s; 2357119Sgblack@eecs.umich.edu %(ea_code)s; 2367119Sgblack@eecs.umich.edu 2377119Sgblack@eecs.umich.edu if (%(predicate_test)s) 2387119Sgblack@eecs.umich.edu { 2397119Sgblack@eecs.umich.edu if (fault == NoFault) { 2407119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 2417119Sgblack@eecs.umich.edu } 2427119Sgblack@eecs.umich.edu } 2437119Sgblack@eecs.umich.edu 2447119Sgblack@eecs.umich.edu return fault; 2457119Sgblack@eecs.umich.edu } 2467119Sgblack@eecs.umich.edu}}; 2477119Sgblack@eecs.umich.edu 2487119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 2497119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 2507119Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 2517119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2527119Sgblack@eecs.umich.edu { 2537119Sgblack@eecs.umich.edu Fault fault = NoFault; 2547119Sgblack@eecs.umich.edu 2557119Sgblack@eecs.umich.edu %(op_decl)s; 2567119Sgblack@eecs.umich.edu %(op_rd)s; 2577119Sgblack@eecs.umich.edu 2587119Sgblack@eecs.umich.edu if (%(predicate_test)s) 2597119Sgblack@eecs.umich.edu { 2607119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 2617119Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 2627119Sgblack@eecs.umich.edu 2637119Sgblack@eecs.umich.edu if (fault == NoFault) { 2647119Sgblack@eecs.umich.edu %(memacc_code)s; 2657119Sgblack@eecs.umich.edu } 2667119Sgblack@eecs.umich.edu 2677119Sgblack@eecs.umich.edu if (fault == NoFault) { 2687119Sgblack@eecs.umich.edu %(op_wb)s; 2697119Sgblack@eecs.umich.edu } 2707119Sgblack@eecs.umich.edu } 2717119Sgblack@eecs.umich.edu 2727119Sgblack@eecs.umich.edu return fault; 2737119Sgblack@eecs.umich.edu } 2747119Sgblack@eecs.umich.edu}}; 2757119Sgblack@eecs.umich.edu 2767120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 2777120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 2787120Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 2797120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2807120Sgblack@eecs.umich.edu { 2817120Sgblack@eecs.umich.edu Fault fault = NoFault; 2827120Sgblack@eecs.umich.edu 2837120Sgblack@eecs.umich.edu %(op_decl)s; 2847120Sgblack@eecs.umich.edu %(op_rd)s; 2857120Sgblack@eecs.umich.edu 2867120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2877120Sgblack@eecs.umich.edu { 2887120Sgblack@eecs.umich.edu if (fault == NoFault) { 2897120Sgblack@eecs.umich.edu %(op_wb)s; 2907120Sgblack@eecs.umich.edu } 2917120Sgblack@eecs.umich.edu } 2927120Sgblack@eecs.umich.edu 2937120Sgblack@eecs.umich.edu return fault; 2947120Sgblack@eecs.umich.edu } 2957120Sgblack@eecs.umich.edu}}; 2967120Sgblack@eecs.umich.edu 2977205Sgblack@eecs.umich.edudef template SwapDeclare {{ 2987205Sgblack@eecs.umich.edu /** 2997205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3007205Sgblack@eecs.umich.edu */ 3017205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3027205Sgblack@eecs.umich.edu { 3037205Sgblack@eecs.umich.edu public: 3047205Sgblack@eecs.umich.edu 3057205Sgblack@eecs.umich.edu /// Constructor. 3067205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3077205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 3087205Sgblack@eecs.umich.edu 3097205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3107205Sgblack@eecs.umich.edu 3117205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3127205Sgblack@eecs.umich.edu 3137205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3147205Sgblack@eecs.umich.edu }; 3157205Sgblack@eecs.umich.edu}}; 3167205Sgblack@eecs.umich.edu 3177279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 3187279Sgblack@eecs.umich.edu /** 3197279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3207279Sgblack@eecs.umich.edu */ 3217279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3227279Sgblack@eecs.umich.edu { 3237279Sgblack@eecs.umich.edu public: 3247279Sgblack@eecs.umich.edu 3257279Sgblack@eecs.umich.edu /// Constructor. 3267279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3277279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 3287279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 3297279Sgblack@eecs.umich.edu 3307279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3317279Sgblack@eecs.umich.edu 3327279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3337279Sgblack@eecs.umich.edu 3347279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3357279Sgblack@eecs.umich.edu }; 3367279Sgblack@eecs.umich.edu}}; 3377279Sgblack@eecs.umich.edu 3387119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 3397119Sgblack@eecs.umich.edu /** 3407119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3417119Sgblack@eecs.umich.edu */ 3427119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3437119Sgblack@eecs.umich.edu { 3447119Sgblack@eecs.umich.edu public: 3457119Sgblack@eecs.umich.edu 3467119Sgblack@eecs.umich.edu /// Constructor. 3477119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3487119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 3497119Sgblack@eecs.umich.edu 3507119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3517119Sgblack@eecs.umich.edu 3527119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3537119Sgblack@eecs.umich.edu 3547119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3557119Sgblack@eecs.umich.edu }; 3567119Sgblack@eecs.umich.edu}}; 3577119Sgblack@eecs.umich.edu 3587279Sgblack@eecs.umich.edudef template LoadStoreDRegDeclare {{ 3597279Sgblack@eecs.umich.edu /** 3607279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3617279Sgblack@eecs.umich.edu */ 3627279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3637279Sgblack@eecs.umich.edu { 3647279Sgblack@eecs.umich.edu public: 3657279Sgblack@eecs.umich.edu 3667279Sgblack@eecs.umich.edu /// Constructor. 3677279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3687279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 3697279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 3707279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 3717279Sgblack@eecs.umich.edu uint32_t _index); 3727279Sgblack@eecs.umich.edu 3737279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3747279Sgblack@eecs.umich.edu 3757279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3767279Sgblack@eecs.umich.edu 3777279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3787279Sgblack@eecs.umich.edu }; 3797279Sgblack@eecs.umich.edu}}; 3807279Sgblack@eecs.umich.edu 3817119Sgblack@eecs.umich.edudef template LoadStoreRegDeclare {{ 3827119Sgblack@eecs.umich.edu /** 3837119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3847119Sgblack@eecs.umich.edu */ 3857119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3867119Sgblack@eecs.umich.edu { 3877119Sgblack@eecs.umich.edu public: 3887119Sgblack@eecs.umich.edu 3897119Sgblack@eecs.umich.edu /// Constructor. 3907119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3917119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 3927119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 3937119Sgblack@eecs.umich.edu uint32_t _index); 3947119Sgblack@eecs.umich.edu 3957119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3967119Sgblack@eecs.umich.edu 3977119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3987119Sgblack@eecs.umich.edu 3997119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 4007119Sgblack@eecs.umich.edu }; 4017119Sgblack@eecs.umich.edu}}; 4027119Sgblack@eecs.umich.edu 4037119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 4047119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 4057119Sgblack@eecs.umich.edu}}; 4067119Sgblack@eecs.umich.edu 4077119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 4087119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 4097119Sgblack@eecs.umich.edu}}; 4107119Sgblack@eecs.umich.edu 4117205Sgblack@eecs.umich.edudef template SwapConstructor {{ 4127205Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 4137205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 4147205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4157205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 4167205Sgblack@eecs.umich.edu { 4177205Sgblack@eecs.umich.edu %(constructor)s; 4187205Sgblack@eecs.umich.edu } 4197205Sgblack@eecs.umich.edu}}; 4207205Sgblack@eecs.umich.edu 4217279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 4227279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 4237279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 4247279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 4257279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4267279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 4277279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 4287279Sgblack@eecs.umich.edu { 4297279Sgblack@eecs.umich.edu %(constructor)s; 4307279Sgblack@eecs.umich.edu } 4317279Sgblack@eecs.umich.edu}}; 4327279Sgblack@eecs.umich.edu 4337119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 4347119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 4357119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 4367119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4377119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 4387119Sgblack@eecs.umich.edu { 4397119Sgblack@eecs.umich.edu %(constructor)s; 4407119Sgblack@eecs.umich.edu } 4417119Sgblack@eecs.umich.edu}}; 4427119Sgblack@eecs.umich.edu 4437279Sgblack@eecs.umich.edudef template LoadStoreDRegConstructor {{ 4447279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 4457279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 4467279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 4477279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4487279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 4497279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 4507279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 4517279Sgblack@eecs.umich.edu (IntRegIndex)_index) 4527279Sgblack@eecs.umich.edu { 4537279Sgblack@eecs.umich.edu %(constructor)s; 4547279Sgblack@eecs.umich.edu } 4557279Sgblack@eecs.umich.edu}}; 4567279Sgblack@eecs.umich.edu 4577119Sgblack@eecs.umich.edudef template LoadStoreRegConstructor {{ 4587119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 4597119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 4607119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 4617119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4627119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 4637119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 4647119Sgblack@eecs.umich.edu (IntRegIndex)_index) 4657119Sgblack@eecs.umich.edu { 4667119Sgblack@eecs.umich.edu %(constructor)s; 4677119Sgblack@eecs.umich.edu } 4687119Sgblack@eecs.umich.edu}}; 469